CN114665709B - Light-load efficient step-down circuit - Google Patents
Light-load efficient step-down circuit Download PDFInfo
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- CN114665709B CN114665709B CN202210336601.4A CN202210336601A CN114665709B CN 114665709 B CN114665709 B CN 114665709B CN 202210336601 A CN202210336601 A CN 202210336601A CN 114665709 B CN114665709 B CN 114665709B
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- 239000003990 capacitor Substances 0.000 claims description 20
- 238000001514 detection method Methods 0.000 claims description 14
- 230000010355 oscillation Effects 0.000 claims description 3
- 238000005070 sampling Methods 0.000 claims description 2
- 239000000523 sample Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000013074 reference sample Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
Abstract
The invention provides a light-load efficient voltage-reducing circuit, which comprises a voltage-reducing circuit, wherein the voltage-reducing circuit is electrically connected with a light-load judging circuit; the light load judging circuit comprises a low-power-consumption voltage dividing resistor network, the voltage dividing resistor network is electrically connected with the in-phase input end of a light load comparator, the reverse-phase input end of the light load comparator is electrically connected with the voltage reducing circuit, the output end of the light load comparator is connected with an NOT gate and an AND gate in parallel, the NOT gate is electrically connected with an OR gate, the OR gate is electrically connected with the voltage reducing circuit, the AND gate is electrically connected with a zero current time judging module, the zero current time judging module is electrically connected with the voltage reducing circuit, the AND gate is electrically connected with a low-power-consumption oscillator, the low-power-consumption oscillator is electrically connected with a band gap reference mode, and the band gap reference mode is electrically connected with a sample hold circuit.
Description
Technical Field
The invention belongs to the technical field of voltage reduction circuits, and particularly relates to a light-load efficient voltage reduction circuit.
Background
Currently, in a step-down circuit of a conventional structure, the quiescent current is typically several tens of microamps, and the efficiency is typically less than 25% under light load conditions, such as 10uA loading. The low light load efficiency is determined by the architecture of the conventional circuit, which is shown in fig. 1.
For conventional circuits, substantially all of the modules are still operating even in idle mode, so even if efforts are made to reduce the quiescent current of each module, its total quiescent power consumption is typically above 30uA, which determines that it is unlikely to be very efficient under light loads.
However, in applications such as wearable, internet of things and battery power supply, the smaller the standby power consumption of the power supply is, the better the standby power consumption is, and the higher the light load efficiency is. The conventional step-down circuit cannot meet the requirements.
The invention provides a novel low-power-consumption architecture, and the standby power consumption of a chip under no load is about 300nA, which is only 1% of that of a traditional circuit. Thus greatly improving the standby time of the battery.
Disclosure of Invention
The invention provides a light-load efficient voltage reduction circuit, which solves the problems in the prior art.
The technical scheme of the invention is realized as follows: the light load efficient voltage reduction circuit comprises a voltage reduction circuit, wherein the voltage reduction circuit is electrically connected with a light load judging circuit;
the light load judging circuit comprises a low-power-consumption voltage dividing resistor network, the voltage dividing resistor network is electrically connected with an in-phase input end of a light load comparator, an inverting input end of the light load comparator is electrically connected with the voltage reducing circuit, an output end of the light load comparator is connected with an NOT gate and an AND gate in parallel, the NOT gate is electrically connected with an OR gate, the OR gate is electrically connected with the voltage reducing circuit, the AND gate is electrically connected with a zero current time judging module, the zero current time judging module is electrically connected with the voltage reducing circuit, the AND gate is electrically connected with a low-power-consumption oscillator, the low-power-consumption oscillator is electrically connected with a band gap reference mode, the band gap reference mode is electrically connected with a sample hold circuit, and the sample hold circuit is electrically connected between the inverting input end of the light load comparator and the voltage reducing circuit.
As a preferred implementation mode, the voltage reduction circuit comprises a voltage division circuit network and an SW voltage division network, wherein an error amplifier is electrically connected to the voltage division circuit network, a PWM comparator is electrically connected to the SW voltage division network, the error amplifier is electrically connected to the PWM comparator, the PWM comparator is electrically connected to an OR gate, the OR gate is electrically connected to a processor, the processor is electrically connected to a driving pulse, the driving pulse is respectively electrically connected to an MOS tube MP and an MOS tube MN, the MOS tube MP is electrically connected to the MOS tube MN, an inductor is electrically connected between the MOS tube MP and the MOS tube MN, a resistor R0 and a capacitor R0 are connected to the other end of the inductor in parallel, and the resistor R0 and the capacitor R0 are grounded.
As a preferred embodiment, the voltage divider circuit network includes a resistor Rf1 and a resistor Rf2 connected in series, a switch S1 is electrically connected between the resistor Rf1 and the power input terminal, a switch S2 is electrically connected to the resistor Rf2, an inverting input terminal of the error amplifier is electrically connected between the resistor Rf1 and the resistor Rf2, and a non-inverting input terminal of the error amplifier is electrically connected to an inverting input terminal of the light load comparator.
As a preferred implementation manner, the SW voltage dividing network comprises a resistor R1 and a resistor R2 which are connected in series, wherein a switch S3 is electrically connected to the resistor R1, an inverting input end of the PWM comparator is electrically connected between the resistor R1 and the resistor R2, the resistor R2 is grounded, a capacitor C1 is electrically connected to a grounding end of the resistor R2, the other end of the capacitor C1 is electrically connected to an inverting input end of the PWM comparator, a non-inverting input end of the PWM comparator is electrically connected to an output end of the light load comparator, and an output end of the PWM comparator is electrically connected to an OR gate.
As a preferred embodiment, the voltage dividing resistor network includes a voltage dividing resistor Rf3 and a voltage dividing resistor Rf4 connected in series, and the non-inverting input terminal of the light load comparator is electrically connected between the voltage dividing resistor Rf3 and the voltage dividing resistor Rf 4.
As a preferred embodiment, the R pin and the S pin of the processor are respectively electrically connected with an OR gate and a timer, and the Q pin and the timer of the processorThe pins are respectively electrically connected with the driving pulses.
As a preferred embodiment, the driving pulse DRV is connected to the gate of the MOS transistor MP through the hsd_gt signal, and the driving pulse DRV is connected to the gate of the MOS transistor MN through the lsd_gt signal.
After the technical scheme is adopted, the invention has the beneficial effects that:
when the load is detected to be light-load, the vast majority of circuits are turned off, only the light-load comparator and the low-power-consumption oscillator module are kept to work, and meanwhile, the oscillator is used for periodically and intermittently starting the band-gap reference circuit and the reference sample hold circuit, so that the power consumption can be greatly reduced.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a schematic circuit diagram of the background of the invention;
FIG. 2 is a circuit diagram of the present invention;
FIG. 3 is a schematic diagram of an OSC period;
FIG. 4 is a timing diagram showing the OSC output signal being high;
fig. 5 is a schematic diagram of input current and output ripple.
In the figure, rf 1-resistance; rf 2-resistance; S1-S2-switch; R1-R2-resistance; cmp_lload-light load comparator; an EA-error amplifier; pwm_cmp-PWM comparator; OR-OR gate; DRV-drive pulses; MN-MOS tube MN; MP-MOS tube MP; l-inductance; r0-resistance; c0-capacitance; INV-not gate; TON TIMER-TIMER; an i_zero_detection-ZERO current DETECTION circuit; I_ZERO >10 us-ZERO current time judging module; AND-AND gate; rf 3-resistance; rf 4-resistance; OSC-low power consumption oscillator; BANDGAP-BANDGAP reference mode; SAMPLE & HOLD-SAMPLE-and-HOLD circuit.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 2 to 5, a light load efficient voltage reduction circuit comprises a voltage reduction circuit, wherein the voltage reduction circuit is electrically connected with a light load judging circuit;
the light load judging circuit comprises a low-power-consumption voltage dividing resistor network, the voltage dividing resistor network is electrically connected with a non-inverting input end of a light load comparator CMP_LLOAD, an inverting input end of the light load comparator CMP_LLOAD is electrically connected with a voltage reducing circuit, an output end of the light load comparator CMP_LLOAD is connected with an NOT gate INV AND an AND gate AND in parallel, the NOT gate INV is electrically connected with an OR gate OR, the OR gate OR is electrically connected with the voltage reducing circuit, the AND gate AND is electrically connected with a zero current time judging module, the zero current time judging module is electrically connected with the voltage reducing circuit, the AND gate AND is electrically connected with a low-power-consumption oscillator OSC, the low-power-consumption oscillator OSC is electrically connected with a band gap reference mode BANDGAP, the band gap reference mode BANDGAP is electrically connected with a SAMPLE AND HOLD circuit SAME AND HOLD, AND the SAMPLE AND HOLD circuit SAME are electrically connected between the inverting input end of the light load comparator_LLOAD AND the voltage reducing circuit.
The step-down circuit comprises a voltage division circuit network and an SW voltage division network, wherein an error amplifier EA is electrically connected to the voltage division circuit network, a PWM comparator PWM_CMP is electrically connected to the SW voltage division network, the error amplifier EA is electrically connected to the PWM comparator PWM_CMP, the PWM comparator PWM_CMP is electrically connected to an OR gate OR, the OR gate OR is electrically connected to a processor, the processor is electrically connected to a driving pulse DRV, the driving pulse DRV is electrically connected to a MOS tube MP and a MOS tube MN respectively, a source electrode of the MOS tube MP is electrically connected to a source electrode of the MOS tube MN, an inductor L is electrically connected between the source electrode of the MOS tube MP and a source electrode of the MOS tube MN, a resistor R0 and a capacitor C0 are connected to the other end of the inductor L in parallel, and the resistor R0 and the capacitor C0 are grounded.
The voltage dividing circuit network comprises a resistor Rf1 and a resistor Rf2 which are connected in series, a switch S1 is electrically connected between the resistor Rf1 and a power input end, a switch S2 is electrically connected on the resistor Rf2, an inverting input end of the error amplifier EA is electrically connected between the resistor Rf1 and the resistor Rf2, and a non-inverting input end of the error amplifier EA is electrically connected with an inverting input end of the light load comparator CMP_LLOAD. The SW voltage dividing network comprises a resistor R1 and a resistor R2 which are connected in series, a switch S3 is electrically connected to the resistor R1, an inverting input end of the PWM comparator PWM_CMP is electrically connected between the resistor R1 and the resistor R2, the resistor R2 is grounded, a capacitor C1 is electrically connected between the resistor R2 and the resistor R1, the other end of the capacitor C1 is grounded, a non-inverting input end of the PWM comparator PWM_CMP is electrically connected with an output end of the error amplifier EA, and an output end of the PWM comparator PWM_CMP is electrically connected with an OR gate OR.
The voltage dividing resistor network comprises a voltage dividing resistor Rf3 and a voltage dividing resistor Rf4 which are connected in series, and the non-inverting input end of the light load comparator CMP_LLOAD is electrically connected between the voltage dividing resistor Rf3 and the voltage dividing resistor Rf 4. The R pin and the S pin of the processor are respectively connected with an OR gate OR a timer, and the Q pin of the processor is connected withThe pins are respectively and electrically connected with the driving pulse DRV. The driving pulse DRV is connected with the grid electrode of the MOS tube MP through an HSD_GT signal, and the driving pulse DRV is connected with the grid electrode of the MOS tube MN through an LSD_GT signal.
When the voltage dividing resistors Rf3 and Rf4 detect that the output voltage reaches 101% of the set value (i.e., the output voltage is determined by the voltage dividing network resistor Rf1 and the resistor Rf2 under medium or heavy load), the light load comparator cmp_lload output signal becomes high.
At this time, if the current of the lower MOS MN is 0 AND exceeds 10us, the ZERO current time judging module signal i_zero_10us becomes high, AND the output signal SLEEP of the AND gate AND becomes high. At this time, most circuits are turned off, such as the voltage dividing network resistor Rf1 and the resistor Rf2, the SW voltage dividing network resistor R1 and the resistor R2, the error amplifier EA, the PWM comparator pwm_cmp and the low-level MOS transistor MN ZERO current detection circuit i_zero_detection_detection, and the oscillation period of the OSC is about 16ms, wherein the time when the OSC signal is high is about 50us.
When the OSC signal is high, the BANDGAP reference mode BANDGAP circuit is turned on and the output voltage VREF of the BANDGAP reference mode BANDGAP module is sampled and held. So in SLEEP state, the BANDGAP reference mode BANDGAP is turned off for most of the time, and only 50us of the time is turned on in 16ms period, thus saving a lot of power consumption.
The switch S1 is electrically connected with the voltage dividing resistor Rf1 AND the power v0, the voltage dividing resistor Rf1 is electrically connected with the voltage dividing resistor Rf2 AND the negative input end of the error amplifier EA, the voltage dividing resistor Rf2 is electrically connected with the switch S2, the switch S2 is grounded, the output end of the difference amplifier EA is electrically connected with the positive input end of the PWM comparator PWM_CMP, the switch S3 is electrically connected with the voltage dividing network resistor R1, the voltage dividing network resistor R2, the capacitor C1 AND the negative input end of the PWM comparator PWM_CMP, the voltage dividing network resistor R2 is electrically connected with the capacitor C1 AND then grounded, the output end of the PWM comparator PWM_CMP is electrically connected with the input end of the OR gate OR is electrically connected with the interface of the processor R, the processor is electrically connected with the driving pulse DRV, the driving pulse DRV is connected with the MOS tube MP through an HSD_GT signal, the drain electrode of the MOS tube MP is connected with the voltage, the MOS tube MP is electrically connected with the inductor L AND the MOS tube MN, the inductor L is electrically connected with the capacitor C0 AND the resistor R0, the MOS tube MN is electrically connected with the lower MOS tube MN ZERO current DETECTION circuit I_ZERO_DETECTION, the capacitor C0, the resistor R0 AND the lower MOS tube MN ZERO current DETECTION circuit I_ZERO_DETECTION are simultaneously grounded, the lower MOS tube MN ZERO current DETECTION circuit I_ZERO_DETECTION is electrically connected with the ZERO current time judging module I_ZERO >10us, the ZERO current time judging module I_ZERO >10us is electrically connected with the AND gate input end, the AND gate output end is electrically connected with the low-power-consumption oscillator OSC, the low-power-consumption oscillator OSC is electrically connected with the band gap reference module AND the SAMPLE HOLD circuit SAMPLE & HOLD, the band gap reference module SAMPLE & HOLD is electrically connected with the positive input end of the error amplifier EA AND the negative input end of the light load comparator CMP_LLOAD, the positive input end of the light load comparator is electrically connected with the divider network Rf3 AND the divider network Rf4, the voltage dividing resistor network Rf3 is electrically connected with the power supply V0, the voltage dividing resistor network Rf4 is grounded, the output end of the light load comparator cmp_lload is electrically connected with the AND gate AND the inverter INV, the inverter INV is electrically connected with the input end of the OR gate OR, AND the interface of the processor S is electrically connected with the timer.
Compared with the traditional circuit which has only one group of output voltage dividing resistors Rf1 and Rf2, the invention adds one group of low-power consumption dividing resistor networks Rf3 and Rf4, a light load comparator CMP_LLOAD, a low-power consumption oscillator OSC, a sampling and holding circuit SAMPLE & HOLD of a reference circuit, a judging circuit with the current of a lower MOS tube MN of which the time is 0 and exceeds 10us, and I_ZERO >10us, etc.
The specific functions are as follows: when the voltage dividing resistor networks Rf3 and Rf4 detect that the output voltage reaches 101% of the set value (the output voltage is determined by the voltage dividing resistor network Rf1 and the resistor Rf2 under medium or heavy load), the light load comparator cmp_lload output signal becomes high. At this time, if the current of the lower MOS MN is 0 AND exceeds 10us, the ZERO current time judging module signal i_zero_10us becomes high, AND the output signal SLEEP of the AND gate AND becomes high.
At this time, most of the circuits, such as the voltage divider networks Rf1 and Rf2, the SW voltage divider networks R1 and R2, the error amplifier EAEA, the PWM comparator pwm_cmp and the low-level power transistor MN ZERO current DETECTION circuit i_zero_detection are turned off.
Wherein the quiescent current of the comparator is only 100nA, the average power consumption of the OSC is also about 80nA, and the average current of the BANDGAP reference BANDGAP and SAMPLE and HOLD circuit is also only 100nA. The oscillation period of OSC is about 16ms, as shown in fig. 3.
The time in which the OSC signal is high is about 50us, as shown in fig. 4.
When the OSC signal is high, the BANDGAP circuit is turned on and the output voltage VERF of the BANDGAP module is sampled and held. So in SLEEP state, the BANDGAP is turned off for most of the time, and only 50us of time is turned on in 16ms period, thus saving a lot of power consumption.
When the output voltage is lower than 101% of the set value, the light load comparator CMP_LLOAD output signal LLOAD becomes low, meanwhile the SLEEP signal becomes low, most circuits of the system start to work immediately, and meanwhile the upper power pipeline is connected to supply energy for output.
The waveform of the output 1.8V, 10uA on load is as follows, with a ripple of about 20mV. The input current is about 260nA in SLEEP state (if the average current of OSC is calculated, the average current of SLEEP will be slightly greater than 260nA, about 300 nA).
Under the conditions of 3.6V input, 1.8V output and 10uA load, the efficiency reaches 81 percent, and the original product exceeds the similar product.
Compared with the traditional circuit, the invention adds the light load judging circuit. And when the circuit is found to be in a light load state, entering a SLEEP mode. In SLEEP mode, most of the blocks of the circuit are in an off state. The band gap block band gap starts intermittently along with the band gap reference mode band gap block and has a much longer off time than it has on time. While the output of the band gap is SAMPLE-and-HOLD using the SAMPLE & HOLD circuit. The quiescent current of the circuit is thus about 300nA.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.
Claims (1)
1. A light-load efficient buck circuit comprising: the device comprises a voltage dividing circuit network, an SW voltage dividing network, an error amplifier, a PWM comparator, an NOT gate, an OR gate, a timer, a processor, a pulse driver, an MOS tube MP, an MOS tube MN, an inductor L, a resistor Ro, a capacitor Co, a zero current detection circuit, a zero current time judging module, an AND gate, a light load comparator, a low-power-consumption voltage dividing resistor network, a low-power-consumption oscillator OSC, a band gap reference module and a sampling and holding circuit;
the drain electrode of the MOS tube MP is connected with a power supply voltage VDD, the source electrode of the MOS tube MP and the source electrode of the MOS tube MN are connected to a node SW, the node SW is connected with one end of an inductor L, the other end of the inductor L is connected with one end of a resistor Ro and one end of a capacitor Co, the other end of the resistor Ro and the other end of the capacitor Co are grounded, and the drain electrode of the MOS tube MN is grounded through a zero current detection circuit;
the SW voltage division network comprises a resistor R1 and a resistor R2 which are connected in series, one end of a node SW is connected with one end of a switch S3, the other end of the switch S3 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with one end of a resistor R2 and one end of a capacitor C1, the other end of the resistor R2 and the other end of the capacitor C1 are grounded, and the other end of the resistor R1, one end of the resistor R2 and one end of the capacitor C1 are also connected to an inverting input end of the PWM comparator;
the voltage dividing circuit network comprises a resistor Rf1 and a resistor Rf2 which are connected in series, one end of a switch S1 is connected with one end of a resistor Ro and one end of a capacitor Co, the other end of the switch S1 is connected with one end of a resistor Rf1, the other end of the resistor Rf1 is connected with one end of a resistor Rf2, the other end of the resistor Rf2 is connected with one end of the switch S2, the other end of the switch S2 is grounded, and the other end of the resistor Rf1 and one end of the resistor Rf2 are also connected to an inverting input end of the error amplifier;
the output end of the error amplifier is connected to the normal phase input end of the PWM comparator, the output end of the PWM comparator is connected to one input end of the OR gate, the other input end of the OR gate is connected to the output end of the NOT gate, the output end of the OR gate is connected to the R end of the processor, the S end of the processor is connected to the output end of the timer, the Q end and the' Q end of the processor are connected to the input end of the pulse driver, the signal HSD_GT output by the pulse driver is connected with the grid electrode of the MOS tube MP, and the signal LSD_GT output by the pulse driver is connected with the grid electrode of the MOS tube MN;
the output end of the zero current detection circuit is connected to the input end of the zero current time judging module, and the output end of the zero current time judging module is connected to one input end of the AND gate;
the divider resistor network comprises a resistor Rf3 and a resistor Rf4 which are connected in series, one end of the resistor Rf3 is connected with one end of a resistor Ro and one end of a capacitor Co, the other end of the resistor Rf3 is connected with one end of the resistor Rf4, the other end of the resistor Rf4 is grounded, the other end of the resistor Rf3 and one end of the resistor Rf4 are also connected to a non-inverting input end of a light load comparator, and an output end of the light load comparator is connected to the other input end of an AND gate and an input end of an NOT gate;
the output end of the AND gate is connected to the input end of the low-power consumption oscillator OSC, the output end of the low-power consumption oscillator OSC is connected to the input end of the band-gap reference module and one input end of the sample-hold circuit, the output end of the band-gap reference module is connected to the other input end of the sample-hold circuit, and the output end of the sample-hold circuit is connected to the inverting input end of the light load comparator and the non-inverting input end of the error amplifier;
when the resistance Rf3 and the resistance Rf4 detect that the output voltage reaches 101% of the set value, the output signal of the light load comparator becomes high, at this time, if the current flowing through the MOS tube MN is 0 and the time exceeds 10us, the output signal of the zero current time judging module becomes high, the output signal SLEEP of the AND gate becomes high, at this time, most circuits comprising a voltage dividing circuit network, an SW voltage dividing network, an error amplifier, a PWM comparator and a zero current detecting circuit are turned off, the oscillation period of the OSC signal output by the low power consumption oscillator OSC is 16ms, the time when the OSC signal is high is 50us, the band gap reference module is turned on only when the OSC signal is high, and the output voltage VREF of the band gap reference module is sampled and maintained; when the output voltage is lower than 101% of the set value, the output signal of the light-load comparator becomes low, meanwhile, the signal SLEEP becomes low, most circuits of the system immediately start to work, and meanwhile, the MOS tube MP is conducted to provide energy for output.
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| CN202210336601.4A CN114665709B (en) | 2022-04-01 | 2022-04-01 | Light-load efficient step-down circuit |
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| CN202210336601.4A CN114665709B (en) | 2022-04-01 | 2022-04-01 | Light-load efficient step-down circuit |
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| CN114665709B true CN114665709B (en) | 2023-11-03 |
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| JP2003338552A (en) * | 2002-05-22 | 2003-11-28 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| US7304464B2 (en) * | 2006-03-15 | 2007-12-04 | Micrel, Inc. | Switching voltage regulator with low current trickle mode |
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| CN114665709A (en) | 2022-06-24 |
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