CN114664875A - 背照式图像传感器 - Google Patents
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Abstract
本公开涉及一种背照式图像传感器，包括形成于半导体晶圆中的存储器区域，每个存储器区域位于两个不透明壁之间，这两个不透明壁延伸到该晶圆中并与安排在该存储器区域的后表面处的不透明屏幕接触。
Description
本申请是申请日为2017年04月25日、申请号为2017102776947、发明名称为“背照式图像传感器”的申请的分案申请。
技术领域
本公开涉及半导体器件，并且更具体地涉及背照式图像传感器。
背景技术
图像传感器包括由半导体晶圆形成的像素阵列。根据在获取期间接收的光而在每个像素中生成电荷，并且在读取期间读取所生成电荷的数量。在某些图像传感器中，像素与存储器区域相关联，其中，所生成的电荷被周期性地转移以便稍后进行读取。
问题在于，光可能在转移时间与读取时间之间到达存储器区域，并在其中生成电子/空穴对。这修改了所存储电荷的数量，这降低了图像质量。具体的，针对背照式图像传感器提出了这一问题。已经提供了存储器区域的光隔离的结构(比如，在美国专利申请2016/0118438中所描述的结构)，该专利申请关于其图2提供了使用不透明钨壁来包围每个存储器区域以及在背面提供钨屏蔽层。然而，不透明壁和屏蔽层是不连续的并且光可以穿过其之间并到达存储器区域。因此，这种结构允许部分光通过。这些结构进一步具有各种制造和实施问题。
因此，期望一种具有包括被有效地防止受光影响的存储器区域的背照式图像传感器、以及一种制造这种传感器的方法。
发明内容
因此，实施例提供了一种背照式图像传感器，该背照式图像传感器包括形成于半导体晶圆中的存储器区域，每个存储器区域位于两个不透明壁之间，这两个不透明壁延伸到该晶圆中并与安排在该存储器区域的后表面上的不透明屏幕接触。
根据实施例，对于每个存储器区域，这些不透明壁以及该不透明屏幕是导电的并且连接至偏置电位的施加节点。
根据实施例，这些不透明壁和这些不透明屏幕由钨制成并且这些不透明壁具有在从50nm到200nm范围内的厚度。
根据实施例，这些不透明壁通过氧化铪层与这些存储器区域分-离。
根据实施例，每个不透明壁通过多晶硅层与相关联存储器区域分-离，该多晶硅层通过氧化硅层与该相关联存储器区域分离。
根据实施例，这些不透明壁通过氧化铪层与这些多晶硅层分离。
实施例提供了一种制造背照式图像传感器的方法，该方法包括以下连续步骤：a)形成沟槽，这些沟槽被安排在半导体晶圆的前表面中的存储器区域的任一侧上；b)使用氮化硅来填充这些沟槽；c)在该前表面的内部和顶部上形成晶体管；d)通过化学机械抛光来对所述后表面进行蚀刻直至该氮化硅；e)通过选择性蚀刻来从该后表面中去除该氮化硅；f)通过使用不透明材料来填充这些沟槽从而形成不透明壁；以及g)在每个存储器区域的后表面上形成与这些不透明壁接触的不透明屏幕。
根据实施例，这些不透明壁和这些不透明屏幕由钨制成，这些不透明壁具有在从50nm到200nm的范围内的厚度。
根据实施例，该方法包括，在步骤e)与步骤f)之间：使用氧化铪层来覆盖该结构。
根据实施例，该方法包括，在步骤d)与步骤e)之间：使用氧化铪层来覆盖该结构；以及蚀刻出从该后表面延伸至该氮化硅的开口。
根据实施例，该方法包括，在步骤a)与步骤b)之间，在这些沟槽的侧壁以及底部上形成电绝缘层以及然后多晶硅层；在步骤b)，不完全地填充这些氮化硅沟槽；以及在步骤b)与步骤c)之间，使用多晶硅来完成沟槽填充。
根据实施例，在步骤b)，该氮化硅从该晶圆的该前表面开始被凹陷从50nm到150nm，这些沟槽具有在从3μm至12μm范围内的深度。
根据实施例，该方法还包括，在步骤b)：使用填充这些沟槽的氮化硅层来覆盖该前表面；以及通过选择性湿法蚀刻来去除该氮化硅层的覆盖该前表面的部分。
前述和其他特征及优点将在以下特定实施例的非限制性描述中结合所附附图进行详细讨论。
附图说明
图1至图9是部分简化的横截面视图，展示了制造背照式图像传感器的方法的实施例的步骤，图9展示了所获得的传感器；以及
图10至图13是部分简化的横截面视图，展示了制造背照式图像传感器的方法的另一个实施例的步骤，图13展示了所获得的传感器。
具体实施方式
在各种附图中，相同的元件已被指定有相同的参考号，进而，各种附图并不按比例绘制。为清楚起见，仅仅示出了并详细描述了对理解所描述的实施例有用的那些步骤和元件。具体地，未示出导电互连线路和如晶体管和光电二极管等元件。
在以下描述中，在参照限制绝对位置(比如，术语“左”、“右”等)或者相对位置(比如，术语“上”、“下”等)的术语时，参照相应的附图中有关的元件的取向。除非另外指定，表述“大约”意指在10％以内，优选地，在5％以内。
图1至图9是简化的横截面视图，以制造背照式图像传感器的连续步骤来展示了背照式图像传感器的实施例。传感器包括像素阵列，并且已经示出了对这些像素中的单个像素的以及对相邻像素的制造。
在图1的步骤处，前表面已经覆盖以半导体晶圆1(例如，由硅制成)，覆盖以蚀刻停止层3(例如，由氧化硅制成)，并且然后覆盖以氮化硅掩模层5。已经在半导体晶圆1中蚀刻了沟槽7。沟槽7被成对地安排在晶圆1的区域9的任一侧上，这些区域对应于未来的存储器区域。在图1的左边部分可以看到沟槽7对和相关联的区域9。优选地，存储器区域9具有在正交于附图的平面的方向上的细长形状。每个像素均包括光电二极管，将在位于成对的沟槽7对之外的区域11中形成该光电二极管。
然后，已经共形沉积了厚度较小的例如由氧化硅制成的电绝缘层13。层13覆盖沟槽7的侧壁和底部。
然后，多晶硅层15共形沉积在前表面上。具体地，层15覆盖层13的位于沟槽中的部分。层13和15具有小于沟槽7的一半厚度的总厚度，从而使得在沟槽7的中心处仍然存在凹陷17。作为变体，可以省略层15。
作为示例，沟槽7具有大约200nm的宽度。沟槽7可以延伸到晶圆中向下到在从3到10μm(例如，6μm)的范围内的深度。绝缘层13可以具有在从5nm到20nm(例如，12nm)的范围内的厚度。绝缘层17可以具有在从50nm到200nm(例如，70nm)范围内的宽度。
在图2的步骤处，氮化硅层20沉积在前表面上以便填充凹陷17。
在图3的步骤处，按照提供的蚀刻时间例如通过湿法蚀刻来去除氮化硅层20，从而使得在凹陷17中仍然存在氮化硅牺牲壁30。作为示例，牺牲壁30填充凹陷17一直到位于晶圆1的前表面下在从50nm到150nm的范围内的深度处的层面。
在图4的步骤处，已经使用多晶硅来对已保持为空的凹陷17的部分40进行了填充。已经通过化学机械抛光去除了位于蚀刻停止层3的层面上方的前表面上的所有元件。
然后，执行掺杂步骤，具体地，以便形成存储器区域9和光电二极管区域11以及以便形成各种晶体管(比如，转移晶体管、读取晶体管或者复位晶体管)。由于已经形成并填充了暗示针对其制造的高热预算的深沟槽的事实而可以实施这些步骤。在这些步骤期间，在退火步骤期间，牺牲壁30可以经受高温。有利的是，牺牲壁30由于是由氮化硅制成的而承受了这些步骤。进一步地，覆盖牺牲壁30的两侧的层13和15使得能够避免源自牺牲壁的氮原子到达存储器区域9或者光电二极管区域11的任何风险。
然后，沉积例如由氮化硅制成的保护层42以及例如由氧化硅制成的绝缘层44。在层44上形成包括互连线路的层46。
在图5的步骤处，已经翻转了晶圆。现在，后表面或者背面位于图5至图9的上部部分中。存储器区域9及相关联沟槽7位于右边部分中。然后，例如通过对后表面进行化学机械抛光来去除位于牺牲壁30的层面上方的元件，从而使得牺牲壁与经抛光的后表面持平。
在图6的步骤处，去除牺牲壁30。在示例中，由于牺牲壁30由氮化硅制成的事实，所以有利的是，在背面上的其他材料只是硅和氧化硅的示例中，通过选择性湿法蚀刻可以很容易地去除牺牲壁30。可以通过磷酸溶液H3PO4来执行这种选择性湿法蚀刻。在牺牲壁30的位置处得到凹陷60。
在图7的步骤处，沉积由带正电荷的钝化材料(比如，氧化铪HfO2)制成的层70。层70覆盖存储器区域9的以及光电二极管11的后表面并覆盖凹陷60的壁和底部。然后，在层70上沉积氧化硅。该沉积是非共形的，即，其主要覆盖被定向为朝向背面的表面。因此，除了在凹陷60底部上形成部分72之外，还形成了在每个凹陷的层面处展现开口76的氧化硅层74。
作为示例，层70具有在从4nm到10nm的范围内的厚度。层74可以具有在从30nm到40nm的范围内的厚度。作为变体，可以省略层70。
在图8的步骤处，凹陷60填充有不透明材料，即，具有大于1的消光系数的材料(例如，钨)。经由开口76例如通过在后表面上的钨沉积(随后是向下直至层74的化学机械抛光)来执行填充。然后，层74被用作抛光停止层。得到与层74的表面持平的不透明壁80。不透明壁80使其两侧覆盖有层70。
根据在此所描述的方法的优点，由于在关于图4所讨论的形成晶体管的步骤之后(并且具体地，在退火步骤之后)执行了钨沉积的事实而避免了各种问题，比如，钨扩散到存储器区域和光电二极管区域9和11中的问题。
在图9的步骤处，在层74上沉积防反射层90和92。作为示例，层90由氧化钽制成并且层92由氧化硅制成。选择层90的厚度，从而使得夹在层74与92之间的这一层形成防反射涂层。从背面开始对被定位成与存储器区域9和不透明壁80相反的层92和90的部分进行蚀刻，并且蚀刻继续向下到层74的层面。不透明壁的部分由于提供了层74而暴露在蚀刻部分的底部。蚀刻部分(例如，钨)填充有不透明材料。由于部分不透明壁被暴露的事实，钨与不透明壁80相接触。因此，在存储器区域9的背面上已获得了与不透明壁80接触的不透明屏幕96。
因此，每个存储器区域9位于与不透明屏幕96接触的两个不透明壁80之间。在操作中，当图像传感器的背面被光辐射照亮时，存储器区域9由于不透明屏幕96与不透明壁80之间的接触而特别有效地被保护免受辐射的影响。因此，所得到的图像传感器具有特别高的图像质量。
作为示例，每个不透明屏幕96连接至偏置电位的施加节点(未示出)。然后，由于要使用层70、74、90和92的绝缘材料来包围不透明壁80及相关联不透明屏幕96的事实，可以偏置不透明壁和屏幕的组件，这使得能够控制存储器单元的操作。
图10至图13是简化的横截面视图，以制造背照式图像传感器的连续步骤来展示了背照式图像传感器的另一个实施例。已经以与图1至图9相同的方式示出了对单个像素和相邻像素的一部分的制造。
在图10的步骤处，已经从半导体晶圆1开始连续实施了与图1至图5的步骤类似的步骤。因此，背面位于图10至图13的上部部分中。
后表面或者背面覆盖以例如由氧化铪HfO2制成的钝化层70，并且然后覆盖以氧化硅层74。然后，从牺牲壁30中的每个牺牲层上方的背面开始蚀刻开口100，开口100延伸穿过层70和74直至牺牲壁30。
在图11的步骤处，以与先前关于图6所描述的方式类似的方式(即，通过选择性湿法蚀刻)来去除牺牲壁30。在每个牺牲壁30的位置处得到凹陷60，每个凹陷60通过相关联的开口100朝向背面。
以与先前关于图8所描述的方式类似的方式(即，通过使用不透明材料来填充凹陷60和开口100，并且然后通过抛光后表面直至抛光停止层74)来执行图12的步骤。
类似于关于图9所描述的步骤来执行图13的步骤。一方面，获得了覆盖光电二极管11中的每个光电二极管的后表面上的钝化层70的防反射涂层74、90和92，并且另一方面，获得了位于每个存储器区域9的后表面上的不透明屏幕96。每个不透明屏幕96与界定每个存储器区域9的不透明壁80相接触。
已经描述了具体实施例。本领域技术人员将容易想到各种变更、修改和改进。具体地，在图4的步骤处，可以针对每个沟槽一方面在部分40和多晶硅层15之间并且另一方面在部分40与偏置电位的施加节点之间形成一个通孔。因此，可以控制存储器单元操作。
这种变更、修改和改进旨在作为本公开的一部分，并且旨在在本发明的精神和范围内。因此，前面的描述仅是示例性的并不旨在为限制性的。本发明仅根据下面的权利要求书及其等效物中所限定的那样进行限制。
Claims (6)
1.一种背照式图像传感器，包括存储器区域，所述存储器区域形成于半导体晶圆中，每个存储器区域位于两个不透明壁之间，所述两个不透明壁从所述半导体晶圆的背表面延伸到所述半导体晶圆中，并且与布置在所述半导体晶圆的后表面处的不透明屏幕接触以覆盖所述存储器区域，其中每个不透明壁通过多晶硅层与所述存储器区域分离。
2.根据权利要求1所述的传感器，其中，对于每个存储器区域，所述不透明壁和所述不透明屏幕是导电的并且连接至偏置电位的施加节点。
3.根据权利要求1所述的传感器，其中，所述不透明壁和所述不透明屏幕由钨制成，并且所述不透明壁具有在从50nm到200nm范围内的厚度。
4.根据权利要求1所述的传感器，其中，所述不透明壁通过氧化铪层与所述存储器区域分离。
5.根据权利要求1所述的传感器，其中，所述多晶硅层通过氧化硅层与相关联的所述存储器区域分离。
6.根据权利要求5所述的传感器，其中，所述不透明壁通过氧化铪层与所述多晶硅层分离。
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