CN114650025A - Negative slope equalizer with high equalization volume, high linearity and high return loss - Google Patents
Negative slope equalizer with high equalization volume, high linearity and high return loss Download PDFInfo
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- CN114650025A CN114650025A CN202210565812.5A CN202210565812A CN114650025A CN 114650025 A CN114650025 A CN 114650025A CN 202210565812 A CN202210565812 A CN 202210565812A CN 114650025 A CN114650025 A CN 114650025A
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- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/0115—Frequency selective two-port networks comprising only inductors and capacitors
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Abstract
The invention discloses a negative slope equalizer with high equalization volume, high linearity and high return loss. The equalization circuit includes: the system comprises an unbalanced bridging T-shaped network, a parallel resonance unit, two symmetrical linear equalization units, a series resonance unit, an input port and an output port; the unbalanced bridged T-network comprises a first impedance module and a second impedance module, a shunt impedance module coupled at the junction of the first impedance module and the second impedance module, and a bridge impedance module in parallel with the first impedance module and the second impedance module in series; the product of the impedances of the first impedance module and the second impedance module is smaller than the product of the impedances of the shunt impedance module and the bridge impedance module; the parallel resonance unit is connected with the bridge impedance module in parallel; the series resonance unit is connected with the shunt impedance module in series; the two symmetrical linear equalizing units are respectively connected between the input port and the first impedance module and between the output port and the second impedance module. The scheme improves the signal equalization amount in the limited circuit area and optimizes the linear trend.
Description
Technical Field
The embodiment of the invention relates to a microwave transmitting technology, in particular to a negative slope equalizer with high equalization volume, high linearity and high return loss.
Background
With the wide use of microwave devices in military and civil fields, the demand for microwave devices is manifested as integration of wider frequency bands. The frequency band that the amplifier can integrate as the resident device of the radio frequency front end module is also getting wider and wider. In the design of a broadband amplifier, an amplified signal often varies unidirectionally with frequency, so that the gain is not consistent in a certain frequency band. The equalizer can keep the gain of the amplifier consistent in the whole frequency band and can prevent the amplifier from being operated in saturation.
The current equalizer has a small equalization amount, and a plurality of equalization circuits are often connected in a cascade mode in order to improve the overall equalization amount, so that the circuit area is large.
Disclosure of Invention
The invention provides a negative slope equalizer with high equalization amount, high linearity and high return loss, which is used for improving the signal equalization amount in a limited circuit area and optimizing the linear trend of signals.
In a first aspect, an embodiment of the present invention provides an equalization circuit, where the equalization circuit includes: the system comprises an unbalanced bridging T-shaped network, a parallel resonance unit, a series resonance unit, two symmetrical linear equalization units, an input port and an output port;
the unbalanced bridged T-network comprises a first impedance module and a second impedance module connected in series between the input port and the output port, a shunt impedance module coupled at the connection of the first impedance module and the second impedance module, and a bridge impedance module in parallel with the first impedance module and the second impedance module in series; the product of the impedance of the first impedance module and the impedance of the second impedance module is smaller than the product of the impedance of the shunt impedance module and the impedance of the bridge impedance module, the impedance of the first impedance module is equal to the impedance of the second impedance module, and the impedance of the first impedance module and the impedance of the second impedance module are both smaller than 50 Ω;
the parallel resonance unit is connected in parallel with the bridge impedance module; the series resonance unit is connected in series with the shunt impedance module;
one of the symmetrical linear equalizing units is connected between the input port and the first impedance block, and the other of the symmetrical linear equalizing units is connected between the output port and the second impedance block.
Optionally, the bridge impedance module comprises a first resistor.
Optionally, the shunt impedance module includes a second resistor, one end of the second resistor is connected to a connection between the first impedance module and the second impedance module, and the other end of the second resistor is connected to the series resonant unit.
Optionally, the parallel resonant unit includes a first capacitor and a first inductor, and both the first capacitor and the first inductor are connected in parallel with the bridge impedance module.
Optionally, the series resonant unit includes a second capacitor and a second inductor, and the second capacitor and the second inductor are connected in series between the shunt impedance module and the reference terminal.
Optionally, the symmetrical linear equalization unit comprises a third inductor and a third resistor connected in parallel.
Optionally, the first inductor, the second inductor and the third inductor each comprise a microstrip line.
In a second aspect, an embodiment of the present invention further provides an equalizer, where the equalizer includes the equalizing circuit described in any one of the first aspects.
The equalizing circuit and the equalizer provided by the embodiment of the invention adopt an unbalanced bridge T-shaped network, the product of the impedances of a bridge impedance module and a shunt impedance module in the unbalanced bridge T-shaped network is larger than the product of the impedances of a first impedance module and a second impedance module, and the resonance points of a series resonance unit and a parallel resonance unit are controlled outside an equalizing frequency band, so that the echo performance is conveniently improved, the optimization of the linear trend and the resonance impedance is realized, the equalization amount is improved in a limited circuit area, the circuit area is reduced, the linear trend of signals is optimized, and the linear trend of the equalized signals is more ideal.
Drawings
Fig. 1 is a schematic structural diagram of an equalizing circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another equalizing circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another equalizing circuit according to an embodiment of the present invention;
fig. 4 is a comparison graph of the gain of the signal to be equalized, the equalization amount, and the gain of the equalized amplified signal according to the embodiment of the present invention;
fig. 5 is a schematic diagram showing the distribution of insertion loss and return loss of a conventional equalizing circuit;
FIG. 6 is a diagram illustrating a distribution of linearity of a conventional equalizer circuit;
fig. 7 is a schematic diagram illustrating distribution of insertion loss and return loss of an equalizing circuit according to an embodiment of the present invention;
fig. 8 is a distribution diagram of the linearity of the equalizing circuit according to the embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
In order to solve the problems in the background art, an embodiment of the present invention provides an equalization circuit, where the equalization circuit may be disposed at an output interface of a radio frequency amplifier, and provides equalization amounts with different slopes according to a slope of an output signal of the amplifier, and the equalization circuit may be further connected to a detector, so as to equalize the slope of the detector. Fig. 1 is a schematic structural diagram of an equalizing circuit according to an embodiment of the present invention, and referring to fig. 1, the equalizing circuit 100 includes: the system comprises an unbalanced bridge T-shaped network 101, a parallel resonance unit 102, a series resonance unit 103, a symmetrical linear equalization unit 201, an input port a and an output port b; the unbalanced bridged T-network 101 comprises a first impedance module 104 and a second impedance module 105 connected in series between the input port a and the output port b, a shunt impedance module 107 coupled at the connection of the first impedance module 104 and the second impedance module 105, and a bridge impedance module 106 connected in parallel with the first impedance module 104 and the second impedance module 105 in series; the product of the impedance of the first impedance module 104 and the impedance of the second impedance module 105 is smaller than the product of the impedance of the shunt impedance module 107 and the impedance of the bridge impedance module 106; the parallel resonance unit 102 is connected in parallel with the bridge impedance block 106; the series resonance unit 103 is connected in series with the shunt impedance module 107. One symmetrical equalizing unit 201 is connected between the input interface a and the first impedance block 104, and the other symmetrical equalizing unit 201 is connected between the output interface b and the second impedance block 105.
Specifically, the unbalanced bridged T-network 101 may be a resistive network, and may include a plurality of impedance modules, the first impedance module 104 and the second impedance module 105 are characteristic impedances of the unbalanced bridged T-network 101, the impedances of the first impedance module 104 and the second impedance module 105 are equal, and the impedances of the first impedance module 104 and the second impedance module 105 are both less than 50 Ω. The connection and impedance setting of the unbalanced bridge T-network 101 and other modules can make the real impedance between the input port a and the output port b infinitely close to 50 Ω, and the return loss is good. The shunt impedance module 107 is coupled between a connection point of the first impedance module 104 and the second impedance module 105 and a reference terminal D, which may be a ground terminal. The product of the impedances of the bridge impedance block 106 and the shunt impedance block 107 is larger than the product of the impedances of the first impedance block 104 and the second impedance block 105, so that the unbalanced bridged T-network 101 is unbalanced. On the basis of setting the unbalanced bridging T-shaped network 101, the resistance value of the series resonance unit 103 is increased, the internal resistance of the series resonance branch can be increased, the resonance Q value can be reduced, the balanced frequency band is widened, and the linear trend of the sideband is optimized. The parallel resonant unit 102 may include an inductive element and a capacitive element in parallel, in parallel with the bridge impedance module 106. The series resonance unit 103 may include an inductive element and a capacitive element, which are connected in series between the reference terminal D and the shunt impedance module 107. The combination of the inductance element and the capacitance element in the series resonance unit 103 and the parallel resonance unit 102 controls the resonance point of the unit to be outside the balanced frequency band, for example, the balanced frequency band is 2GHz-18GHz, and then the resonance point of the series resonance unit 103 and the parallel unit 102 can be set at 20GHz, which facilitates the adjustment of echo performance while sacrificing the balanced amount by a small margin, and optimizes the linearity trend.
The equalization circuit provided by the embodiment of the invention adopts an unbalanced bridging T-shaped network, the product of the impedances of a bridge impedance module and a shunt impedance module in the unbalanced bridging T-shaped network is larger than the product of the impedances of a first impedance module and a second impedance module, and the resonance points of a series resonance unit and a parallel resonance unit are controlled outside an equalization frequency band, so that the echo performance is conveniently improved, the optimization of the linear trend and the resonance impedance is realized, the equalization amount is improved in a limited circuit area, the circuit area is reduced, the equalization frequency band is widened, the linear trend of a sideband is optimized, and the linear trend of the equalized signal is more ideal.
Optionally, fig. 2 is a schematic structural diagram of another equalizing circuit according to an embodiment of the present invention, and based on the foregoing embodiment, the equalizing circuit 100 further includes: and two symmetrical linear equalization units 201, wherein one symmetrical linear equalization unit 201 is connected between the input port a and the first impedance module 104, the other symmetrical linear equalization unit 201 is connected between the output port b and the second impedance module 105, and the symmetrical linear equalization unit 201 is used for adjusting the real impedance of the input port a and the output port b, and further optimizing the return loss and the linear trend of the middle and high frequency band.
Specifically, the first impedance module 104 and the second impedance module 105 may be resistors having the same resistance, and the resistance of the resistors is less than 50 ohms. The symmetrical linear equalizing unit 201 includes a third inductor L3 and a third resistor R3 connected in parallel. The third resistor R3 is set to make the real impedance between the input port a and the output port b close to 50 ohms, so that the function of adjusting the real impedance can be realized. The third inductor L3 is connected in parallel with the third resistor R3, which can optimize the return loss at high frequencies and optimize linearity.
Further, the third inductor L3 may be configured to include an inductor or a microstrip line. The inductor is in the form of a finger-loop coil. Considering that the inductor is a winding coil in actual process manufacturing, such an inductor is not ideal in inductance. On the one hand, parasitic capacitance exists between the coils, on the other hand, charge flows around the inner side in the inductor coil, which causes charge maldistribution, and the inductor coil also has a skin effect that causes charge to be concentrated on the surface but not in the inner side, which also causes charge maldistribution. This also creates parasitic capacitance in the inductor, which resonates with the inductance. As the inductance of the inductor increases, the number of windings of the coil increases, and the parasitic capacitance increases, the self-resonance point decreases. Similarly, in consideration of the nature of the microstrip line, the inductive reactance of the microstrip line increases with increasing frequency, and gradually decreases as the self-resonant frequency of the microstrip line approaches, until the frequency rises beyond the self-resonant frequency, and the microstrip line is capacitive. Compared with an ideal inductor, the third inductor L3 is set as a microstrip line, so that the virtual impedance variation trend of a parallel branch consisting of the third inductor L3 and the third resistor R3 is modified, and the low-frequency loss can be reduced. In the equalizing frequency band of 2GHz-18GHz, the virtual impedance of the parallel combination of the third resistor R3 and the third inductor L3 is increased and then decreased by utilizing the self-resonance of the inductor or the self-properties of the microstrip line. With this correction, the equalization circuit 100 greatly increases the attenuation in the middle band, and relatively slightly increases the attenuation in the low band and the high band, thereby optimizing the linearity.
Optionally, fig. 3 is a schematic structural diagram of another equalizing circuit according to an embodiment of the present invention, and with reference to fig. 3, on the basis of the foregoing embodiment, the parallel resonant unit 102 includes a first capacitor C1 and a first inductor L1, and both the first capacitor C1 and the first inductor L1 are connected in parallel to the bridge impedance module 106. The series resonant unit 103 includes a second capacitor C2 and a second inductor L2, and the second capacitor C2 and the second inductor L2 are connected in series between the shunt impedance module 107 and the reference terminal D.
Specifically, the capacitance value of the first capacitor C1 is smaller than that of the second capacitor C2. The inductance of the first inductor L1 is greater than the inductance of the second inductor L2. The first capacitor C1 and the first inductor L1 connected in parallel to the two ends of the bridge impedance module 106 in the parallel resonant unit 102 adopt a large inductance value and a small capacitance value to increase the peak value at the resonant point, which can further increase the balance but worsen the return loss. Furthermore, the second capacitor C2 and the second inductor L2 connected in series between the shunt impedance module 107 and the reference terminal in the series resonance unit 103 adopt a small inductance value and a large capacitance value, which can increase the real impedance of the equalizing circuit 100, reduce the virtual impedance, improve the equalization amount and the linearity, and optimize the return loss of the intermediate frequency band. The arrangement of the parallel resonance unit 102 and the series resonance unit 103 can obtain a larger amount of equalization and a better return loss. The first inductance L1 and the second inductance L2 may also comprise inductors or microstrip lines. The microstrip line is adopted as the first inductor L1, the virtual impedance change function during parallel resonance is modified, the impedance of the microstrip line is equivalent to a sine function form, the first inductor L1 is connected with the first capacitor C1 in parallel, the trend of the virtual impedance during resonance is changed, the linear trend change is more average, and the signal linearity can be further optimized.
Optionally, with continued reference to fig. 3, on the basis of the foregoing embodiment, the shunt impedance module 107 includes a second resistor R2, a first end of the second resistor R2 is connected to a connection of the first impedance module 104 and the second impedance module 105, and another end of the second resistor R2 is connected to the series resonant unit 103. The bridge impedance module 106 includes a first resistor R1.
Specifically, the impedance of the first impedance module 104 and the impedance of the second impedance module 105 in the equalization circuit are both equal to R0, the resistance value of the first resistor R1 is equal to k × R0, and the resistance value of the second resistor R2 is equal to R0/k, where k is a constant coefficient, and R0 is less than 50 Ω. The third resistor R3 has a value equal to 50- [ (k-R0)/(k + 2) ] -T, where T ∈ (0, 1). k is larger than 1, and the effect of widening the balanced frequency band and optimizing sideband linearity can be achieved by increasing the impedance value of the first resistor R1.
Fig. 4 is a comparison diagram of gain and equalization amount of an amplified signal to be equalized and gain of an amplified signal after equalization according to an embodiment of the present invention, and referring to fig. 4, a curve X may be represented by a relationship between gain and frequency of an amplified signal to be equalized within a 2-18GHz equalization frequency band before equalization. As shown in FIG. 4, in the 2-18GHz equalization frequency band, the gain of the signal to be equalized and amplified is monotonically increased from 12dB to 32 dB. The curve Y is the equalization amount that can be provided by the equalization circuit provided in the embodiment of the present invention, and it can be seen that the variation trend of the equalization amount in the 2-18GHz equalization frequency band is opposite to the variation trend of the signal to be equalized and amplified, so that the gain of the signal to be equalized and amplified can be equalized to a more stable level. As shown in curve Z of fig. 4, the maximum gain fluctuation amount of the amplified signal after equalization in the 2-18GHz equalization frequency band is between-1 dB and 1dB, and effective equalization of the gain of the amplified signal to be equalized is realized.
Fig. 5 is a diagram showing distribution of insertion loss and return loss of a conventional equalizer circuit, and fig. 6 is a diagram showing distribution of linearity of a conventional equalizer circuit. Through the research of the inventor, the bridge connection T-shaped network in the traditional equalizing circuit in the prior art is a balanced structure, that is, the resistance values of the first impedance module and the second impedance module are both equal to 50 Ω, the product of the impedance of the first impedance module and the impedance of the second impedance module in the bridge connection T-shaped network is equal to the product of the impedance of the shunt impedance module and the impedance of the bridge impedance module, and the resonance point is set at 20 GHz. Referring to fig. 5 and 6, in the case where the equalization amount is small (exemplarily, constant coefficient k = 2), the insertion loss, the return loss, and the linearity are all excellent. However, as the equalization amount increases (k value increases), the insertion loss changes less, but the linearity and the return loss deteriorate sharply, so that the equalization amount which can be introduced by the conventional equalization circuit is smaller.
In order to solve the problems of the conventional equalizing circuit, the present application proposes the equalizing circuit in the foregoing embodiments, which are exemplified herein on the basis of the foregoing embodiments. With reference to fig. 3, the impedance of the first impedance module 104 and the impedance of the second impedance module 105 in the equalization circuit are both equal to R0, where R0=5 Ω, for example. The resistance of the first resistor R1 is equal to k × R0, and the resistance of the second resistor R2 is equal to R0/k, where k is a constant coefficient and k = 3. The third resistor R3 has a value equal to 50- [ (k-R0)/(k + 2) ] -T, where T = 0.3. The capacitance of the first capacitor C1 is equal to 95fF, and the capacitance of the second capacitor C2 is equal to 499.5 fF. The first inductor L1 is a microstrip line, which has a width-to-length ratio equal to 10 × 1510um, is inductive around 2GHz, and is capacitive around 18 GHz. The second inductor L2 is a microstrip line, and the width-to-length ratio of the microstrip line is equal to 10 × 125 um. The third inductor L3 is a microstrip line, and the width-to-length ratio of the microstrip line is equal to 10 × 1550um, and the microstrip line is inductive around 2GHz and capacitive around 18 GHz.
Fig. 7 is a schematic diagram of distribution of insertion loss and return loss of an equalizing circuit according to an embodiment of the present invention, and fig. 8 is a schematic diagram of distribution of linearity of an equalizing circuit according to an embodiment of the present invention. On the basis that the parameters of each element in the equalization circuit meet the conditions, the insertion loss of the equalization circuit in the frequency band of 2-18GHz is shown as a curve W in FIG. 7, the insertion loss of the equalization circuit at 2G can be determined to be equal to 1.395dB according to the curve W, and the maximum equalization amount of the equalization circuit is equal to 26.798 dB. The return loss of the equalizing circuit in the frequency band of 2-18GHz is shown as a curve V in FIG. 7, and the return loss of the equalizing circuit can be determined to be less than-15 dB according to the curve V. The linearity of the equalizer circuit in the 2-18GHz band is shown by a curve M in fig. 8, and it can be known from fig. 7 and fig. 8 that, when the equalization amount provided by the equalizer circuit is less than 26.798dB, the return loss of the equalizer circuit is less than-15 dB, and the linearity is between-0.75 dB and 0.75dB, so that compared with the conventional equalizer circuit, the equalizer circuit can provide a higher equalization amount and better linearity while maintaining a smaller return loss and insertion loss on the basis of a limited circuit area.
The embodiment of the invention also provides an equalizer. The equalizer includes an equalization circuit of any of the preceding.
The equalizer and the equalizing circuit provided by the embodiment of the invention both adopt an unbalanced bridge T-shaped network, and the product of the resistance values of the shunt impedance module and the bridge impedance module in the unbalanced bridge T-shaped network is larger than the product of the resistance values of the first impedance module and the second impedance module, so that the equalization amount of the sideband is increased, and in addition, the resistance values of the first impedance module and the second impedance module are both smaller than 50 omega, so that the equalization amount of the sideband can be improved. The equalizing circuit also comprises two symmetrical equalizing units, the real impedance of the input port and the output port can be adjusted by the resistors in the symmetrical equalizing units, the parallel resonance units adopt large inductors and small capacitors, the series resonance units adopt small inductors and large capacitors, the return loss of linear and high-frequency signals can be optimized, the equalizing circuit can provide higher equalizing amount in limited circuit area, optimize the linearity of the signals and widen the equalizing frequency band.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (8)
1. An equalization circuit, comprising:
the system comprises an unbalanced bridging T-shaped network, a parallel resonance unit, a series resonance unit, two symmetrical linear equalization units, an input port and an output port;
the unbalanced bridged T-network comprises a first impedance module and a second impedance module connected in series between the input port and the output port, a shunt impedance module coupled at the connection of the first impedance module and the second impedance module, and a bridge impedance module in parallel with the first impedance module and the second impedance module in series; the product of the impedance of the first impedance module and the impedance of the second impedance module is smaller than the product of the impedance of the shunt impedance module and the impedance of the bridge impedance module, the impedance of the first impedance module is equal to the impedance of the second impedance module, and the impedance of the first impedance module and the impedance of the second impedance module are both smaller than 50 Ω;
the parallel resonance unit is connected in parallel with the bridge impedance module; the series resonance unit is connected in series with the shunt impedance module;
one of the symmetrical linear equalizing units is connected between the input port and the first impedance block, and the other of the symmetrical linear equalizing units is connected between the output port and the second impedance block.
2. The equalizing circuit of claim 1, wherein the bridge impedance block comprises a first resistor.
3. The equalizing circuit of claim 1, wherein the shunt impedance block comprises a second resistor having one end connected to a junction of the first impedance block and the second impedance block and another end connected to the series resonant unit.
4. The equalizing circuit of claim 1, wherein the parallel resonant unit comprises a first capacitor and a first inductor, each of the first capacitor and the first inductor being connected in parallel with the bridge impedance block.
5. The equalizing circuit of claim 4, wherein the series resonant unit comprises a second capacitor and a second inductor connected in series between the shunt impedance module and a reference terminal.
6. The equalizing circuit of claim 5, wherein the symmetric linear equalizing unit comprises a third inductor and a third resistor connected in parallel.
7. The equalizing circuit of claim 6, wherein the first inductor, the second inductor, and the third inductor each comprise a microstrip line.
8. An equalizer comprising the equalizing circuit of any one of claims 1-7.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210565812.5A CN114650025A (en) | 2022-05-24 | 2022-05-24 | Negative slope equalizer with high equalization volume, high linearity and high return loss |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210565812.5A CN114650025A (en) | 2022-05-24 | 2022-05-24 | Negative slope equalizer with high equalization volume, high linearity and high return loss |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117335766A (en) * | 2023-12-01 | 2024-01-02 | 成都世源频控技术股份有限公司 | Ultra-wideband radio frequency equalizer structure |
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| CN117335766A (en) * | 2023-12-01 | 2024-01-02 | 成都世源频控技术股份有限公司 | Ultra-wideband radio frequency equalizer structure |
| CN117335766B (en) * | 2023-12-01 | 2024-03-26 | 成都世源频控技术股份有限公司 | Ultra-wideband radio frequency equalizer structure |
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Application publication date: 20220621 |