CN114785297A - Power amplifier and input matching network thereof - Google Patents
Power amplifier and input matching network thereof Download PDFInfo
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- CN114785297A CN114785297A CN202210407157.0A CN202210407157A CN114785297A CN 114785297 A CN114785297 A CN 114785297A CN 202210407157 A CN202210407157 A CN 202210407157A CN 114785297 A CN114785297 A CN 114785297A
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- 239000003990 capacitor Substances 0.000 claims abstract description 103
- 101100074846 Caenorhabditis elegans lin-2 gene Proteins 0.000 claims abstract description 6
- 101100497386 Mus musculus Cask gene Proteins 0.000 claims abstract description 6
- 230000003321 amplification Effects 0.000 claims description 13
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 13
- 101100181929 Caenorhabditis elegans lin-3 gene Proteins 0.000 claims description 10
- 230000005764 inhibitory process Effects 0.000 abstract 1
- 230000001629 suppression Effects 0.000 description 8
- 238000004088 simulation Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
- H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/195—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
Abstract
The invention provides a power amplifier and an input matching network thereof, wherein the input matching circuit comprises a first resonator and a second resonator; the first resonator includes: the first input capacitor Cin1, the first variable capacitor VC1 connected in series with the first input capacitor Cin1, and the first inductor Lin1 connected in series with the first variable capacitor VC1, wherein the first reverse bias voltage V1 is connected to a first end of the first variable capacitor VC 1; the second resonator includes: a second variable capacitor VC2 connected with the first variable capacitor VC1 in series, and a second inductor Lin2 connected with the second variable capacitor VC2 in series, wherein the first end of the first variable capacitor VC1 is connected with a second reverse bias voltage V2; the capacitance of the first variable capacitor VC1 can be adjusted by adjusting the first reverse bias voltage V1 and the second reverse bias voltage V2, and the capacitance of the second variable capacitor VC2 can be adjusted by adjusting the second reverse bias voltage V2. The invention can realize the purpose of continuously adjusting the gain inhibition.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a power amplifier and an input matching network thereof.
Background
A radio frequency Power Amplifier (PA), which is an important component of a mobile phone communication system, is mainly used for amplifying signals. With the continuous development of mobile phone communication systems, the requirement for the transmission power of the power amplifier of the mobile phone is continuously increased. The increase in PA transmit power also requires higher power gain and therefore tends to introduce worse spurs, and the degradation of the out-of-band spurs can severely impact the quality of the communication.
Disclosure of Invention
In view of the above deficiencies of the prior art, the present invention provides a power amplifier and a radio frequency chip for suppressing and attenuating non-resonant frequency band signals and reducing the gain of the non-resonant frequency band signals.
In order to solve the above technical problem, in a first aspect, an embodiment of the present invention provides an input matching circuit for a power amplifier, the input matching circuit including a first resonator and a second resonator;
the first resonator includes: the circuit comprises a first input capacitor Cin1, a first variable capacitor VC1 connected with the first input capacitor Cin1 in series, and a first inductor Lin1 connected with the first variable capacitor VC1 in series, wherein a first reverse bias voltage V1 is connected to a first end of the first variable capacitor VC 1;
the second resonator includes: a second variable capacitor VC2 connected in series with the first variable capacitor VC1, and a second inductor Lin2 connected in series with the second variable capacitor VC2, wherein a first end of the first variable capacitor VC1 is connected with a second reverse bias voltage V2;
the capacitance of the first variable capacitor VC1 can be adjusted by adjusting the first reverse bias voltage V1 and the second reverse bias voltage V2, and the capacitance of the second variable capacitor VC2 can be adjusted by adjusting the second reverse bias voltage V2.
Preferably, the input matching circuit further includes a third resonator, the third resonator is connected in series with the first resonator, and a resonant frequency band of the third resonator is the same as an operating frequency band of the output amplifying circuit.
Preferably, the third resonator includes: the third input capacitor Cin3 is connected with the first inductor Lin1 in series, and the third inductor Lin3 is connected with the third input capacitor Cin3 in series, and an output end of the third inductor Lin3 is connected to the output amplification circuit.
Preferably, the first variable capacitor VC1 and/or the second variable capacitor VC2 are varactors.
Preferably, the output amplification circuit includes a multistage amplification circuit.
In a first aspect, an embodiment of the present invention provides a power amplifier, including: the input matching circuit and the output amplifying circuit are connected with the output end of the input matching circuit;
wherein the input matching circuit comprises a first resonator and a second resonator;
the first resonator includes: a first input capacitor Cin1, a first variable capacitor VC1 connected in series with the first input capacitor Cin1, and a first inductor Lin1 connected in series with the first variable capacitor VC1, wherein a first reverse bias voltage V1 is connected to a first end of the first variable capacitor VC 1;
the second resonator includes: a second variable capacitor VC2 connected in series with the first variable capacitor VC1, and a second inductor Lin2 connected in series with the second variable capacitor VC2, wherein a first end of the first variable capacitor VC1 is connected to a second reverse bias voltage V2;
the capacitance of the first variable capacitor VC1 can be adjusted by adjusting the first reverse bias voltage V1 and the second reverse bias voltage V2, and the capacitance of the second variable capacitor VC2 can be adjusted by adjusting the second reverse bias voltage V2.
Preferably, the input matching circuit further includes a third resonator, the third resonator is connected in series with the first resonator, and a resonant frequency band of the third resonator is the same as an operating frequency band of the output amplifying circuit.
Preferably, the third resonator includes: the third input capacitor Cin3 is connected with the first inductor Lin1 in series, and the third inductor Lin3 is connected with the third input capacitor Cin3 in series, and an output end of the third inductor Lin3 is connected to the output amplification circuit.
Preferably, the first variable capacitor VC1 and/or the second variable capacitor VC2 are varactors.
Preferably, the output amplification circuit includes a multistage amplification circuit.
Compared with the prior art, in the power amplifier, the input matching circuit can change the capacitance of the first variable capacitor VC1 and the capacitance of the second variable capacitor VC2 by changing the magnitude of the first reverse bias voltage V1 and the magnitude of the second reverse bias voltage V2, so that the suppression effect of different out-of-band gains can be realized, and the voltage is continuously adjustable, thereby achieving the purpose of continuously adjusting the gain suppression.
Drawings
The present invention will be described in detail below with reference to the accompanying drawings. The foregoing and other aspects of the invention will become more apparent and more readily appreciated from the following detailed description, taken in conjunction with the accompanying drawings. In the drawings, there is shown in the drawings,
fig. 1 is a circuit configuration diagram of a power amplifier according to an embodiment of the invention;
FIG. 2 is an equivalent circuit diagram of an input matching circuit according to an embodiment of the present invention;
FIG. 3 is a S-parameter curve of the equivalent circuit simulation of FIG. 2 according to an embodiment of the present invention;
FIG. 4 is a simulated S-parameter curve of a power amplifier under a reverse bias voltage in an embodiment of the present invention;
fig. 5 is a simulated S-parameter curve of the power amplifier under different reverse bias voltages in the embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings.
The embodiments/examples described herein are specific embodiments of the invention, are intended to be illustrative of the concepts of the invention, are exemplary and explanatory, and should not be construed as limiting the embodiments of the invention and the scope of the invention. In addition to the embodiments described herein, those skilled in the art will be able to employ other technical solutions which are obvious based on the disclosure of the claims and the specification of the present application, and these technical solutions include the technical solutions of making any obvious replacement or modification of the embodiments described herein, and are within the scope of the present invention.
Fig. 1 shows a schematic circuit diagram of a power amplifier according to the present invention, which includes: an input matching circuit 100 and an output amplifying circuit 200 connected to an output terminal of the input matching circuit 100, wherein the input matching circuit 100 includes a first resonator 110 and a second resonator 120.
Wherein the first resonator 110 includes: the circuit comprises a first input capacitor Cin1, a first variable capacitor VC1 connected with the first input capacitor Cin1 in series, and a first inductor Lin1 connected with the first variable capacitor VC1 in series, wherein a first reverse bias voltage V1 is connected to a first end of the first variable capacitor VC 1. The second resonator 120 includes: the first end of the first variable capacitor VC1 is connected with a second reverse bias voltage V2, and the second variable capacitor VC2 is connected with the first variable capacitor VC1 in series, and the second inductor Lin2 is connected with the second variable capacitor VC2 in series. The capacitance of the first variable capacitor VC1 can be adjusted by adjusting the first reverse bias voltage V1 and the second reverse bias voltage V2, and the capacitance of the second variable capacitor VC2 can be adjusted by adjusting the second reverse bias voltage V2.
In this embodiment, the output amplifier circuit may include a multi-stage amplifier circuit, and as a specific implementation, the output amplifier circuit 200 includes: the amplifier comprises a first-stage amplifying circuit 210, a second-stage amplifying circuit 220 and a third-stage amplifying circuit 230, wherein the first-stage amplifying circuit 210 is connected with the second-stage amplifying circuit 220 in a matched mode through a first interstage matching circuit 211, the second-stage amplifying circuit 220 is connected with the third-stage amplifying circuit 230 in a matched mode through a second interstage matching circuit 221, and the third-stage amplifying circuit 230 is connected with an output matching circuit 231 in a matched mode.
As shown in fig. 2, in this embodiment, the first input capacitor Cin1 is connected in series with the first variable capacitor VC1, so the equivalent capacitance can be expressed as follows:
C＝Cin1*VC1/(Cin1+VC1)＝VC1/(1+VC1/Cin1) (1)
from equation (1), it can be seen that if the first input capacitor Cin1 approaches infinity, the size of the first input capacitor Cin1 and the first variable capacitor VC connected in series depends on the size of the first variable capacitor VC 1. The equivalent circuit of the input matching circuit 100 in fig. 1 is shown in fig. 2.
Fig. 3 is an S-parameter curve of the equivalent circuit simulation of fig. 2 in this embodiment, which is illustrated by taking two frequency points m1 and m2 as examples, and the principle of the generated gain suppression is as follows:
with reference to fig. 2, the impedance of the first equivalent capacitor C1 and the first equivalent inductor L1 constituting the first resonant network can be represented as:
the second equivalent capacitor C2 and the second equivalent inductor L2 form a second resonant network, and the impedance of the second resonant network can be expressed as:
order to
From the equation (2), the impedance Z111 of the first resonator resonates at ω α. When ω < ω α, the impedance Z111 of the first resonator is capacitive, and when ω > ω α, the impedance Z111 of the first resonator is inductive. From equation (3), the impedance Z112 of the second resonator resonates at ω β. When ω < ω β, the impedance Z111 of the first resonator is inductive, and when ω > ω β, the impedance Z111 of the first resonator is capacitive.
The impedance of the filter formed by the first resonator and the second resonator can be expressed as:
it is clear that the equation ω4L1L1C1C2-ω2(L1C1+L1C2+L2C2) There are four roots present when +1 ═ 0. The four roots can be divided into two pairs, each pair of roots being opposite numbers to each other. The parameters of the first equivalent capacitor C1, the second equivalent capacitor C2, the first equivalent inductor L1 and the second equivalent inductor L2 can be configured appropriately, so that the two pairs of roots respectively correspond to two resonant frequencies m1 and m 2. That is, the impedance Z11 of the filter is very small, close to zero, at the frequency around m1 and around m 2. Thereby, the filter has larger attenuation around two frequencies of m1 and m2, and the non-resonant frequency band signals in the input end signals are suppressed and attenuated.
Further, the input matching circuit 100 of this embodiment further includes a third resonator 130, where the third resonator 130 is arranged in series with the first resonator 110, and a resonant frequency band of the third resonator 130 is the same as an operating frequency band of the output amplifying circuit 200. One of the functions of the third resonator 130 is to adjust impedance, and the other is to form a series resonant network, where the resonant frequency band is the working frequency band of the power amplifier, and forms a high resistance to the non-resonant frequency band, so as to have a certain suppression effect on out-of-band gain.
Specifically, the third resonator includes: the third input capacitor Cin3 is connected with the first inductor Lin1 in series, and the third inductor Lin3 is connected with the third input capacitor Cin3 in series, and an output end of the third inductor Lin3 is connected to the output amplification circuit.
Referring to fig. 4, fig. 4 is an S-parameter simulation curve of the power amplifier when the first reverse bias voltage V1 is 20V and the second reverse bias voltage V2 is 5V. With continuing reference to fig. 5, fig. 5 is a graph of S-parameters of a power amplifier simulated by two different voltage levels of the first reverse bias voltage V1 and the second reverse bias voltage V2. The thick line is a simulation curve when V1 is 45V, V2 is 25V, and the thin line (see fig. 4) is a simulation curve when V1 is 20V, V2 is 5V. It can be seen from comparison between fig. 4 and fig. 5 that the magnitudes of the first reverse bias voltage V1 and the second reverse bias voltage V2 are changed to change the magnitudes of the capacitances of the first variable capacitor VC1 and the second variable capacitor VC2, so that different out-of-band gain suppression effects can be achieved, and the voltage is continuously adjustable, thereby achieving the purpose of continuously adjusting the gain suppression.
In this embodiment, the first variable capacitor VC1 and/or the second variable capacitor VC2 are varactors.
Compared with the prior art, in the power amplifier, the input matching circuit can change the capacitance of the first variable capacitor VC1 and the capacitance of the second variable capacitor VC2 by changing the magnitude of the first reverse bias voltage V1 and the magnitude of the second reverse bias voltage V2, so that the suppression effect of different out-of-band gains can be realized, and the voltage is continuously adjustable, thereby achieving the purpose of continuously adjusting the gain suppression.
It should be noted that the related capacitors, inductors, resistors and circuit modules adopted in the present invention are all circuit modules and components commonly used in the art, and the corresponding specific indexes and parameters are adjusted according to practical applications, which are not described in detail herein.
It should be noted that the above-mentioned embodiments described with reference to the drawings are only intended to illustrate the present invention and not to limit the scope of the present invention, and it should be understood by those skilled in the art that modifications and equivalent substitutions can be made without departing from the spirit and scope of the present invention. Furthermore, unless the context indicates otherwise, words that appear in the singular include the plural and vice versa. Additionally, all or a portion of any embodiment may be utilized with all or a portion of any other embodiment, unless stated otherwise.
Claims (10)
1. An input matching circuit for a power amplifier, the input matching circuit comprising a first resonator and a second resonator;
the first resonator includes: a first input capacitor Cin1, a first variable capacitor VC1 connected in series with the first input capacitor Cin1, and a first inductor Lin1 connected in series with the first variable capacitor VC1, wherein a first reverse bias voltage V1 is connected to a first end of the first variable capacitor VC 1;
the second resonator includes: a second variable capacitor VC2 connected in series with the first variable capacitor VC1, and a second inductor Lin2 connected in series with the second variable capacitor VC2, wherein a first end of the first variable capacitor VC1 is connected to a second reverse bias voltage V2;
the capacitance of the first variable capacitor VC1 can be adjusted by adjusting the first reverse bias voltage V1 and the second reverse bias voltage V2, and the capacitance of the second variable capacitor VC2 can be adjusted by adjusting the second reverse bias voltage V2.
2. The input matching circuit for the power amplifier as recited in claim 1, further comprising a third resonator, said third resonator being disposed in series with said first resonator, said third resonator having a resonant frequency band that is the same as an operating frequency band of said output amplifying circuit.
3. The input matching circuit for a power amplifier of claim 2, wherein the third resonator comprises: a third input capacitor Cin3 connected in series with the first inductor Lin1, and a third inductor Lin3 connected in series with the third input capacitor Cin3, wherein an output end of the third inductor Lin3 is connected to the output amplification circuit.
4. The input matching circuit for the power amplifier according to claim 1, wherein the first variable capacitor VC1 and/or the second variable capacitor VC2 is a varactor.
5. The input matching circuit for a power amplifier of claim 1, wherein the output amplification circuit comprises a multi-stage amplification circuit.
6. A power amplifier, comprising: the input matching circuit and the output amplifying circuit are connected with the output end of the input matching circuit;
wherein the input matching circuit comprises a first resonator and a second resonator;
the first resonator includes: a first input capacitor Cin1, a first variable capacitor VC1 connected in series with the first input capacitor Cin1, and a first inductor Lin1 connected in series with the first variable capacitor VC1, wherein a first reverse bias voltage V1 is connected to a first end of the first variable capacitor VC 1;
the second resonator includes: a second variable capacitor VC2 connected in series with the first variable capacitor VC1, and a second inductor Lin2 connected in series with the second variable capacitor VC2, wherein a first end of the first variable capacitor VC1 is connected to a second reverse bias voltage V2;
the capacitance of the first variable capacitor VC1 can be adjusted by adjusting the first reverse bias voltage V1 and the second reverse bias voltage V2, and the capacitance of the second variable capacitor VC2 can be adjusted by adjusting the second reverse bias voltage V2.
7. The power amplifier of claim 1, wherein the input matching circuit further comprises a third resonator, the third resonator being arranged in series with the first resonator, the third resonator having a resonant frequency band that is the same as an operating frequency band of the output amplifying circuit.
8. The power amplifier of claim 2, wherein the third resonator comprises: a third input capacitor Cin3 connected in series with the first inductor Lin1, and a third inductor Lin3 connected in series with the third input capacitor Cin3, wherein an output end of the third inductor Lin3 is connected to the output amplification circuit.
9. The power amplifier according to claim 1, wherein the first variable capacitor VC1 and/or the second variable capacitor VC2 are varactors.
10. The power amplifier of claim 1, wherein the output amplification circuit comprises a multi-stage amplification circuit.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210407157.0A CN114785297A (en) | 2022-04-18 | 2022-04-18 | Power amplifier and input matching network thereof |
| PCT/CN2023/082963 WO2023202310A1 (en) | 2022-04-18 | 2023-03-22 | Power amplifier and input matching network thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210407157.0A CN114785297A (en) | 2022-04-18 | 2022-04-18 | Power amplifier and input matching network thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023202310A1 (en) * | 2022-04-18 | 2023-10-26 | 深圳飞骧科技股份有限公司 | Power amplifier and input matching network thereof |
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| WO2023202310A1 (en) * | 2022-04-18 | 2023-10-26 | 深圳飞骧科技股份有限公司 | Power amplifier and input matching network thereof |
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| WO2023202310A1 (en) | 2023-10-26 |
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