CN114649215A

CN114649215A - Method for manufacturing electronic device

Info

Publication number: CN114649215A
Application number: CN202111237369.0A
Authority: CN
Inventors: 纪仁海
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2020-12-18
Filing date: 2021-10-22
Publication date: 2022-06-21

Abstract

The present disclosure provides a method for manufacturing an electronic device, including providing a first carrier, disposing a first substrate on the first carrier, disposing a first conductive structure on the first substrate, removing the first carrier, providing a second carrier, disposing a second substrate on the second carrier, disposing a second conductive structure on the second substrate, removing the second carrier, and combining the first substrate and the second substrate.

Description

Method for manufacturing electronic device

Technical Field

The present disclosure relates to electronic devices, and more particularly, to a method for fabricating an electronic device with two substrates combined.

Background

In some electronic devices, two conductive layers are spaced apart by a suitable distance to meet specific application requirements. If two conductive layers are formed on the same substrate, the two conductive layers are separated by a distance, for example, a dielectric layer, and when the thickness of the dielectric layer is too thick, the substrate warpage problem may occur. Therefore, a process method is needed to simultaneously separate two conductive layers with a proper distance and improve the warpage of the substrate.

Disclosure of Invention

According to an embodiment of the present disclosure, a method for manufacturing an electronic device includes providing a first carrier, disposing a first substrate on the first carrier, disposing a first conductive structure on the first substrate, removing the first carrier, providing a second carrier, disposing a second substrate on the second carrier, disposing a second conductive structure on the second substrate, removing the second carrier, and combining the first substrate and the second substrate.

Drawings

Fig. 1A-1I are schematic partial cross-sectional views of a manufacturing flow of an electronic device according to some embodiments of the present disclosure;

FIG. 2 is a schematic partial cross-sectional view of an electronic device according to some embodiments of the present disclosure;

fig. 3 is a top view schematic diagram of an electronic device according to some embodiments of the present disclosure.

Detailed Description

So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, examples of which are illustrated in the appended drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Certain terms are used throughout the description and following claims to refer to particular components. Those skilled in the art will appreciate that electronic device manufacturers may refer to a same component by different names. This document does not intend to distinguish between components that differ in function but not name. In the following specification and claims, the words "comprise", "comprising", "includes" and "including" are open-ended words, and thus should be interpreted to mean "including, but not limited to …".

Directional phrases used herein, such as: "up", "down", "front", "back", "left", "right", etc., refer only to the orientation of the figures. Accordingly, the directional terminology is used for purposes of illustration and is in no way limiting. In the drawings, various figures illustrate general features of methods, structures and/or materials used in particular embodiments. These drawings, however, should not be construed as defining or limiting the scope or nature encompassed by these embodiments. For example, the relative sizes, thicknesses, and locations of various film layers, regions, and/or structures may be reduced or enlarged for clarity.

The description of a structure (or layer, element, substrate) on/over another structure (or layer, element, substrate) in the present disclosure may refer to two structures being adjacent and directly connected, or may refer to two structures being adjacent and not directly connected. By indirectly connected, it is meant that there is at least one intermediate structure (or intermediate layer, intermediate assembly, intermediate substrate, intermediate spacer) between the two structures, the lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure may be a single-layer or multi-layer solid structure or a non-solid structure, and is not limited. In the present disclosure, when a structure is "on" another structure, it may mean that the structure is "directly" on the other structure or "indirectly" on the other structure, that is, at least one structure is sandwiched between the structure and the other structure.

The terms "about," "equal to," or "the same," "substantially," or "approximately" are generally construed as being within 20% of a given value or range, or as being within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range.

The use of ordinal numbers such as "first," "second," etc., in the specification and claims to modify an element is not by itself intended to imply any previous order to the element(s), nor the order in which an element is sequenced or in which it is sequenced or which order is in a manner which causes the element(s) with which it is/are sequenced or which should be sequenced in a manner which requires that the element(s) with which it is/are sequenced be sequenced or otherwise sequenced in a manner which allows for a clear distinction between the element(s) which is/are given a certain name and another element which is/are given the same name. The claims may not use the same words in the specification and accordingly, a first element in a specification may be a second element in a claim.

The electrical connection or coupling described in the present disclosure may refer to a direct connection or an indirect connection, in which case, the terminals of the two circuit components are directly connected or connected with each other by a conductor segment, and in which case, the terminals of the two circuit components have a switch, a diode, a capacitor, an inductor, a resistor, other suitable components, or a combination of the above components, but is not limited thereto.

In the present disclosure, the thickness, length and width may be measured by an optical microscope, and the thickness or width may be measured by a cross-sectional image of an electron microscope, but not limited thereto. In addition, there may be some error in any two values or directions for comparison. In addition, the terms "equal," "identical," "substantially," or "substantially" as referred to in this disclosure generally represent 10% of the range of a given value or range. Further, the phrase "a given range is from a first value to a second value," and "a given range is within a range from a first value to a second value" means that the given range includes the first value, the second value, and other values therebetween. If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

It is to be understood that the following disclosure is illustrative of various embodiments, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the disclosure. Features of the various embodiments may be combined and matched as desired, without departing from the spirit or ambit of the invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In the present disclosure, the electronic device may include a display device, a backlight device, an antenna device, a sensing device or a splicing device, but is not limited thereto. The electronic device can be a bendable or flexible electronic device. The display device may be a non-self-luminous type display device or a self-luminous type display device. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device, and the sensing device may be a sensing device for sensing capacitance, light, heat or ultrasonic waves, but not limited thereto. In the present disclosure, the electronic devices may include passive devices and active devices, such as capacitors, resistors, inductors, diodes, transistors, IC chips, etc. The diode may comprise a light emitting diode or a photodiode. The light emitting diode may include, for example, an Organic Light Emitting Diode (OLED), a submillimeter light emitting diode (mini LED), a micro light emitting diode (micro LED), or a quantum dot light emitting diode (quantum dot LED), but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device can be any permutation and combination of the foregoing, but not limited thereto. The present disclosure will be described below with reference to a display device as an electronic device or a tiled device, but the disclosure is not limited thereto.

It should be noted that the technical solutions provided in the following different embodiments can be used alternatively, combined or mixed with each other to form another embodiment without departing from the spirit of the present disclosure.

Fig. 1A-1I are schematic partial cross-sectional views of a manufacturing flow of an electronic device according to some embodiments of the present disclosure. Referring to fig. 1A, the manufacturing process of the electronic device may include providing a first carrier C1, and disposing a release layer R1 and a first substrate SUB1 on the first carrier C1, but is not limited thereto. In other words, the release layer R1 may be disposed on the first carrier C1 and between the first carrier C1 and the first substrate SUB 1. In other embodiments, other layers may be further disposed between the release layer R1 and the first substrate SUB1 as required. In some embodiments, the first carrier plate C1 may have a material with supportive properties. The rigid carrier may include, but is not limited to, a quartz substrate, a glass substrate, a ceramic substrate, a sapphire substrate, a hybrid soft-hard plate, other hard substrates, or a combination thereof. In some embodiments, the release layer R1 can be used to temporarily fix the first substrate SUB1 on the first carrier C1. In some embodiments, the release layer R1 may include, but is not limited to, a laser release layer or other types of release layers. In some embodiments, the release layer R1 can be released, for example, physically or chemically, but not limited thereto.

The first substrate SUB1 may be disposed on the release layer R1. The first substrate SUB1 may include a flexible substrate, a bendable substrate, a rigid substrate, or a combination thereof, but is not limited thereto. For example, the material of the first substrate SUB1 may include, but is not limited to, a polymer, other suitable materials, or a combination thereof. For example, the material of the first substrate SUB1 may include, but is not limited to, PET, Polyimide (Polyimide), Liquid Crystal Polymer (LCP), Cyclic Olefin Polymer (COP), epoxy resin, ajinomoto build-up Film (ABF), Bismaleimide (bismalimide), fluorine resin (fluoroesin), and/or other suitable materials or combinations thereof. In some embodiments, the first substrate SUB1 may include, for example, glass, ceramic, quartz, sapphire, or a combination thereof, but is not limited thereto. In some embodiments, the material of the first substrate SUB1 may have a low Dielectric Loss (Df) characteristic, but is not limited thereto.

In some embodiments, the thickness T1 of the first substrate SUB1 can be greater than or equal to 5 μm and less than or equal to 1000 μm (5 μm ≦ thickness T1 ≦ 1000 μm), but not limited thereto. In some embodiments, the thickness T1 of the first substrate SUB1 may be greater than or equal to 50 μm and less than or equal to 900 μm (50 μm ≦ thickness T1 ≦ 900 μm). In some embodiments, the thickness T1 of the first substrate SUB1 may be greater than or equal to 150 μm and less than or equal to 800 μm (150 μm ≦ thickness T1 ≦ 800 μm). In some embodiments, the first substrate SUB1 may comprise a single layer material or a composite layer material. The thickness T1 of the first substrate SUB1 may vary according to the selected material or the number of layers.

The process flow of manufacturing the electronic device may include disposing the first conductive structure CS1 on the first substrate SUB 1. In detail, in some embodiments, a conductive layer CL1 is disposed on the first substrate SUB1, and the dielectric layer DL1 may be selectively disposed between the first substrate SUB1 and the conductive layer CL 1. In some embodiments, the material of the dielectric layer DL1 may include, but is not limited to, silicon nitride (SiNx), silicon oxide (SiOx), other suitable materials, or combinations thereof. By disposing the dielectric layer DL1 between the first substrate SUB1 and the conductive layer CL1, the yield of the conductive layer CL1 attached to the first substrate SUB1 can be improved, so as to reduce the chance of peeling (peeling) of the first substrate SUB 1. In addition, the dielectric layer DL1 can reduce the chance of the first substrate SUB1 being invaded by water oxygen. In other words, the dielectric layer DL1 may be directly disposed on the first substrate SUB 1. In other embodiments (not shown), the conductive layer CL1 can be directly disposed on the first substrate SUB1, but is not limited thereto. In other words, there is no other layer between the conductive layer CL1 and the second substrate SUB 1. In some embodiments, a protective layer PL1 may be disposed on the first substrate SUB1, and the protective layer PL1 may be disposed on the conductive layer CL1, but is not limited thereto. In some embodiments, other layers may be disposed between the above-mentioned stacks or any number of layers may be deleted as required.

In some embodiments, when the dielectric layer DL1 is disposed between the first substrate SUB1 and the conductive layer CL1, the dielectric layer DL1 may be a patterned dielectric layer. For example, the dielectric layer DL1 may include an opening a1 exposing a portion of the first substrate SUB 1.

In some embodiments, conductive layer CL1 may be disposed between dielectric layer DL1 and protective layer PL1, and conductive layer CL1 may be a patterned conductive layer. For example, the conductive layer CL1 may partially cover the dielectric layer DL1 and extend into the opening a1 to cover the sidewall of the dielectric layer DL1 exposed by the opening a 1. In some embodiments, the conductive layer CL1 may contact a portion of the first substrate SUB1 through the opening a 1. In some embodiments, conductive layer CL1 may comprise a single conductive layer or multiple conductive layers. In some embodiments, the material of conductive layer CL1 may include a metal, such as, but not limited to, titanium (Ti), copper (Cu), aluminum (Al), molybdenum (Mo), other suitable materials, or combinations thereof.

Through the above manufacturing process, the first conductive structure CS1 is disposed on the first substrate SUB 1. In some embodiments, the first conductive structure CS1 may include at least one conductive layer (e.g., conductive layer CL1) and at least one dielectric layer (e.g., dielectric layer DL1), but is not limited thereto.

In some embodiments, the protective layer PL1 may be disposed on the first conductive structure CS1 (including the dielectric layer DL1 and/or the conductive layer CL1), but is not limited thereto. The protective layer PL1 may be a patterned protective layer. For example, the protection layer PL1 may include an opening a2 exposing a portion of the first substrate SUB 1. In some embodiments, the opening a2 of the protection layer PL1 may overlap with the opening a1 of the dielectric layer DL1 in a normal direction (e.g., the direction Z) of the first substrate SUB 1. In some embodiments, in a normal direction (e.g., the direction Z) of the first substrate SUB1, an area (not labeled) of the opening a2 of the protection layer PL1 projected on the first substrate SUB1 may be, for example, greater than or equal to an area (not labeled) of the opening a1 of the dielectric layer DL1 projected on the first substrate SUB1, but is not limited thereto.

In some embodiments, the opening a2 of the protection layer PL1 may expose a portion of the conductive layer CL1, for example, the conductive layer CL1 extending into the opening a1 may be exposed. In some embodiments, the material of the protection layer PL1 may include, but is not limited to, silicon nitride (SiNx), silicon oxide (SiOx), other suitable materials, or combinations thereof. Protective layer PL1 reduced the chance of conductive layer CL1 being attacked by water and oxygen.

Referring to fig. 1B, the manufacturing process of the electronic device may further include, but is not limited to, disposing the protection layer PL2 on the protection layer PL 1. In some embodiments, Protective layer PL2 may be used as a Temporary Protective Film (TPF). In some embodiments, the protection layer PL2 may be removed, for example, in a subsequent manufacturing flow of the electronic device (refer to fig. 1G), but is not limited thereto. In some embodiments, protective layer PL2 may comprise a single layer of material or a composite material. When protective layer PL2 is a composite material, it may include a combination of film layers, glue layers, and/or other suitable materials, but is not limited thereto. The film layer includes, for example, but is not limited to, polyethylene terephthalate (PET), Polyimide (Polyimide PI), other suitable materials, and/or combinations thereof. Examples of the adhesive include, but are not limited to, pressure sensitive adhesive, acrylic adhesive, Epoxy (Epoxy), silicone (silicon), other suitable materials, and/or combinations thereof.

Referring to fig. 1B, in some embodiments, the manufacturing process of the electronic device may further include removing the first carrier C1. For example, after the protective layer PL2 is formed, the first carrier C1 and the first substrate SUB1 can be separated by performing a releasing step on the releasing layer R1. In some embodiments, the protection layer PL2 may have a supporting property, which may be used to support the first substrate SUB1 after removing the first carrier C1, but is not limited thereto.

Referring to fig. 1C, the manufacturing process of the electronic device may further include providing a second carrier C2, and disposing a release layer R2 and a second substrate SUB2 on the second carrier C2. In other embodiments, other layers may be further disposed between the release layer R2 and the second substrate SUB2 as required. In some embodiments, carrier plate C2 may have a material with supportive properties. The carrier C2 may include, but is not limited to, a quartz substrate, a glass substrate, a ceramic substrate, a sapphire substrate, a hybrid soft-hard plate, other hard substrates, or a combination thereof. In some embodiments, the release layer R2 may be used to temporarily fix the second substrate SUB2 on the carrier C2.

In some embodiments, the release layer R2 may include, but is not limited to, a laser release layer or other types of release layers. In some embodiments, the release layer R2 can be released, for example, physically or chemically, but not limited thereto.

Referring to fig. 1C, the second substrate SUB1 can be disposed on the release layer R2. The second substrate SUB2 may include a flexible substrate, a bendable substrate, a rigid substrate, or a combination thereof, but is not limited thereto. For example, the material of the second substrate SUB2 may be a polymer, other suitable materials, or a combination thereof, but is not limited thereto. For example, the material of the second substrate SUB2 may include, but is not limited to, PET, polyimide, liquid crystal polymer, Cyclic Olefin Polymer (COP), epoxy resin, ajinomoto film (ABF), bismaleimide, fluorine resin, and/or other suitable materials or combinations thereof. In some embodiments, the material of the second substrate SUB2 may include, for example, glass, ceramic, quartz, sapphire, or a combination thereof, but is not limited thereto. In some embodiments, the material of the second substrate SUB2 may have a low Dielectric Loss (Df) characteristic, but is not limited thereto. In some embodiments, the thickness T2 of the second substrate SUB2 can be greater than or equal to 5 μm and less than or equal to 1000 μm (5 μm ≦ thickness T2 ≦ 1000 μm), but not limited thereto. In some embodiments, the thickness T2 of the second substrate SUB2 may be greater than or equal to 50 μm and less than or equal to 900 μm (50 μm ≦ thickness T2 ≦ 900 μm). In some embodiments, the thickness T2 of the second substrate SUB2 can be greater than or equal to 150 μm and less than or equal to 800 μm (150 μm ≦ thickness T2 ≦ 800 μm). In some embodiments, the second substrate SUB2 may comprise a single layer material or a composite layer material. The thickness T2 of the second substrate SUB2 may vary according to the selected material or the number of layers.

In some embodiments, the sum of the thickness T1 of the first substrate SUB1 and the thickness T2 of the second substrate SUB2 can be greater than or equal to 10 μm and less than or equal to 2000 μm (10 μm ≦ T1+ T2 ≦ 2000 μm), but is not limited thereto. In some embodiments, the sum of the thickness T1 of the first substrate SUB1 and the thickness T2 of the second substrate SUB2 may be greater than or equal to 100 μm and less than or equal to 1700 μm (100 μm ≦ T1+ T2 ≦ 1700 μm). In some embodiments, the sum of the thickness T1 of the first substrate SUB1 and the thickness T2 of the second substrate SUB2 may be greater than or equal to 200 μm and less than or equal to 1500 μm (200 μm ≦ T1+ T2 ≦ 1500 μm). In some embodiments, when the electronic device is applied to an antenna, the sum of the thickness T1 of the first substrate SUB1 and the thickness T2 of the second substrate SUB2 may be designed according to the frequency applied to the electronic device, for example, the frequency and the "sum of the thicknesses T1 and T2" may be in an approximately inverse relationship, but not limited thereto.

In some embodiments, the material of at least one of the first substrate SUB1 and the second substrate SUB2 is a polymer. In some embodiments, the first substrate SUB1 and the second substrate SUB2 are polymers. In some embodiments, the thickness T1 of the first substrate SUB1 and the thickness T2 of the second substrate SUB may be the same or different. In some embodiments, the first substrate SUB1 and the second substrate SUB2 are different in area. In some embodiments, the material of the first substrate SUB1 may be the same as or different from the material of the second substrate SUB, for example.

Referring to fig. 1C, the manufacturing process of the electronic device may further include disposing a second conductive structure CS2 on a second substrate SUB 2. In detail, in some embodiments, the conductive layer CL2 is disposed on the second substrate SUB 2. In some embodiments, the dielectric layer DL2 can be selectively disposed between the second substrate SUB2 and the conductive layer CL 2. In some embodiments, the material of the dielectric layer DL2 may include, but is not limited to, silicon nitride (SiNx), silicon oxide (SiOx), other suitable materials, or combinations thereof. By disposing the dielectric layer DL2 between the second substrate SUB2 and the conductive layer CL2, the yield of the conductive layer CL2 adhering to the second substrate SUB2 can be improved, so as to reduce the chance of peeling the second substrate SUB 2. In addition, the dielectric layer DL2 can reduce the chance of the second substrate SUB2 being invaded by water and oxygen. In other embodiments (not shown), the conductive layer CL2 can be directly disposed on the second substrate SUB2, but is not limited thereto. In other words, there is no other layer between the conductive layer CL2 and the second substrate SUB 2. In some embodiments, a dielectric layer DL3, a conductive layer CL3, and/or a protective layer PL3 may be disposed on the conductive layer CL2, but are not limited thereto. Other layers may be provided between the above stacks or any number of layers may be deleted as desired.

In some embodiments, a dielectric layer DL2 may be disposed on the second substrate SUB2 and between the second substrate SUB2 and the conductive layer CL 2. Dielectric layer DL2 may be a patterned dielectric layer. For example, the dielectric layer DL2 may include an opening A3 exposing the second substrate SUB 2. In some embodiments, the dielectric layer DL2 is made of a material similar to that of the dielectric layer DL1, and thus the description is not repeated. In some embodiments, the dielectric layer DL2 may be used to reduce the chance of the second substrate SUB2 being invaded by water oxygen, or to reduce the problem of peeling of the second substrate SUB 2.

In some embodiments, conductive layer CL2 may be disposed between dielectric layer DL2 and dielectric layer DL3, and conductive layer CL2 may be a patterned conductive layer. For example, the conductive layer CL2 can partially cover the dielectric layer DL2 and extend into the opening A3 to cover the sidewall of the dielectric layer DL2 exposed by the opening A3. In some embodiments, the conductive layer CL2 may contact a portion of the second substrate SUB2 through the opening A3. In some embodiments, conductive layer CL2 can be a single conductive layer or multiple conductive layers. The material of conductive layer CL2 may include a metal, such as titanium, copper, aluminum (Al), molybdenum (Mo), other suitable materials, or a combination thereof, but is not limited thereto.

In some embodiments, dielectric layer DL3 may be disposed on conductive layer CL2 and between conductive layer CL2 and conductive layer CL 3. Dielectric layer DL3 may be a patterned dielectric layer. Dielectric layer DL3 may include an opening a4 that exposes a portion of conductive layer CL 2. In some embodiments, in the normal direction of the second substrate SUB2, the opening a4 of the dielectric layer DL3 may not overlap with the opening A3 of the dielectric layer DL 2. In some embodiments, the material of the dielectric layer DL3 may include, but is not limited to, silicon nitride, silicon oxide, Epoxy (Epoxy), acryl, maleimide (bismalemide), polyimide (polyimide), photoresist, other suitable materials, or combinations thereof. In some embodiments, dielectric layer DL3 may have Solder Resist material (Solder Resist) properties.

In some embodiments, a conductive layer CL3 may be disposed on dielectric layer DL3 and between dielectric layer DL3 and protective layer PL 3. Conductive layer CL3 may be a patterned conductive layer. For example, conductive layer CL3 may partially cover dielectric layer DL 3. In some embodiments, a portion of conductive layer CL3 can extend into opening a4 and contact a portion of conductive layer CL 2. In some embodiments, a portion of the conductive layer CL3 may extend into the opening a4 and contact a portion of the sidewall of the dielectric layer DL3 exposed by the opening a4, but is not limited thereto. In some embodiments, conductive layer CL3 can be a single conductive layer or multiple conductive layers. The material of conductive layer CL3 can be similar to conductive layer CL2, and thus the description will not be repeated.

In some embodiments, a protective layer PL3 may be disposed on dielectric layer DL3 and conductive layer CL 3. The protective layer PL3 may be a patterned protective layer. For example, the protection layer PL3 may have an opening a5 exposing the local conductive layer CL3, and an opening a 5' exposing the local conductive layer CL3 and the local dielectric layer DL3, but not limited thereto. In some embodiments, the material of the protection layer PL3 may include, but is not limited to, silicon nitride, silicon oxide (SiOx), other suitable materials, or combinations thereof. In some embodiments, protective layer PL3 may be used to reduce the chance of moisture ingress.

Through the above manufacturing process, the second conductive structure CS2 is disposed on the second substrate SUB 2. In some embodiments, the second conductive structure CS2 may include at least one conductive layer (e.g., conductive layer CL2 and/or conductive layer CL3) and at least one dielectric layer (e.g., dielectric layer DL2 and/or dielectric layer DL3), but is not limited thereto.

Referring to fig. 1D, the process flow of manufacturing the electronic device may further include forming a protection layer PL4 on the protection layer PL 3. In some embodiments, protective layer PL4 may be a temporary protective film, but is not limited thereto. In some embodiments, the protection layer PL4 may be removed, for example, in a subsequent manufacturing process of the electronic device (refer to fig. 1G), but is not limited thereto. In some embodiments, the material of the protection layer PL4 may be similar to the protection layer PL2, and thus the description will not be repeated.

In some embodiments, the manufacturing process of the electronic device may further include removing the carrier board C2. For example, after the protective layer PL4 is formed, the second carrier C2 and the second substrate SUB2 can be separated by performing a releasing step on the release layer R2. In some embodiments, the protection layer PL4 may have a supporting property, which may be used to support the second substrate SUB2 after removing the second carrier C2, but is not limited thereto.

In some embodiments, the steps shown in fig. 1C and 1D may be performed after the steps shown in fig. 1A and 1B are completed. Alternatively, the steps shown in fig. 1A and 1B may be continued after the steps shown in fig. 1C and 1D are completed. The number of the conductive layers, the dielectric layers and/or the protective layers shown in fig. 1A to 1D is only an example, and the number of the conductive layers, the dielectric layers and/or the protective layers formed on the first substrate SUB1 or the second substrate SUB2 may be changed as required. In addition, the corresponding relationship between the number of the openings or the arrangement of the layers shown in fig. 1A to 1D is only an example, and can be adjusted according to the requirement.

Referring to fig. 1E, the process flow of manufacturing the electronic device may include combining the first substrate SUB1 and the second substrate SUB 2. For example, in some embodiments, the first substrate SUB1 may be bonded (or attached) to the second substrate SUB2 through the glue material GL. The glue material GL may include acrylic glue, epoxy glue, pressure sensitive glue, Ultraviolet (UV) glue, other suitable materials, or a combination thereof, but is not limited thereto. After the first substrate SUB1 is attached to the second substrate SUB2, the opening a1 of the dielectric layer DL1 may substantially overlap the opening A3 of the dielectric layer DL2 in the normal direction (e.g., direction Z) of the first substrate SUB 1. In a normal direction (e.g., the direction Z) of the first substrate SUB1, the opening a 5' of the dielectric layer DL3 may substantially overlap the opening A3 of the dielectric layer DL2 and/or the opening a1 of the dielectric layer DL 1.

Referring to fig. 1F, the process of manufacturing the electronic device may further include performing a via process on the combined (or bonded) first substrate SUB1 and second substrate SUB2 to form a via hole TH, wherein the via hole TH may penetrate through the first substrate SUB1 and the second substrate SUB 2. The via process may include, but is not limited to, laser or other suitable methods to form the via hole TH. In the normal direction (e.g., the direction Z) of the first substrate SUB1, the formation position of the through hole TH may overlap the opening a1, the opening A3 and/or the opening a 5', for example. In some embodiments, the via hole TH may, for example, expose a portion of the conductive layer (conductive layer CL1, conductive layer CL2, and/or conductive layer CL 3).

In some embodiments, as shown in fig. 1F, a through hole process may be performed, for example, from the second substrate side, so that the through hole TH has different aperture widths at different cross-sectional cross-sections. For example, the sectional shape of the through hole TH may approximate an inverted trapezoid, but is not limited thereto. In detail, a width R3 of the via hole TH corresponding to the aperture at the conductive layer CL3 may be, for example, greater than a width R2 of the via hole TH corresponding to the aperture at the conductive layer CL2, and a width R2 of the via hole TH corresponding to the aperture at the conductive layer CL2 may be, for example, greater than a width R1 of the via hole TH corresponding to the aperture at the conductive layer CL1, but is not limited thereto. The width R3 of the aperture and the width R2 of the aperture may be measured, for example, in a cross section corresponding to the width of the aperture measured at the surface of the conductive layer farthest from the second substrate SUB 2. In addition, the width R1 of the aperture may be measured on the same cross section, for example, corresponding to the width of the aperture measured at the surface of the conductive layer CL1 farthest from the first substrate SUB 1.

In other embodiments (not shown), the through hole process may be performed, for example, from one side of the first substrate SUB1, such that the cross-sectional shape of the through hole TH approximates an upright trapezoid. For example, the width R1 of the aperture described above may be, for example, greater than the width R2 of the aperture, and the width R2 of the aperture may be, for example, greater than the width R3 of the aperture. Alternatively, in other embodiments (not shown), the through-hole processes may be separately performed from one side of the second substrate SUB2 and one side of the first substrate SUB1, respectively, such that the cross-sectional shape of the through-hole TH approximates an hourglass shape. For example, the width of the aperture of the through hole TH at the surface of the corresponding protection layer PL4 far from the second substrate SUB2 may be, for example, larger than the width of the aperture of the through hole TH at the corresponding glue GL, and the width of the aperture of the through hole TH at the surface of the corresponding protection layer PL2 far from the first substrate SUB1 may be, for example, larger than the width of the aperture of the through hole TH at the corresponding glue GL, but is not limited thereto.

In some embodiments, the manufacturing process of the electronic device may further include a step of modifying the surface exposed by the through holes TH. For example, the modification step may be performed on the surface of the nonmetal layer (e.g., dielectric layer, protection layer) exposed by the via hole TH. In some embodiments, the modification step may form, for example, colloidal palladium (not shown) on the exposed surface of the layer of the through holes TH, so that the conductive material can be attached to the surface of the material in the subsequent process, but is not limited thereto.

Referring to fig. 1G, the manufacturing process of the electronic device may further include disposing a conductive layer CL in the through hole TH, and the first conductive structure CS1 and the second conductive structure CS2 may be electrically connected through the conductive layer CL. The conductive layer CL may be provided on the layer surface exposed by the through hole TH, for example. The conductive layer CL can be electrically connected to the circuit exposed by the via TH (e.g., a portion of the circuit in the conductive layer CL1, a portion of the circuit in the conductive layer CL2, and a portion of the circuit in the conductive layer CL3) through the via TH. The conductive layer CL may include a metal, and the metal may include titanium (Ti), copper (Cu), aluminum (Al), molybdenum (Mo), other suitable materials, or a combination thereof, but is not limited thereto. In some embodiments, the forming method of the conductive layer CL may include, but is not limited to, electroless plating, deposition, or other suitable methods.

In some embodiments, the manufacturing flow of the electronic device may further include removing the protective layer PL2 and/or the protective layer PL 4. In some embodiments, protective layer PL2 and/or protective layer PL4 may be removed prior to forming conductive layer CL. In other embodiments, protective layer PL2 and/or protective layer PL4 may be removed after forming conductive layer CL. In other words, the protection layer PL2 and/or the protection layer PL4 may be removed, for example, in the final electronic device.

Referring to fig. 1H, the process flow of manufacturing the electronic device may further include forming a conductive material CC in the through holes TH. The conductive material CC may for example be surrounded by a conductive layer CL. In some embodiments, conductive material CC may be electrically connected to each other, for example, in contact with conductive layer CL. In some embodiments, the material of the conductive material CC may include a conductive polymer material, a metal material, a transparent conductive material, or a combination thereof, for example, the conductive material CC may include copper paste, silver paste, nano-copper, other conductive material, or a combination thereof.

Referring to fig. 1H, in some embodiments, the manufacturing process of the electronic device may further include disposing a plurality of pads PD1, a plurality of pads PD1 may be disposed on the second substrate SUB2, and the pads PD1 may be formed in the multi-opening a5 and/or the opening a5 of the protection layer PL3, for example, but not limited thereto. For example, the pads PD1 may be formed by, for example, Nickel Immersion Gold (ENIG), but not limited thereto, and the material of the pads PD1 may be adjusted according to the requirement.

Referring to fig. 1I, in some embodiments, the process flow of manufacturing the electronic device may further include bonding the electronic element EC to one of the first substrate SUB1 and the second substrate SUB 2. In some embodiments, the electronic device EC may include passive devices and active devices, such as, but not limited to, capacitors, resistors, inductors, diodes, transistors, IC chips, and the like. In some embodiments, the pads PD2 of the electronic component EC may be bonded to the pads PD1 on the second substrate SUB2 through the conductive elements CB, for example, but not limited thereto. In other embodiments (not shown), the pads PD1 may be disposed on the first substrate SUB1, and the pads PD2 of the electronic component EC may be bonded to the pads PD1 on the first substrate SUB1 through the conductive elements CB, for example, but not limited thereto.

After the above-described bonding step, the manufacturing of the electronic device 1 is preliminarily completed. The electronic device 1 may include a first substrate SUB1, a second substrate SUB2, a first conductive structure CS1, and/or a second conductive structure CS 2. The first substrate SUB1 has a first surface S1 and a second surface S2 opposite to the first surface S1. The second substrate SUB2 has a third surface S3 facing the second surface S2 and a fourth surface S4 opposite to the third surface S3. The first conductive structure CS1 is disposed on the first surface S1. The second conductive structure CS2 is disposed on the fourth surface S4. The second surface S2 is attached to the third surface S3, and the thickness of the first substrate SUB1 and the second substrate SUB2 is greater than or equal to 5 μm and less than or equal to 1000 μm. For example, the second surface S2 can be adhered to the third surface S3 by the glue GL, but not limited thereto.

In some embodiments, the electronic device 1 may further include a via TH, a conductive layer CL, and/or an electronic element EC. The through hole TH may penetrate through the first substrate SUB1 and the second substrate SUB2, for example. The conductive layer CL may be disposed in the through hole TH, and the first conductive structure CS1 and the second conductive structure CS2 may be electrically connected through the conductive layer CL. In some embodiments, the first conductive structure CS1 may include at least one conductive layer (e.g., the conductive layer CL1) and at least one dielectric layer (e.g., the dielectric layer DL1), and one of the at least one dielectric layer (e.g., the dielectric layer DL1) may be disposed directly on the first substrate SUB1, but is not limited thereto. In some embodiments, the second conductive structure CS2 may include at least one conductive layer (e.g., conductive layer CL2 and/or conductive layer CL3) and at least one dielectric layer (e.g., dielectric layer DL2 and/or dielectric layer DL3), and one of the at least one dielectric layer (e.g., dielectric layer DL2) may be directly disposed on the second substrate SUB2, but is not limited thereto. In other embodiments (not shown), the first conductive structure CS1 may be a conductive layer (e.g., conductive layer CL1), which may be directly disposed on the first substrate SUB 1. In other embodiments (not shown), the second conductive structure CS2 may be a conductive layer (e.g., conductive layer CL2), which may be directly disposed on the second substrate SUB 2.

In some embodiments, as shown in fig. 1I, the conductive layer CL1, a portion of the wiring (e.g., wiring CK1) in the conductive layer CL2, and a portion of the wiring (e.g., wiring CK2) in the conductive layer CL3 can be electrically connected, for example, through the conductive layer CL. For example, taking the electronic device 1 as an antenna device, the conductive layer CL1, a portion of the trace (e.g., trace CK1) in the conductive layer CL2, and a portion of the trace (e.g., trace CK2) in the conductive layer CL3 may be electrically connected to a first signal of the electronic component EC, such as a radio frequency signal, through the corresponding pad PD1 and/or the conductive element CB. On the other hand, as shown in fig. 1I, a portion of the lines (e.g., the line CK3) in the conductive layer CL2 and a portion of the lines (e.g., the line CK4) in the conductive layer CL3 can be electrically connected to a second signal, such as a ground signal, through the corresponding pad PD1 and/or the conductive element CB, but is not limited thereto. In some embodiments, the first signal and the second signal have a potential difference.

In some embodiments, a distance D may be provided between a conductive layer (e.g., conductive layer CL1) of first conductive structure CS1 closest to first substrate SUB1 and a conductive layer (e.g., conductive layer CL2) of second conductive structure CS2 closest to second substrate SUB 2. In some embodiments, when the electronic device is applied to an antenna, the distance D may be designed according to the frequency applied to the electronic device or other parameters (such as the impedance of the two conductive layers), wherein the frequency and the "distance D" may be approximately in inverse proportion, but are not limited thereto. In some embodiments, as shown in fig. 1I, the distance D between the two conductive layers can be separated by an insulating layer and/or a dielectric layer disposed between the two conductive layers. For example, as shown in fig. 1I, the distance D may be separated by a substrate (e.g., the first substrate SUB1 and the second substrate SUB2), a dielectric layer (e.g., the dielectric layer DL1, the dielectric layer DL2 and the dielectric layer DL3), a protective layer (e.g., the protective layer PL1 and the protective layer PL3), and/or a glue (e.g., the glue GL), and the value of the distance D may be determined by the sum of thicknesses of the layers in the direction Z. The distance D can be adjusted by the insulating layer and/or the dielectric layer disposed between the two conductive layers, and in some embodiments, the distance D can be, for example, greater than or equal to 10 μm and less than or equal to 2000 μm (10 μm ≦ distance D ≦ 2000 μm), but is not limited thereto. In some embodiments, the distance D can be, for example, greater than or equal to 100 μm and less than or equal to 1800 μm (100 μm ≦ distance D ≦ 1800 μm), but is not so limited. In some embodiments, distance D can be, for example, greater than or equal to 200 μm and less than or equal to 1500 μm (200 μm ≦ distance D ≦ 1500 μm), but is not so limited.

In some embodiments, the electronic device 1 may be a circuit board, and the first conductive structure CS1 and/or the second conductive structure CS2 may be a redistribution layer (RDL), but is not limited thereto.

In some embodiments, the warpage problem can be reduced by forming different conductive layers on the two substrates, respectively. In addition, compared with the method of forming different conductive layers on two opposite sides of one substrate by a double-sided process, the method of forming the conductive layer on one side of the different substrate can reduce the difficulty of the process.

Fig. 2 is a schematic partial cross-sectional view of an electronic device according to some embodiments of the present disclosure. Referring to fig. 2, the main differences between the electronic device 1' and the electronic device 1 of fig. 1I are described as follows. The electronic device 1' may not include the conductive layer CL of fig. 1I, and the conductive material CC may be electrically connected by contacting with the film layer (e.g., the conductive layer CL1) or the circuit (e.g., the circuit CK1 and the circuit CK2) exposed by the via TH. For example, after the via process is performed (as shown in fig. 1F), a conductive material CC may be formed in the via hole TH, for example. The material of the conductive material CC may be as described above.

In some embodiments, the first substrate SUB1 and the second substrate SUB2 have different areas when viewed from the top of the electronic device. For example, the area of the second substrate SUB2 may be larger than the area of the first substrate SUB1, but is not limited thereto. In some embodiments, the electronic element EC may be bonded to one of the first substrate SUB1 and the second substrate SUB2, and the electronic element EC may be bonded to the second substrate SUB2) with a larger area, but is not limited thereto. In other embodiments (not shown), the area of the first substrate SUB1 may be larger than the area of the second substrate SUB2, for example.

In other embodiments (not shown), the shapes of the first substrate SUB1 and the second substrate SUB2 may be the same or different when viewed from the top of the electronic device. In other embodiments (not shown), the first substrate SUB1 and the second substrate SUB2 have similar areas or shapes when viewed from the top of the electronic device, but the first substrate SUB1 and the second substrate SUB2 may be slightly shifted when combined, for example, so that a portion of the first substrate SUB1 does not overlap with the second substrate SUB2, but is not limited thereto.

It should be noted that although not shown, other substrates or polymers may be disposed between the first substrate SUB1 and the second substrate SUB2 as required. In addition, when another substrate or polymer is disposed between the first substrate SUB1 and the second substrate SUB2, another substrate (or polymer) can be selectively bonded to the first substrate SUB1 and/or the second substrate SUB2 by another adhesive material (not shown).

In summary, in the embodiments of the present disclosure, different conductive layers are formed on two substrates, and the two substrates are used to maintain the distance between the different conductive layers, which is helpful to improve the process cost, time or warpage of the substrate. In addition, the single-sided process can reduce the process difficulty. In some embodiments, by using the polymer substrate as the first substrate and the second substrate, the through hole process can be facilitated or the probability of the substrate breaking or cracking during the through hole process can be reduced. In some embodiments, the electronic device may include a through hole penetrating through the first substrate and the second substrate, and a conductive material may be formed in the through hole, and the heat dissipation or heat conduction effect may be further improved by appropriately selecting the conductive material.

The above embodiments are only used for illustrating the technical solutions of the present disclosure, and not for limiting the same; while the present disclosure has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be combined or modified, or some or all of the technical features may be equivalently replaced; such combination, modification or substitution does not make the essence of the corresponding technical solution depart from the scope of the technical solution of the embodiments of the present disclosure.

Although the embodiments of the present disclosure and their advantages have been described above, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure, and the features of the various embodiments may be arbitrarily mixed and substituted with one another to form new embodiments. Moreover, the scope of the present disclosure is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. Accordingly, the scope of the present disclosure includes the processes, machines, manufacture, compositions of matter, means, methods, and steps described above. In addition, each claim constitutes a separate embodiment, and the scope of the present disclosure also includes combinations of the respective claims and embodiments. The scope of the present disclosure is to be determined by the claims appended hereto.

Claims

1. A method of making an electronic device, comprising:

providing a first carrier plate;

arranging a first substrate on the first carrier plate;

arranging a first conductive structure on the first substrate;

removing the first carrier plate;

providing a second carrier plate;

arranging a second substrate on the second carrier plate;

arranging a second conductive structure on the second substrate;

removing the second carrier plate; and

and combining the first substrate and the second substrate.

2. The method of claim 1, wherein the first substrate is bonded to the second substrate by a glue.

3. The method of manufacturing an electronic device according to claim 1, further comprising:

and forming a through hole which penetrates through the first substrate and the second substrate.

4. The method of manufacturing an electronic device according to claim 3, further comprising:

disposing a conductive layer in the via, wherein the first conductive structure and the second conductive structure are electrically connected through the conductive layer.

5. The method of claim 1, wherein the first substrate and the second substrate have a thickness greater than or equal to 5 μm and less than or equal to 1000 μm.

6. The method of claim 1, wherein a material of at least one of the first substrate and the second substrate is a polymer.

7. The method of claim 1, wherein the first substrate and the second substrate are both made of a polymer.

8. The method of claim 1, wherein the first substrate and the second substrate have different areas.

9. The method of manufacturing an electronic device according to claim 1, wherein the first substrate and the second substrate have different thicknesses.

10. The method of manufacturing an electronic device according to claim 1, further comprising:

bonding an electronic component to one of the first substrate and the second substrate.