CN114649017A

CN114649017A - Write operation method of magnetic memory

Info

Publication number: CN114649017A
Application number: CN202011523893.XA
Authority: CN
Inventors: 吕玉鑫; 朱怡皓; 何伟伟; 李志怀; 戴瑾
Original assignee: Shanghai Information Technologies Co ltd
Current assignee: Shanghai Information Technologies Co ltd
Priority date: 2020-12-21
Filing date: 2020-12-21
Publication date: 2022-06-21

Abstract

The application provides a write operation method of a magnetic memory, the magnetic memory comprises a memory cell array consisting of a plurality of memory cells, the memory cell array is connected with an external circuit through a word line, a source line and a bit line, and each memory cell consists of a magnetic tunnel junction and an NMOS tube. For the selected storage unit, the write operation method comprises the following steps: when the writing operation needs to be electrified from the source line to the bit line direction, the source line voltage is set to be the working voltage of the circuit through the writing driving circuit, and the bit line voltage is set to be negative voltage; when the writing operation needs to be powered on from the bit line to the source line direction, the source line voltage is set to be zero potential through the writing driving circuit, and the bit line voltage is set to be equal to or smaller than the working voltage. The application reduces the workload of the MOS tube, and safely avoids the short circuit problem caused by overlarge forward bias of the PN junction while increasing the write drive current.

Description

Write operation method of magnetic memory

Technical Field

The present invention relates to the field of memory technology, and more particularly, to a write operation method for a magnetic memory.

Background

The principle of magnetic memories (MRAM) is based on a structure called MTJ (magnetic tunnel junction). It is composed of two layers of ferromagnetic material sandwiching a very thin layer of non-ferromagnetic insulating material. When a P-state is to be written to a selected memory cell in the array (i.e., the magnetization of the memory layer of the MTJ is oriented parallel to the reference layer), the write circuit needs to provide a top-down current to the MTJ. When an AP state is to be written to a selected memory cell in the array (i.e., the magnetization direction of the memory layer of the MTJ is set to be anti-parallel to the reference layer), the write circuit needs to provide a bottom-up current to the MTJ. Saturation current pair V of MOS tube_GSIs very sensitive. At this time, V is divided by the resistance of the MTJ device in the write path_GSThe MOS tube can not provide enough drive current to complete the writing operation. At high process nodes on the nanometer scale (e.g., 28 nm), the voltage dividing effect of the parasitic resistance of the line connection on the write path is not negligible, which further reduces the driving capability of the access MOS transistor.

Some manufacturers will optimize the design, as shown in chinese patent publication No. CN 101859599a, to increase the gate voltage of the access transistor to offset V when writing the AP state_GSHowever, mos tubes usually work at 1.2-1.0V VDD, which affects their long life, plus the effect of the body effect (body effect), which raises V_G，V_SBAnd the saturation current of the NMOS tube is lost correspondingly.

Also, as proposed in US patent No. 8634232B 2, a design scheme is proposed to share the source line between adjacent memory cells in different rows of the same column. In this scheme, when writing the AP state to the selected memory cell (i.e., the write operation requires power to be applied from the source line to the bit line), the write driver circuit biases the bit line BL to a negative VDD, and the shared source line SL potential is grounded. At this time, the body potential of the access MOS transistor is biased at a larger negative bias (e.g., -VDD) by default so as to avoid the occurrence of short circuit due to the excessively large forward bias of the PN junction of the access MOS transistor near the end of the BL bit line, which is different from the cells in the same column as the memory cell to be written. However, such voltage bias may cause an excessive voltage drop from the gate of the MOS transistor to the substrate, which may cause stress to the MOS transistor, thereby affecting the service life of the chip. In addition, the body effect can further weaken the saturation current of the MOS tube.

Further, as disclosed in chinese patent publication No. CN 109817253 a, an MRAM chip array layout capable of controlling body potential is proposed. It makes it possible to individually change the body potential of this region by providing a deep N-well in the MRAM chip array portion. When writing operation is carried out, the body potential is properly increased by delta, so that the voltage drop from the grid electrode of the access MOS tube to the substrate is reduced, the body effect is reduced, and the write drive saturation current of the access MOS tube is increased. However, this improvement has limited effect on increasing the drive current, especially at advanced semiconductor process nodes (28 nm or less) where the operating voltage is lower (below 0.9V), and this approach does not meet the material requirements.

Disclosure of Invention

In order to solve the above technical problem, an object of the present application is to provide a write operation method of a magnetic memory, which is a design scheme for improving write driving capability by applying a negative bias in a write path bit line direction, and is superior to the conventional scheme.

The purpose of the application and the technical problem to be solved are realized by adopting the following technical scheme.

According to the write operation method of the magnetic memory provided by the application, the magnetic memory comprises a memory cell array consisting of a plurality of memory cells, the memory cell array is connected with the external circuit through a word line, a bit line and a source line, and each memory cell consists of a magnetic tunnel junction and an NMOS tube. For the selected storage unit, the write operation method comprises the following steps: when the writing operation needs to be electrified from the source line to the bit line direction, setting the source line voltage as the working voltage of the circuit through a writing driving circuit; when the writing operation needs to be powered on from the bit line to the source line direction, the source line voltage is set to be zero potential through the writing driving circuit, and the bit line voltage is set to be equal to or smaller than the working voltage.

The technical problem solved by the application can be further realized by adopting the following technical measures.

Optionally, the body potential of the NMOS transistor of the selected memory cell is grounded.

Optionally, a forward bias voltage from the substrate of the memory cell to the bit line needs to be smaller than a forward turn-on voltage of a PN junction formed between the substrate of the NMOS transistor and the active region.

Optionally, the negative voltage is between-0.3V and-0.6V.

Optionally, the memory cell array includes a row address decoder and a column address decoder, which respectively convert the received external address information into selection information of a word line, a bit line and a source line, and obtain the selected memory cell.

Optionally, the memory cell array includes a write driver and a sense amplifier, and the memory cell array performs read or write operations on the selected memory cell under the control of an external read/write enable signal.

Optionally, the write driver and sense amplifier includes a write driver circuit and a sense amplifier; the write driving and sense amplifier obtains a high-level read operation signal, and when the low-level write operation signal is received, the read operation is carried out on the selected memory cell, the write driving circuit is disconnected with a bit line and a source line of the selected memory cell, and the sense amplifier is connected with the bit line and the source line of the selected memory cell; the write driving and sense amplifier obtains a low-level read operation signal, and performs write operation on the selected memory cell when the high-level write operation signal is received, the write driving circuit is connected with the bit line and the source line of the selected memory cell, and the sense amplifier is disconnected with the bit line and the source line of the selected memory cell.

Optionally, when the write operation to the selected memory cell requires power supply from the bit line to the source line, the write driver circuit sets the voltage of the source line to a zero potential and sets the voltage of the bit line to an operating voltage. When a write operation to a selected memory cell requires energization from the source line in the direction of the bit line, the write driver circuit sets the voltage of the source line to an operating voltage and sets the voltage of the bit line to a negative voltage.

Optionally, the method further includes that a data bus provides writing or reading of m +1 bit data, where m is a natural number greater than 1; the column decoder comprises a plurality of multi-path selection switches, wherein a proper pair of multi-path selection switches are switched on according to external address information and are respectively connected with bit lines and source lines of the same memory unit, and the same memory unit is the selected memory unit.

According to the design scheme, the write driving capability is improved by applying the negative bias voltage in the bit line direction of the write path, the requirement on the gate voltage VG on the access MOS tube is obviously reduced while the driving current is improved, and the working load stress of the NMOS is reduced. The service life of the NMOS tube, namely the MRAM chip is prolonged. Secondly, when the writing operation needs to be conducted from the source line to the bit line direction, the voltage of the source line SL is set to VDD, the voltage of the bit line BL is biased in a smaller negative bias range from-0.3 to-0.6V (the body potential of the access MOS tube is always grounded), the working load stress of the MOS tube is reduced, the writing driving current of the MOS tube is increased, and meanwhile the problem of short circuit caused by overlarge forward bias of a PN junction is safely avoided. Thirdly, the write driving capability is improved, and meanwhile, a margin is provided for the size design selection of NMOS and PMOS devices on a write path. That is, a smaller area NMOS transistor may be used in the MRAM array, or a smaller size MUX select switch may be selected in the column decoder on the write path. The manufacturing cost of the chip is reduced. Compared with a write operation method for improving the body potential, the read-write operation method for the MRAM chip array layout can bring larger drive current increase, especially under the condition of a high-level process node and slightly higher material turnover voltage.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a memory structure according to an embodiment of the present application;

FIG. 2 is a diagram of an exemplary memory structure;

FIG. 3 is a functional diagram of a write driver and a sense amplifier according to an embodiment of the present application.

Detailed Description

Referring to the drawings, wherein like reference numbers refer to like elements throughout. The following description is based on illustrated embodiments of the application and should not be taken as limiting the application with respect to other embodiments that are not detailed herein.

The following description of the various embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. In the present application, directional terms such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", and the like are merely referring to the directions of the attached drawings. Accordingly, the directional terminology is used for purposes of illustration and understanding, and is in no way limiting.

The terms "first," "second," "third," and the like in the description and in the claims of the present application and in the above-described drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the objects so described are interchangeable under appropriate circumstances. Furthermore, the terms "comprising" and "having," as well as variations thereof, such as, for example, are intended to cover non-exclusive inclusions.

The terminology used in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the concepts of the present application. Unless the context clearly dictates otherwise, expressions used in the singular form encompass expressions in the plural form. In the present specification, it will be understood that terms such as "including," "having," and "containing" are intended to specify the presence of the features, integers, steps, acts, or combinations thereof disclosed in the specification, and are not intended to preclude the presence or addition of one or more other features, integers, steps, acts, or combinations thereof. Like reference symbols in the various drawings indicate like elements.

The drawings and description are to be regarded as illustrative in nature, and not as restrictive. In the drawings, elements having similar structures are denoted by the same reference numerals. In addition, the size and thickness of each component shown in the drawings are arbitrarily illustrated for understanding and ease of description, but the present application is not limited thereto.

In the drawings, the range of configurations of devices, systems, components, circuits is exaggerated for clarity, understanding, and ease of description. It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.

In addition, in the description, unless explicitly described to the contrary, the word "comprise" will be understood to mean that the recited components are included, but not to exclude any other components. Further, in the specification, "on.

To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description is given of a write operation method of a magnetic memory according to the present invention with reference to the accompanying drawings and the embodiments, structures, features and effects thereof are described in detail.

Fig. 1 is a schematic diagram of a memory structure according to an embodiment of the present application. The embodiment of the application discloses a write operation method of a magnetic memory, wherein the magnetic memory comprises a memory cell array consisting of a plurality of memory cells, the memory cell array is connected with an external circuit through a word line, a source line and a bit line, and each memory cell consists of a magnetic tunnel junction and an NMOS tube. For the selected storage unit, the write operation method comprises the following steps:

as shown in FIG. 1, when a Write operation requires power to be applied from the source line to the bit line (P to AP, i.e., writing AP state), the source line voltage V is applied by the Write Driver_SL1Set to the operating voltage V of the circuit_W1Setting the bit line voltage to a negative voltage-ΔWherein the negative voltage-ΔLower than the voltage VSS. Such a bias arrangement brings two advantageous aspects to increasing write drive capability: 1) firstly due to V_BL1For negative bias, access to V on MOS transistor_GSThe voltage drop of the capacitor is greatly increased; 2) in addition, under such voltage bias, V on the access MOS transistor will also be caused to be accessed_SBWith a large reduction (body potential of the tube is grounded, in which case V_SBNegatively biased), the body effect further increases the saturation current of the tube. The enhancement of the write driving current reduces the requirement on the grid voltage of the access tube. When selecting reasonable negative bias voltage according to parasitic effect of actual write circuit-ΔCan make the pair V_GThe voltage requirement is reduced to VDD.

When a write operation requires power-on from the bit line to the source line (AP to P, i.e., writing a P-state), as shown on the right side of FIG. 1, the source line voltage V is applied by the write driver circuit_SL2Set to zero potential, set the bit line voltage V_BL2Is set as V_W2At this time, since the driving current of the write driving circuit is larger than that of the write AP state, V_W2May be equal to or less than VDD.

Optionally, when the write operation on the selected memory cell needs to be performed in a direction from the source line to the bit line, for the memory cells in the same column but different rows, a forward bias voltage exists at one end of the NMOS transistor close to the bit line BL, and the forward bias voltage is changed by the potential of the negative voltage.

Optionally, a forward bias voltage from the substrate of the memory cell to the bit line needs to be smaller than a forward turn-on voltage of a PN junction formed between the substrate of the NMOS transistor and the active region. Because a short circuit occurs when the forward conduction voltage of the PN junction between the NMOS transistor substrate and the active region is applied to the positive bias voltage, the leakage current increases even when the voltage value is close. The value of the negative bias-delta applied to the bit line cannot be too high, preferably around-0.3 to-0.6.

FIG. 2 is a block diagram of a magnetic memory chip according to an embodiment of the present disclosure. A magnetic memory MRAM chip is made up of one or more arrays (101) of MRAM memory cells (100). Each array is provided with a number of external circuits. A row address decoder (102) and a column address decoder (103) convert received external address information into selection information of a Word Line (WLi), a bit line (BLj) and a source line (SLj), respectively. The write driving and sense amplifier (104) respectively performs read or write operations on the selected memory cell under the control of an external read/write enable signal.

Optionally, the column decoder is composed of a plurality of multiplexing switches, which in this embodiment are implemented by CMOS transmission gates.

Optionally, the data bus of the MRAM chip provides writing or reading of m +1 bit data. For each data bit, the column decoder will select one of n multi-way selection switches connected to the bit lines BL in the array to be turned on according to an externally input address. Likewise in the source line SL direction, the column decoder will select one of the n multiplexing switches in communication with the source lines SL in the array, depending on the externally input address. Thereby selecting a memory cell in the memory array. The m +1 bit data bit corresponds to m +1 selected memory units designated by the external address. These memory cells exist on the same word line, on different bit/source lines. In addition, the chip is provided with m +1 groups of write driving and read amplifier modules with the same function, and the write driving and read amplifier modules are used for performing read-write operation on the selected m +1 storage units.

FIG. 3 is a functional diagram of a write driver and a sense amplifier according to an embodiment of the present application. In an embodiment of the present application, the write driver and sense amplifier includes a write driver circuit and a sense amplifier; when the write driving and sense amplifier obtains a read operation signal RD _ EN with a logic high level and a write operation signal WR _ EN with a logic low level, the read operation is carried out on the selected memory cell, the switch m1 and the switch m2 between the write driving circuit and the bit line and the source line of the selected memory cell are disconnected, and the switch m3 and the switch m4 between the sense amplifier and the bit line and the source line of the selected memory cell are connected; and when the write driving and sense amplifier obtains a read operation signal RD _ EN with a logic low level and a write operation signal WR _ EN with a logic high level, the write driving circuit performs write operation on the selected memory cell, the switch m1 and the switch m2 between the write driving circuit and the bit line and the source line of the selected memory cell are connected, and the switch m3 and the switch m4 between the sense amplifier and the bit line and the source line of the selected memory cell are disconnected.

Alternatively, when the writing operation to the selected memory cell requires power supply from the bit line to the source line (P-state, defined as write data "1" in this embodiment), the write driver circuit sets the voltage of the source line SLi to VSS zero potential and sets the voltage of the bit line BLi to the operating voltage VDD. When a write operation to a selected memory cell requires energization from the source line in the bit line direction (AP state, defined as write data "0" in the present embodiment), the write driver circuit sets the voltage of the source line SLi to the operating voltage VDD and sets the voltage of the bit line BLi to the negative voltage- Δ.

According to the design scheme, the write driving capacity is improved by applying the negative bias voltage in the bit line direction of the write path, the requirement on the gate voltage VG on the access MOS tube is obviously reduced while the driving current is improved, and the working load stress of the NMOS is reduced. The service life of the NMOS tube, namely the MRAM chip is prolonged. Secondly, when the write operation needs to be electrified from the source line to the bit line direction, the voltage of the source line SL is set to VDD, the voltage of the bit line BL is biased in a smaller negative bias range of-0.3 to-0.6V (the body potential of the access MOS tube is always grounded), the workload stress of the MOS tube is reduced, the write driving current of the MOS tube is increased, and meanwhile the problem of short circuit caused by the fact that the PN junction is excessively forward biased is safely avoided. Thirdly, the write driving capability is improved, and meanwhile, a margin is provided for the size design selection of NMOS and PMOS devices on a write path. That is, a smaller area NMOS transistor may be used in the MRAM array, or a smaller size MUX multiplexing switch may be selected in the column decoder on the write path. The manufacturing cost of the chip is reduced. Compared with a write operation method for improving the body potential, the read-write operation method for the MRAM chip array layout can bring larger drive current increase, especially under the condition of a high-level process node and slightly higher material turnover voltage.

The terms "in one embodiment of the present application" and "in various embodiments" are used repeatedly. This phrase generally does not refer to the same embodiment; it may also refer to the same embodiment. The terms "comprising," "having," and "including" are synonymous, unless the context dictates otherwise.

Although the present application has been described with reference to specific embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application, and all changes, substitutions and alterations that fall within the spirit and scope of the application are to be understood as being covered by the following claims.

Claims

1. A write operation method of a magnetic memory, the magnetic memory comprises a memory cell array composed of a plurality of memory cells, the memory cell array is connected with an external circuit through a word line, a source line and a bit line, each memory cell is composed of a magnetic tunnel junction and an NMOS tube, and the write operation method comprises the following steps for the selected memory cell:

when the writing operation needs to be electrified from the source line to the bit line direction, the source line voltage is set to be the working voltage of the circuit through the writing driving circuit, and the bit line voltage is set to be negative voltage;

when the writing operation needs to be powered on from the bit line to the source line direction, the source line voltage is set to be zero potential through the writing driving circuit, and the bit line voltage is set to be equal to or smaller than the working voltage.

2. The method of claim 1 wherein the body potential of the NMOS transistor of the selected memory cell is grounded.

3. The method of claim 1 wherein a forward bias voltage from the substrate to the bit line of the memory cell is less than a forward turn-on voltage of a PN junction formed between the substrate and the active region of the NMOS transistor.

4. The method of claim 1 wherein said negative voltage is between-0.3V and-0.6V.

5. The method of claim 1 wherein the memory cell array includes a row address decoder and a column address decoder that translate received external address information into selections of word lines, bit lines and source lines, respectively, to obtain the selected memory cells.

6. A method of writing to a magnetic memory as in claim 5 wherein the array of memory cells includes write driver and sense amplifiers, the read or write operations being performed on the selected memory cells under the control of external read and write enable signals.

7. The method of claim 6 wherein said write driver and sense amplifier comprises a write driver circuit and a sense amplifier; the write driving and sense amplifier obtains a high-level read operation signal, and when the low-level write operation signal is received, the read operation is carried out on the selected memory cell, the write driving circuit is disconnected with a bit line and a source line of the selected memory cell, and the sense amplifier is connected with the bit line and the source line of the selected memory cell; the write driving and sense amplifier obtains a low-level read operation signal, and performs write operation on the selected memory cell when the high-level write operation signal is received, the write driving circuit is connected with the bit line and the source line of the selected memory cell, and the sense amplifier is disconnected with the bit line and the source line of the selected memory cell.

8. The method of claim 7, wherein the write driver circuit sets the source line voltage to zero and the bit line voltage to the operating voltage when a write operation to the selected memory cell requires power to be applied from the bit line to the source line. When a write operation to a selected memory cell requires energization from the source line in the direction of the bit line, the write driver circuit sets the voltage of the source line to an operating voltage and sets the voltage of the bit line to a negative voltage.

9. The method of claim 5 further comprising the step of providing a data bus for writing or reading m +1 bits of data, m being a natural number greater than 1; the column decoder comprises a plurality of multi-path selection switches, wherein a proper pair of multi-path selection switches are switched on according to external address information and are respectively connected with bit lines and source lines of the same memory unit, and the same memory unit is the selected memory unit.