CN114639682A - Three-dimensional memory, preparation method and storage system - Google Patents

Abstract

The application provides a three-dimensional memory, a preparation method and a storage system. The three-dimensional memory includes: a stacked structure; a plurality of channel structures including a channel layer and penetrating the stacked structure; and the top selection gate structure is formed between the adjacent channel structures and penetrates through part of the stacked structures, wherein the channel layer of at least one channel structure close to one end of the top selection gate structure is provided with a dopant along the thickness direction of the stacked structures. According to the three-dimensional memory, the preparation method and the storage system, the area occupied by the top selection gate is saved, the probability of mistakenly opening the top selection transistor in the three-dimensional memory is increased, and the reliability of the three-dimensional memory is improved.

Description

Three-dimensional memory, preparation method and storage system

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a three-dimensional memory, a manufacturing method thereof, and a memory system.

Background

In a three-dimensional memory process, a top select gate structure is usually employed to ensure that each memory cell string can operate independently. As in fig. 1, in a conventional 9-hole structure, a top select gate structure 120 overlaps a row of channel structures 110. The row channel structure 110 does not have a memory function, which results in a certain area waste.

Disclosure of Invention

The present application provides a three-dimensional memory, a method of manufacturing, and a memory system that at least partially solve the above-mentioned problems in the prior art.

One aspect of the present application provides a three-dimensional memory, including: a stacked structure; a plurality of channel structures including a channel layer and penetrating the stacked structure; and a top select gate structure formed between adjacent channel structures and penetrating a portion of the stacked structure, wherein, in a thickness direction of the stacked structure, an end of the channel layer of at least one channel structure near the top select gate structure has a dopant.

In some exemplary embodiments of the present application, the dopant is a P-type dopant.

In some exemplary embodiments of the present application, a length of the channel layer having the dopant is less than a length of the top select gate structure in a thickness direction of the stack structure.

In some exemplary embodiments of the present application, the three-dimensional memory further comprises: a pair of gate slit structures penetrating the stacked structure; the plurality of channel structures are positioned between the pair of gate gap structures and are arranged in N rows, and each row of channel structures and the channel structures of the adjacent rows are arranged in a staggered mode; the top selection gate structure is positioned between the N/2 th row channel structure and the N/2+1 th row channel structure, and N is an even number.

In some exemplary embodiments of the present application, the top select gate structure is in contact with the at least one channel structure.

In some exemplary embodiments of the present application, a channel structure includes: the functional layer and the channel layer are sequentially arranged from outside to inside along the radial direction of the channel structure, and the top selection gate structure is in contact with the functional layer.

In some exemplary embodiments of the present application, a channel structure includes: the functional layer and the channel layer are sequentially arranged from outside to inside along the radial direction of the channel structure, and the top selection gate structure is in contact with the functional layer and the channel layer.

In some exemplary embodiments of the present application, the functional layer includes: and the blocking layer, the charge trapping layer and the tunneling layer are sequentially arranged from outside to inside along the radial direction of the channel structure.

Another aspect of the present application provides a storage system, including: the three-dimensional memory as mentioned in the above embodiments; and the controller is electrically connected with the three-dimensional memory and is used for controlling the three-dimensional memory.

Another aspect of the present application provides a method for manufacturing a three-dimensional memory, including: forming a stacked structure on a substrate; forming a plurality of channel structures penetrating the stacked structure; forming a top select gate structure between adjacent channel structures through a portion of the stack structure; and ion doping one end of at least one channel structure in the plurality of channel structures, which is far away from the substrate.

In some exemplary embodiments of the present application, ion doping the at least one channel structure comprises: and carrying out P-type ion doping on one end of the at least one channel structure far away from the substrate.

In some exemplary embodiments of the present application, a longitudinal depth of the ion doping is less than a length of the top selection gate structure in a thickness direction of the stack structure.

In some exemplary embodiments of the present application, forming the top select gate structure includes: forming a top select gate cut through a portion of the stacked structure between adjacent channel structures; and filling the top selection gate cut with a dielectric filling layer.

In some exemplary embodiments of the present application, ion doping an end of the at least one channel structure remote from the substrate comprises: before forming the top selection gate cut-out or after filling the top selection gate cut-out with a dielectric filling layer, carrying out ion doping on one end of at least one channel structure far away from the substrate, wherein the doping direction of the ion doping is vertical to the channel structure.

In some exemplary embodiments of the present application, ion doping an end of the at least one channel structure remote from the substrate comprises: and after the top selection gate cut is formed, carrying out ion doping on one end of the at least one channel structure far away from the substrate through the top selection gate cut, wherein the doping direction of the ion doping forms an included angle with the direction vertical to the channel structure.

In some exemplary embodiments of the present application, the top select gate structure is in contact with the at least one channel structure.

In some exemplary embodiments of the present application, the forming of the channel structure includes: forming a trench hole through the stacked structure; and sequentially forming a functional layer and a channel layer on the inner wall of the channel hole, wherein the step of forming the top selection gate structure comprises the following steps: forming a top select gate cut through a portion of the stacked structure between adjacent channel structures, the top select gate cut extending to at least one functional layer of the channel structure; and filling the top selection gate cut with a dielectric filling layer.

In some exemplary embodiments of the present application, the forming of the channel structure includes: forming a trench hole penetrating through the stacked structure; and sequentially forming a functional layer and a channel layer on the inner wall of the channel hole, wherein the step of forming the top selection gate structure comprises the following steps: forming a top select gate cut through a portion of the stacked structure between adjacent channel structures, the top select gate cut extending to the functional layer and the channel layer of at least one channel structure; and filling the top selection gate cut with a dielectric filling layer.

In some exemplary embodiments of the present application, the step of forming the functional layer includes: and sequentially forming a blocking layer, a charge trapping layer and a tunneling layer on the inner wall of the channel hole.

According to the three-dimensional memory, the preparation method and the storage system provided by the embodiment of the application, the top selection gate structure is arranged between the adjacent channel structures instead of occupying one row of channel structures, so that the area occupied by the top selection gate structure is saved. In addition, the channel layer at one end of the channel structure close to the top selection gate structure is doped, so that the threshold voltage of the top selection transistor close to the top selection gate structure is improved, the influence of potential coupling of a lower grid layer on the top selection transistor is smaller, the probability of false opening of the top selection transistor is reduced, and the reliability of the three-dimensional memory is improved.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, which proceeds with reference to the accompanying drawings. Wherein:

FIG. 1 is a schematic diagram of a three-dimensional memory according to the related art;

FIGS. 2, 3, and 4 are partial top schematic views of a three-dimensional memory according to one embodiment of the present application;

FIG. 5 is an enlarged partial schematic view of FIG. 3 at area B;

FIGS. 6a and 6b are schematic structural views of a channel structure in contact with a top select gate structure of a three-dimensional memory according to an embodiment of the present application;

FIG. 7 is a schematic cross-sectional view of the three-dimensional memory taken along line AA' in FIG. 3;

FIG. 8 is a schematic diagram of a partial top view of a three-dimensional memory according to another embodiment of the present application;

FIG. 9 is a schematic flow chart of a method of fabricating a three-dimensional memory according to one embodiment of the present application;

FIG. 10 is a schematic view illustrating a doping direction of ion doping in the method of fabricating the three-dimensional memory shown in FIG. 9;

FIG. 11 is a schematic flow chart diagram of a method for fabricating a three-dimensional memory according to another embodiment of the present application;

FIG. 12 is a schematic flow chart diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application;

fig. 13 is a schematic view of a doping direction of ion doping according to a manufacturing method of the three-dimensional memory shown in fig. 12;

FIG. 14 is a schematic block diagram of a storage system according to an embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

It should be noted that in this specification the expressions first, second, third etc. are only used to distinguish one feature from another, and do not indicate any limitation of features, in particular any order of precedence. Thus, a first concentration discussed in this application may also be referred to as a second concentration, and vice versa, without departing from the teachings of this application.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to examples or illustrations.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It should be noted that, in the present application, the embodiments and features of the embodiments may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Further, in this application, when "connected" or "coupled" is used, it may mean either direct contact or indirect contact between the respective components, unless there is an explicit other limitation or can be inferred from the context.

Fig. 2, 3 and 4 are partial top view schematic diagrams of a three-dimensional memory according to an embodiment of the present application, fig. 5 is a partially enlarged schematic diagram at a region B in fig. 3, fig. 6a and 6B are structural schematic diagrams of a channel structure contacting a top select gate structure of the three-dimensional memory according to an embodiment of the present application, and fig. 7 is a schematic cross-sectional view of the three-dimensional memory taken along a line AA' in fig. 3.

Referring to fig. 2, 3 and 4, the three-dimensional memory may include, for example: a stack structure 210, a plurality of channel structures (e.g., 220), and a top select gate structure 230. Each channel structure 220 includes a channel layer 221 and extends through the stack structure 210. A top select gate structure 230 is formed between adjacent channel structures 220 and through a portion of the stacked structure 210. Since the top select gate structures 230 are disposed between adjacent channel structures 220, rather than occupying a row of channel structures 220, the area occupied by the top select gate structures 230 is saved.

In some embodiments of the present application, as shown in fig. 2, 3 and 4, an end of the channel layer 221 of the at least one channel structure 220 near the top select gate structure 230 has a dopant along a thickness direction of the stack structure 210.

According to one embodiment of the present application, a channel layer of a channel structure near one end of a top selection gate structure has dopants (i.e., is doped with ions), so that the threshold voltage of a top selection transistor adjacent to the top selection gate structure is increased, the influence of potential coupling of a lower gate layer on the top selection transistor is reduced, the probability of false opening of the top selection transistor is reduced, and the reliability of a three-dimensional memory is improved.

In some embodiments of the present application, referring to fig. 2-4, the three-dimensional memory may further include, for example, a pair of gate-gap structures 240. The gate slit structure 240 may penetrate through the stacked structure 210, for example, and an angle between an extending direction of the gate slit structure 240 and an extending direction of the top select gate structure 230 may be approximately-10 ° to 10 °. In a three-dimensional memory, the gate slit structure 240 may be used, for example, to divide the three-dimensional memory into a plurality of memory blocks 251, and the top select gate structure 230 may be used, for example, to divide the memory blocks 251 of the three-dimensional memory into smaller memory units, such as the memory regions 252. The top select gate structure 230 may extend in a plane parallel to the substrate 200 and form a stripe or wave shaped cross section.

In some embodiments of the present application, the plurality of channel structures 220 are located between the pair of gate slit structures 240, and the plurality of channel structures 220 are arranged in N rows, where each row of channel structures is staggered with the adjacent rows of channel structures; the top select gate structure 230 is located between the N/2 th row channel structure and the N/2+1 th row channel structure, where N is an even number. Because the top selection gate structure is arranged between the adjacent channel structures instead of occupying a row of channel structures, the area occupied by the top selection gate structure is saved.

In the embodiments shown in fig. 2 to 4, the channel structures (e.g., 220) are arranged in a plurality of rows between the adjacent gate slit structures 240, fig. 2 to 4 show the structure of the three-dimensional memory in which a plurality of channel structures (e.g., 220) are arranged in 8 rows, and the top select gate structure 230 is disposed between the fourth and fifth row channel structures 220, which can save the area of the three-dimensional memory. However, it will be appreciated by those skilled in the art that the above embodiments are merely exemplary and that the number of rows of channel structures, the number of top select gate structures, and the location may be varied as desired without departing from the inventive concepts of the present application.

In some embodiments of the present application, as shown in fig. 2, the top select gate structure 230 and the channel structure 220 may not be in contact.

In other embodiments of the present application, a top select gate structure is in contact with at least one channel structure, as shown in fig. 3 and 4. In other words, referring to fig. 5, during the formation of the top select gate structure 230 between the adjacent channel structures 220, the top select gate structure 230 may extend to the channel structures 220, i.e., there may be a partial overlap between the top select gate structure 230 and the two rows of channel structures 220 adjacent thereto. The gate-all-around structure of the channel structure 220 in the overlap region is broken down into an omega structure, as shown in fig. 6a and 6 b. In the embodiment of the application, the channel layer 221 at one end of the channel structure 220, which is in contact with the top select gate structure 230 and close to the top select gate structure 230, is doped, so that the ion doping concentration at one end of the channel structure 220, which is far away from the substrate 200, is increased, the threshold voltage of the top select transistor adjacent to the top select gate structure is increased, the influence of potential coupling of the lower gate layer 212 on the top select transistor is reduced, the probability of false opening of the top select transistor is reduced, the probability that the channel structure 220 cannot be completely turned off is also reduced, the static turn-off current caused by an omega structure is inhibited, the static power consumption of the three-dimensional memory is reduced, and the reliability of the three-dimensional memory is improved.

Referring to fig. 7, in some embodiments of the present application, the three-dimensional memory may further include a substrate 200, for example. The substrate 200 may be made of any suitable semiconductor material. Examples of the compound include a III-V compound such as single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide. Alternatively, the substrate 200 may be fabricated from a single crystal silicon material.

Alternatively, the substrate 200 may be, for example, a composite substrate for supporting device structures thereon. A plurality of layers made of different materials may be sequentially disposed through a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof to form the substrate 200. Portions of the substrate 200 may also form well regions doped with N-type or P-type dopants formed via an ion implantation or diffusion process. The dopant may include any one or combination of phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments of the present application, the well regions may be prepared by selecting the same dopant, or alternatively, by selecting different dopants. The doping concentration of the well regions may be the same or different, and is not limited in this application.

Alternatively, the gate slit structure 240 may extend through the stacked structure 210 and into the substrate 200. It should be understood that the gate slit structure 240 may also be selectively extended into different layer structures included in the substrate 200 according to different arrangements of the three-dimensional architecture of the three-dimensional memory, or the gate slit structure 240 may also extend only through the stacked structure 210 without departing from the teachings of the present application.

Referring again to fig. 7, in some embodiments of the present application, the stacked structure 210 may, for example, include a plurality of stacked layers 213 formed by alternately stacking an insulating layer 211 and a gate layer 212, wherein the insulating layer 211 includes, but is not limited to, silicon oxide (SiO) layer_X). The gate layer 212 includes a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide, etc. The number of layers of the stacked structure 210 is not limited to the number of layers shown in the drawing, and may be additionally provided as needed, for example, the number of layers of the stacked structure 210 may be, for example, 32 layers, 64 layers, 128 layers, or the like.

Referring to fig. 2-5 and 7, in some embodiments of the present application, the channel structure 220 may include, for example, a functional layer 222 and a channel layer 221 sequentially disposed from the outside to the inside in a radial direction of the channel structure 220.

The structure of the functional layer 222 of the channel structure 220 is explained below as an example.

Referring to fig. 5, the functional layer 222 may include, for example, a blocking layer 2221 formed on an inner wall of a channel hole (not shown) to block outflow of charges, a charge trapping layer 2222 on a surface of the blocking layer 2221 to store charges during operation of the three-dimensional memory, and a tunneling layer 2223 on a surface of the charge trapping layer 2222. Among other things, barrier layer 2221 may, for example, comprise one or more layers, which may comprise one or more materials. The material used to form barrier layer 2221 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide, another wide band gap material, and the like. The charge trapping layer 2222 can, for example, comprise one or more layers, which can comprise one or more materials. The material used to form the charge trapping layer 2222 may include, for example, polysilicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide band gap material, and the like. Tunneling layer 2223 may, for example, comprise one or more layers, which may comprise one or more materials. The material used to form tunneling layer 2223 may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, and the like.

Alternatively, the functional layer 222 may comprise, for example, an oxide-nitride-oxide (ONO) structure. In other words, the blocking layer 2221 may comprise, for example, a silicon oxide layer, the charge trapping layer 2222 may comprise, for example, a silicon nitride layer, and the tunneling layer 2223 may comprise, for example, another silicon oxide layer. However, in some other embodiments, the functional layer 222 may have a structure other than the ONO configuration.

The channel layer 221 of the channel structure 220 is exemplified below.

In one embodiment of the present application, the channel layer 221 can be used to transport desired charges (electrons or holes). According to an exemplary embodiment of the present application, the channel layer 221 may be formed on the surface of the functional layer 222 through a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof.

In one embodiment of the present application, the channel layer 221 may include silicon, such as amorphous silicon, polycrystalline silicon, or single crystal silicon.

Referring again to fig. 2-4, as an option, the trench structure 220 may further include a trench fill layer 223, for example. For example, the channel hole, in which the channel layer 221 and the functional layer 222 have been formed, may be filled by a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof to form the channel filling layer 223. The trench fill layer 223 may include a dielectric layer of oxide, such as silicon oxide, etc. Illustratively, during the filling process, a plurality of insulating gaps may be formed in the trench filling layer 223 by controlling the trench filling process to relieve the structural stress.

Alternatively, after forming the channel fill layer 223, the top surface of the channel structure 220 (the surface away from the substrate 200) may, for example, include a plurality of rings of the channel layer 221, the functional layer 222 surrounding the channel fill layer 223 in sequence from the inner side to the outer side in the radial direction of the channel structure 220, wherein the top surface of the channel fill layer 223 may have an approximately circular shape. A portion of the top of the channel structure 220 is removed and a recess (not shown) is formed over the channel structure 220 by performing one or more etching processes, including, for example, a dry etching process or a combination of dry and wet etching processes. The semiconductor layer, e.g., an amorphous silicon layer or a polysilicon layer, is formed by using a selective epitaxial process or by using a thin film deposition process such as ALD, CVD, PVD, or any other suitable process. The semiconductor layer may be in electrical contact with the channel layer 221 as a channel plug 224 (see fig. 7).

Referring to fig. 7, in some embodiments of the present application, the dopant may be, for example, a P-type dopant. In other words, the doping concentration of the channel structure 220 in contact with the top select gate structure 230 may be, for example, a P-type atom doping concentration.

In one embodiment of the present application, the length of the channel layer 221 having the dopant is less than the length of the top select gate structure 230 in the thickness direction of the stack structure 210.

For example, referring to fig. 7, T stacked layers 213 of the plurality of stacked layers 213 of the stacked structure 210 far from the substrate 200 and the channel structure 220 in contact therewith form a top select gate transistor of the three-dimensional memory, and in order to reduce the case where the gate layer under the T stacked layers 214 is doped with ions to affect the storage function of the three-dimensional memory, the length of the channel layer doped in the embodiment of the present application may be less than or equal to the thickness of the T stacked layers 213. Typically, the length of top select gate structure 230 in the thickness direction of the stacked structure is greater than the thickness of the T stacked layers 213. Therefore, in the embodiments of the present application, the situation that the memory function of the three-dimensional memory is affected by the gate layer with the dopant ions distributed below the T stacked layers 214 can be reduced by limiting the longitudinal depth of doping the channel layer.

In one embodiment of the present application, referring to fig. 3, the top select gate structure 230 is in contact with the functional layer 222. In other words, there is an overlap region between the top select gate structure 230 and the functional layer 222.

In another embodiment of the present application, referring to fig. 4, a top select gate structure 230 is in contact with the functional layer 222 and the channel layer 221. In other words, there is an overlap region between the top select gate structure 230 and both the functional layer 222 and the channel layer 221. For example, the outer walls of the channel layer 221 are tangent to the sidewalls of the top select gate structure 230. Alternatively, to reduce the impact on the channel-gating capability, the top select gate structure 230 does not contact the inner wall of the channel layer 221.

It should be understood that in fig. 3 and 4, the top select gate structure 230 is exemplarily illustrated as being in contact with both adjacent rows of channel structures 220, and the top select gate structure 230 may also be in contact with, for example, one adjacent row of channel structures 220 and not in contact with the other adjacent row of channel structures 220 without departing from the teachings of the present application. For example, as shown in fig. 8, the top select gate structure 230 is in contact with the functional layer 222 and the channel layer 221 of an adjacent row of channel structures 220, and is not in contact with the other row of channel structures 220.

By the mode, the threshold voltage of the top selection transistor adjacent to the top selection gate structure can be increased, so that static off current is restrained, and static power consumption of the three-dimensional memory is reduced.

Fig. 9 is a flowchart of a method of manufacturing a three-dimensional memory according to an exemplary embodiment of the present application. As shown in fig. 9, the preparation method 1000 includes the following steps:

s11, forming a stacked structure on the substrate.

And S12, forming a plurality of channel structures penetrating through the stacked structure.

And S13, forming a top selection gate structure passing through part of the stacked structure between the adjacent channel structures.

And S14, performing ion doping on one end, far away from the substrate, of at least one channel structure in the plurality of channel structures.

According to the preparation method of the three-dimensional memory provided by at least one embodiment of the application, the top selection gate structure is arranged between the adjacent channel structures instead of occupying one row of channel structures, so that the area occupied by the top selection gate structure is saved. The end, far away from the substrate, of the channel structure is subjected to ion doping, so that the threshold voltage of the top selection transistor adjacent to the top selection gate structure is improved, the influence of potential coupling of a lower gate layer on the top selection transistor is smaller, the probability of mistaken opening of the top selection transistor is reduced, and the reliability of the three-dimensional memory is improved.

Specific processes of the respective steps of the above-described production method 1000 will be exemplified below.

Step S11

Referring to fig. 7, in some embodiments of the present application, the substrate 200 may be made of any suitable semiconductor material, such as a iii-v compound, which may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide. Alternatively, the substrate 200 may be fabricated from a single crystal silicon material.

In one embodiment of the present application, the substrate 200 may be, for example, a composite substrate for supporting device structures thereon. A plurality of layers made of different materials may be sequentially disposed through a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof to form the substrate 200.

In one embodiment of the present application, after the substrate 200 is formed, a stacked structure may be formed on one side of the substrate 200 through one or more thin film deposition processes, which may include, but are not limited to, CVD, PVD, ALD, or any combination thereof, which is not limited in this application. The stacked structure may include, for example, a plurality of pairs of insulating layers 211 and gate sacrificial layers (not shown) alternately stacked on each other. For example, the stacked structure may include 64 pairs, 128 pairs, or more than 128 pairs of the insulating layer 211 and the gate sacrificial layer. In some embodiments, the insulating layer 211 comprises a first dielectric material and the gate sacrificial layer comprises a second dielectric material different from the first dielectric material. Exemplary materials for forming the insulating layer 211 and the gate sacrificial layer may include silicon oxide and silicon nitride, respectively. A silicon oxide layer may be used as the insulating layer 211 to isolate the gate sacrificial layer, and a silicon nitride layer may be used as the gate sacrificial layer. The gate sacrificial layer may then be etched away and replaced with a gate layer 212 comprising a conductive material, resulting in a stacked structure 210.

It is understood that the step of replacing the gate sacrificial layer with the gate layer 212 comprising a conductive material may be performed after forming the channel structure 220 and/or the top select gate structure 230 without departing from the teachings of the present application, which is not limited in this application.

It should be understood that the manner in which the stacked structure 210 is formed may be selected as desired without departing from the teachings of the present application, which is not limited by the present application.

Step S12

Referring to fig. 7, in one embodiment of the present application, the step of forming the plurality of channel structures 220 penetrating the stacked structure 210 may include, for example: forming a trench hole (not shown) through the stacked structure 210; the functional layer 222 and the channel layer 221 are sequentially formed on the inner wall of the channel hole.

In one embodiment of the present application, the trench hole may be formed by, for example, a dry etching process or a combination of dry and wet etching processes. In addition, other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, may also be performed. Alternatively, the channel hole may be cylindrical or cylindrical in shape, for example.

In one embodiment of the present application, the functional layer 222 may be formed on the inner wall of the channel hole by a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. Referring to fig. 5, the step of forming the functional layer 222 includes: a blocking layer 2221, a charge trapping layer 2222, and a tunneling layer 2223 are sequentially formed on an inner wall of the channel hole, wherein the blocking layer 2221 may be used to block an outflow of charges, and the charge trapping layer 2222 may be used to store charges during an operation of the three-dimensional memory. Illustratively, the functional layer 222 may comprise an oxide-nitride-oxide (ONO) structure. For example, the functional layer 222 may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer. However, in some other embodiments, the functional layer 222 may have a structure different from the ONO configuration.

In one embodiment of the present application, the channel layer 221 may be formed on the surface of the tunneling layer 2223 through a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. The channel layer 221 can be used to transport desired charges (electrons or holes). Illustratively, the channel layer 221 may include silicon, such as amorphous silicon, polycrystalline silicon, or single crystal silicon. The material of the channel layer 221 may include, but is not limited to, P-type doped polysilicon.

In one embodiment of the present application, the channel holes, in which the channel layer 221 and the functional layer 222 have been formed, may be filled by a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof to form the channel filling layer 223. The trench fill layer 223 may include a dielectric layer of oxide, such as silicon oxide. Further, during the filling process, a plurality of insulation gaps may be formed in the trench filling layer 223 by controlling the trench filling process to relieve the structural stress. Alternatively, a channel plug 224 is formed on top of the channel structure 220. The channel plug 224 may be made of the same material as the channel layer 221, such as P-type doped polysilicon.

In one embodiment of the present application, after forming the channel filling layer 223, the top surface (the surface away from the substrate 200) of the channel structure 220 may include a plurality of rings of the channel layer 221 and the functional layer 222 sequentially surrounding the channel filling layer 223 from the inner side to the outer side along the radial direction of the channel structure 220, wherein the top surface of the channel filling layer 223 may have an approximately circular shape. A portion of the top of the channel structure 220 is removed and a recess (not shown) is formed over the channel structure 220 by performing one or more etching processes, including, for example, a dry etching process or a combination of dry and wet etching processes. The semiconductor layer, e.g., an amorphous silicon layer or a polycrystalline silicon layer, is formed by using a selective epitaxial process or by using a thin film deposition process such as ALD, CVD, PVD, or any other suitable process. The semiconductor layer may be in electrical contact with the channel layer 221 as a channel plug 224.

In some embodiments of the present application, referring to fig. 7, the plurality of channel structures 220 are located between a pair of gate slit structures 240, and the plurality of channel structures 220 are arranged in N rows, each row of channel structures being staggered from the channel structures of the adjacent rows; the top select gate structure 230 is located between the N/2 th row channel structure and the N/2+1 th row channel structure, where N is an even number. Because the top selection gate structure is arranged between the adjacent channel structures instead of occupying a row of channel structures, the area occupied by the top selection gate structure is saved.

Step S13

Referring again to fig. 7, in one embodiment of the present application, the step of forming a top select gate structure 230 between adjacent channel structures 220 through a portion of the stack structure 210 may, for example, include: forming a top select gate cut 231 through a portion of the stacked structure 210 between adjacent channel structures 220; top select gate cuts 231 are filled with a dielectric fill layer 232. Illustratively, the top select gate cut 231 may be formed through a portion of the stack layer 213 by etching down in the thickness direction of the stack structure in the stack structure 210 one or more times, e.g., a dry etching process or a combination of dry and wet etching processes. In a direction perpendicular to the thickness direction of the stacked structure, the top select gate cut 231 may or may not extend to the channel structure 220. A thin film deposition process, such as CVD, PVD, ALD, or any combination thereof, may be employed to deposit an appropriate dielectric material as the dielectric fill layer 232 in the top select gate cutouts 231 to form the top select gate structures 230. The dielectric material may comprise any suitable insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, or silicon oxide doped with any of fluorine, carbon, nitrogen, and hydrogen, or a high dielectric constant dielectric material, such as a hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, or lanthanum oxide film, although not limited thereto.

In one embodiment of the present application, the top select gate structure 230 is in contact with at least one channel structure 220.

As an example, the top select gate structure 230 is in contact with the functional layer 222 of the at least one channel structure 220. In this case, the step of forming the top select gate structure 230 may, for example, include: forming a top select gate cut 231 through a portion of the stacked structure 210 between adjacent channel structures 220, the top select gate cut 231 extending into the functional layer 222 of at least one channel structure 220; and top select gate cuts 231 are filled with a dielectric fill layer 232. In other words, the top select gate structure 230 has a contact area with the functional layer 222 of the channel structure 220 and no contact area with the channel layer 221.

As another example, the top select gate structure 230 is in contact with the functional layer 222 and the channel layer 221 of the at least one channel structure 220. In this case, the step of forming the top select gate structure 230 may, for example, include: forming a top select gate cut 231 through a portion of the stack structure 210 between adjacent channel structures 220, the top select gate cut 231 extending into the functional layer 222 and the channel layer 221 of at least one channel structure 220; and top select gate cuts 231 are filled with a dielectric fill layer 232. In other words, the top select gate structure 230 presents a contact area with the channel layer 221 and the functional layer 222 of the channel structure 220.

It is understood that the positional relationship of the top select gate cut 231 and the channel structure 220 may be set as desired without departing from the teachings of the present application, which is not limited in this application.

According to the embodiment of the application, under the condition that the top selection gate structure is in contact with the channel structure, the channel layer 221 of the channel structure 220 in contact with the top selection gate structure 230, which is close to one end of the top selection gate structure 230, is doped, so that the ion doping concentration of one end, which is far away from the substrate 200, of the channel structure 220 is increased, the threshold voltage of the top selection transistor adjacent to the top selection gate structure is increased, the influence of potential coupling of the lower gate layer 212 on the top selection transistor is reduced, the probability of false opening of the top selection transistor is reduced, the probability that the channel structure 220 cannot be completely turned off is also reduced, static turn-off current caused by an omega structure is suppressed, the static power consumption of a three-dimensional memory is reduced, and the reliability of the three-dimensional memory is improved.

Step S14

In an embodiment of the present application, the step of ion doping an end of the at least one channel structure 220 away from the substrate 200 may, for example, include: the end of the at least one channel structure 220 remote from the substrate 200 is doped with P-type ions. That is, the channel structure 220 in contact with the top select gate structure 230 is P-type ion doped. Alternatively, the process of P-type ion doping may be, for example, an ion implantation process.

In one embodiment of the present application, a schematic view of the doping direction of ion doping is shown in fig. 10. As can be seen from fig. 10, the doping direction of the ion doping is close to the direction perpendicular to the channel structure 220.

In one embodiment of the present application, the longitudinal depth of the ion doping is less than the length of the top select gate structure 230 in the thickness direction of the stack structure 210.

For example, referring to fig. 7, T stacked layers 213 of the plurality of stacked layers 213 of the stacked structure 210 far from the substrate 200 and the channel structure 220 in contact therewith form a top select gate transistor of the three-dimensional memory, and in order to reduce the case where the gate layer under the T stacked layers 214 is doped with ions to affect the storage function of the three-dimensional memory, the length of the channel layer doped in the embodiment of the present application may be less than or equal to the thickness of the T stacked layers 213. Typically, the length of top select gate structure 230 in the thickness direction of the stacked structure is greater than the thickness of the T stacked layers 213. Therefore, in the embodiments of the present application, the longitudinal depth of doping the channel structure 221 may be limited, so as to reduce the situation that the doping ions are distributed on the gate layer below the T stacked layers 214 to affect the storage function of the three-dimensional memory.

It should be understood that, in the above embodiment, the method 1000 for manufacturing a three-dimensional memory exemplifies the process of manufacturing a three-dimensional memory by ion doping the end of the channel structure 220 away from the substrate 200 after forming the top select gate structure 230. The step of ion doping the end of the at least one channel structure 220 remote from the substrate 200 may also be performed at any step after forming the channel structure 220 without departing from the teachings of the present application, which is not limited in this application.

For example, the step of ion doping the end of the at least one channel structure 220 away from the substrate 200 may be performed at any step after the step of forming the channel structure 220 and before the step of forming the top select gate cut 231. As shown in fig. 11, the method 2000 for manufacturing a three-dimensional memory includes the steps of:

s21, forming a stacked structure on the substrate.

And S22, forming a plurality of channel structures penetrating through the stacked structure.

And S23, performing ion doping on one end, far away from the substrate, of at least one channel structure in the plurality of channel structures.

In one embodiment of the present application, the longitudinal depth of the ion doping is less than the length of at least one channel structure (e.g., the channel structures on both sides of the region used to form the top select gate structure, or all of the channel structures) in the direction perpendicular to the substrate. The doping direction for ion doping the end of the at least one channel structure remote from the substrate 200 is approximately perpendicular to the channel structure. Wherein the channel structure for ion doping may be selected, for example, in dependence on the area used for forming the top select gate structure.

And S24, forming a top selection gate structure passing through part of the stacked structure between the adjacent channel structures.

For example, a top select gate cut is formed between adjacent channel structures through a portion of the stacked structure in contact with at least one channel structure; and filling the top selection gate notch with a dielectric filling layer.

Steps S21 to S24 in the method 2000 for manufacturing a three-dimensional memory are similar to steps S11, S12, S14 and S13 in the method 1000 for manufacturing a three-dimensional memory, respectively, and thus are not described herein again.

It should be understood that, in the above embodiments, the ion doping performed on the end of the channel structure 220 away from the substrate 200, which is contacted by the top selection gate structure 230, may be, for example, mask-free ion doping, that is, directly performing ion doping on the end of the channel structure 220 away from the substrate 200, and without departing from the teachings of the present application, the ion doping performed on the end of the channel structure 220 away from the substrate 200, which is contacted by the top selection gate structure 230, may also be, for example, masked ion doping, which is not limited by the present application.

For example, fig. 12 is a flowchart illustrating a method for manufacturing a three-dimensional memory according to another embodiment of the present disclosure, and fig. 13 is a schematic view illustrating a doping direction of ion doping in the method for manufacturing a three-dimensional memory shown in fig. 12. As shown in fig. 12, a method 3000 for manufacturing a three-dimensional memory includes the following steps:

s31, forming a stacked structure on the substrate.

And S32, forming a plurality of channel structures penetrating through the stacked structure.

S33, a top select gate cut is formed through a portion of the stacked structure between adjacent channel structures.

And S34, ion doping the end of the at least one channel structure far away from the substrate through the top selection gate notch, wherein the doping direction of the ion doping forms an included angle with the direction vertical to the channel structure.

S35, filling the top select gate cut with a dielectric fill layer.

Step S31 and step S32 in the method 3000 for manufacturing a three-dimensional memory are similar to step S11 and step S12 in the method 1000 for manufacturing a three-dimensional memory, respectively, and step S33 and step S35 are similar to step S13 in the method 1000 for manufacturing a three-dimensional memory, and are not described again here. The following mainly exemplifies step S34.

Step S34

In some embodiments of the present application, referring to fig. 13, after forming the top select gate cut 231, the channel structure 220 in contact with the top select gate cut 231 is ion-doped through the top select gate cut 231, and a doping direction of the ion-doping is at an angle with a vertical direction to the channel structure 220. In other words, the channel structure 220 in contact with the top select gate cut 231 is ion-doped by an ion implantation process having a tilt angle. By tilting the ion implantation process, the doping energy of the ion doping can be reduced.

In one embodiment of the present application, the angle between the doping direction and the direction perpendicular to the substrate 200 may be determined according to the size of the top select gate cut 231 in the direction perpendicular to the substrate 200. For example, if the top select gate cut 231 has a larger dimension perpendicular to the substrate 200, the included angle is smaller, and if the top select gate cut 231 has a smaller dimension perpendicular to the substrate 200, the included angle is larger. Alternatively, the included angle may be any angle less than 30 °, such as 5 °, 10 °, 15 °, and the like.

In one embodiment of the present application, referring to fig. 13, considering that the top select gate structure 230 may have contact with both side channel structures 220, after forming the top select gate cut 231, two times of ion doping are performed on the channel structures 220 to ensure that the portions of the channel structures 220 on both sides of the top select gate structure 230 near the top select gate cut 231 have ion implantation. Illustratively, after forming the top select gate cut 231, the step of performing two ion dopings on the channel structure 220 may include: the at least one channel structure is ion-doped a first time in a direction having a first angle a with a direction perpendicular to the channel structure (see dashed line direction in fig. 13), and a second time in a direction having a second angle β with the direction perpendicular to the channel structure (see dashed line direction in fig. 13), wherein the difference between the first angle and the second angle is larger than 180 °.

It is understood that the at least one channel structure 220 may also be ion doped, such as by a vertical ion implantation process, without departing from the teachings of the present application, which is not limited in this application.

According to the preparation method of the three-dimensional memory provided by at least one embodiment of the application, the top selection gate structure is arranged between the adjacent channel structures instead of occupying one row of channel structures, so that the area occupied by the top selection gate structure is saved. The channel structure in contact with the top selection gate structure is subjected to ion doping, the doping concentration of the channel layer at one end, close to the top selection gate structure, of the channel structure is increased, the threshold voltage of the top selection transistor adjacent to the top selection gate structure is improved, the influence of potential coupling of a lower grid layer on the top selection transistor is smaller, the probability of mistaken opening of the top selection transistor is reduced, and the reliability of the three-dimensional memory is improved.

FIG. 14 is a schematic block diagram of a storage system according to an embodiment of the present application. As shown in fig. 14, the storage system 40 includes a three-dimensional memory 410 and a controller 420. The controller 420 is electrically connected to the three-dimensional memory 410 for controlling the three-dimensional memory 410.

The three-dimensional memory 410 may be the same as the three-dimensional memory described in any of the above embodiments, and is not described in detail herein.

The controller 420 may control the three-dimensional memory 410 through the channel CH, and the three-dimensional memory 410 may perform an operation based on the control of the controller 420 in response to a request from the host 50. The three-dimensional memory 410 may receive a command CMD and an address ADDR from the controller 420 through a channel CH and access a region selected from the memory cell array in response to the address. In other words, the three-dimensional memory 410 may perform an internal operation corresponding to a command on an area selected by an address.

Although exemplary methods and structures of fabricating a three-dimensional memory are described herein, it will be understood that one or more features may be omitted, substituted, or added from the structure of the three-dimensional memory. For example, various well regions may be formed in the substrate as desired. Furthermore, the materials of the various layers illustrated are merely exemplary.

In the subsequent process of the method for manufacturing the three-dimensional memory, steps such as forming a peripheral circuit in the three-dimensional memory are also included. The embodiments and process flows in this application illustrate only the intermediate body of the three-dimensional memory that forms the gate gap structure.

The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (18)

1. A three-dimensional memory, comprising:

a stacked structure;

a plurality of channel structures including a channel layer and penetrating the stacked structure; and

a top select gate structure formed between adjacent ones of the channel structures and passing through a portion of the stack structure,

wherein, along the thickness direction of the stacked structure, one end of the channel layer of at least one channel structure close to the top selection gate structure is provided with a dopant.

2. The three-dimensional memory of claim 1, wherein the dopant is a P-type dopant.

3. The three-dimensional memory of claim 1, wherein a length of the channel layer having the dopant is less than a length of the top select gate structure in a thickness direction of the stack structure.

4. The three-dimensional memory of claim 1, wherein the three-dimensional memory further comprises:

a pair of gate slit structures penetrating the stacked structure;

the plurality of channel structures are positioned between the pair of gate gap structures and are arranged in N rows, and each row of channel structures and the channel structures in the adjacent rows are arranged in a staggered mode; the top selection gate structure is positioned between the N/2 th row channel structure and the N/2+1 th row channel structure, and N is an even number.

5. The three-dimensional memory of claim 1, wherein the top select gate structure is in contact with the at least one channel structure.

6. The three-dimensional memory of claim 5, wherein the channel structure comprises: the top selection gate structure is in contact with the functional layer.

7. The three-dimensional memory of claim 5, wherein the channel structure comprises: the top selection gate structure is in contact with the functional layer and the channel layer.

8. The three-dimensional memory according to claim 6 or 7, wherein the functional layer comprises: and the blocking layer, the charge trapping layer and the tunneling layer are sequentially arranged along the radial direction of the channel structure from outside to inside.

9. A storage system, comprising:

the three-dimensional memory of any one of claims 1 to 8; and

and the controller is electrically connected with the three-dimensional memory and is used for controlling the three-dimensional memory.

10. A method of fabricating a three-dimensional memory, the method comprising:

forming a stacked structure on a substrate;

forming a plurality of channel structures through the stacked structure;

forming a top select gate structure between adjacent channel structures through a portion of the stack structure; and

and ion doping one end of at least one channel structure far away from the substrate.

11. The method of claim 10, wherein ion doping the at least one channel structure comprises:

and carrying out P-type ion doping on one end of the at least one channel structure far away from the substrate.

12. The method of claim 10, wherein a longitudinal depth of the ion doping is less than a length of the top select gate structure in a thickness direction of the stack structure.

13. The method of claim 10, wherein forming the top select gate structure comprises:

forming a top select gate cut through a portion of the stack structure between adjacent channel structures; and

and filling the top selection gate notch with a dielectric filling layer.

14. The method of claim 13, wherein ion doping an end of the at least one channel structure distal to the substrate comprises:

before forming the top selection gate cut-out or after filling the top selection gate cut-out with the dielectric filling layer, performing ion doping on one end of the at least one channel structure far away from the substrate, wherein the doping direction of the ion doping is perpendicular to the channel structure.

15. The method of claim 13, wherein ion doping an end of the at least one channel structure distal to the substrate comprises:

and after the top selection gate notch is formed, carrying out ion doping on one end, far away from the substrate, of the at least one channel structure through the top selection gate notch, wherein an included angle exists between the doping direction of the ion doping and the direction vertical to the channel structure.

16. The method of claim 10, wherein forming the channel structure comprises:

forming a trench hole through the stacked structure; and

forming a functional layer and a channel layer on the inner wall of the channel hole in sequence,

wherein forming the top select gate structure comprises:

forming a top select gate cut through a portion of the stacked structure between adjacent ones of the channel structures, the top select gate cut extending to the functional layer of the at least one channel structure; and

and filling the top selection gate notch with a dielectric filling layer.

17. The method of claim 10, wherein forming the channel structure comprises:

forming a trench hole through the stacked structure; and

forming a functional layer and a channel layer on the inner wall of the channel hole in sequence,

wherein forming the top select gate structure comprises:

forming a top select gate cut through a portion of the stack structure between adjacent ones of the channel structures, the top select gate cut extending to the functional layer and the channel layer of the at least one channel structure; and

and filling the top selection gate notch with a dielectric filling layer.

18. The method of claim 16 or 17, wherein forming the functional layer comprises:

and forming a blocking layer, a charge trapping layer and a tunneling layer on the inner wall of the channel hole in sequence.

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