CN114639678A

CN114639678A - 3D memory device and method of manufacturing the same

Info

Publication number: CN114639678A
Application number: CN202210208732.4A
Authority: CN
Inventors: 王二伟; 杜明利; 郑晓芬
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-03-04
Filing date: 2022-03-04
Publication date: 2022-06-17

Abstract

Disclosed are a 3D memory device and a method of manufacturing the same, the method including: forming an insulating stack structure on a substrate, the insulating stack structure including a plurality of sacrificial layers and a plurality of interlayer insulating layers alternately stacked; forming a plurality of trench pillars penetrating the insulating stack structure; forming a plurality of gate line slits penetrating the insulating laminated structure; removing the plurality of sacrificial layers through the gate line gaps to form a cavity; sequentially forming a high-K dielectric layer, a titanium nitride layer and a gate conductor in the cavity; and forming a first insulating layer and a conductive channel in the gate line gap, wherein the high-K dielectric layer and the titanium nitride layer are positioned between adjacent interlayer insulating layers in the direction vertical to the surface of the substrate. According to the 3D memory device and the manufacturing method thereof, the high-K dielectric layer is etched back, so that the electric leakage problem of the device is reduced, and the yield and the reliability of the device are improved.

Description

3D memory device and method of manufacturing the same

Technical Field

The invention relates to the technical field of memories, in particular to a 3D memory device and a manufacturing method thereof.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes becomes smaller, the storage density of memory devices becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration in multiples on a unit area of a wafer, and can reduce cost.

In a 3D memory device of a NAND structure, gate conductors of a selection transistor and a memory transistor are provided in a stacked structure, and a memory cell string having a memory function is formed in a Single channel formation (Single channel formation) structure. In the manufacturing process of the 3D memory device, after the structure in the gate line gap is formed, when the wafer or the semiconductor structure is cleaned by a wet method, the cleaning agent is etched along the high K dielectric layer in the gate line gap, and further, a leakage problem (LKG) between adjacent conductors occurs in the subsequently deposited polysilicon layer.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a 3D memory device and a method for manufacturing the same, which can reduce the leakage problem of the device by etching back the high-K dielectric layer, thereby improving the yield and reliability of the device.

According to an aspect of the present invention, there is provided a method of manufacturing a 3D memory device, including: forming an insulating stack structure on a substrate, the insulating stack structure including a plurality of sacrificial layers and a plurality of interlayer insulating layers alternately stacked; forming a plurality of trench pillars penetrating the insulating stack structure; forming a plurality of gate line slits penetrating the insulating laminated structure; removing the plurality of sacrificial layers through the gate line gaps to form a cavity; sequentially forming a high-K dielectric layer, a titanium nitride layer and a gate conductor in the cavity; and forming a first insulating layer and a conductive channel in the gate line gap, wherein the high-K dielectric layer and the titanium nitride layer are positioned between adjacent interlayer insulating layers in the direction vertical to the surface of the substrate.

Optionally, the step of sequentially forming the high-K dielectric layer, the titanium nitride layer, and the gate conductor in the cavity includes: depositing a high-K dielectric material in the gate line gap and the cavity, and etching back the high-K dielectric material to form a high-K dielectric layer covering the gate line gap and the surface of the cavity; depositing a TiN material in the gate line gap and the cavity, and etching back the TiN material to form a titanium nitride layer covering the gate line gap and the surface of the cavity; and depositing a metal material in the gate line gap and the cavity, and etching back the metal material to form a gate conductor filling the cavity.

Optionally, after the step of etching back the metal material to form the gate conductor filling the cavity, the method further includes: carrying out second etching back on the titanium nitride layer, and removing the titanium nitride layer exposed in the gap of the grid line; and carrying out secondary back etching on the high-K dielectric layer, and removing the high-K dielectric layer exposed in the gap of the grid line.

Optionally, the high-K dielectric layer is made of aluminum oxide.

Optionally, the high-K dielectric layer is etched back for the second time by using phosphoric acid at 160 ℃.

Optionally, between the steps of forming an insulating stack structure on a substrate and forming a plurality of channel pillars penetrating through the insulating stack structure, the method further comprises: and forming a protective layer on the surface of the insulation laminated structure.

Optionally, after the step of forming the first insulating layer and the conductive channel in the gate line slit, the method further includes: removing the protective layer and cleaning the semiconductor structure; and forming a polycrystalline silicon layer and a laminated structure on the surface of the insulation laminated structure, wherein the laminated structure comprises oxide-nitride.

According to another aspect of the present invention, there is provided a 3D memory device including: a substrate; a gate stack structure over the substrate, the gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers that are alternately stacked; the gate stack structure comprises a gate conductor, a plurality of gate stack layers and a plurality of channel columns, wherein the channel columns penetrate through the gate stack structure, a high-K dielectric layer and a titanium nitride layer are further arranged between the gate conductor and the interlayer insulating layers, and the high-K dielectric layer and the titanium nitride layer are only arranged between adjacent interlayer insulating layers in the direction perpendicular to the surface of the substrate.

Optionally, the material of the high-K dielectric layer is aluminum oxide.

Optionally, the method further comprises: and the grid line gap penetrates through the grid laminated structure and divides the plurality of grid conductors into a plurality of grid lines.

Optionally, the method further comprises: the first insulating layer and the conductive channel are positioned in the grid line gap, and the first insulating layer isolates the conductive channel from the grid laminated structure.

According to the manufacturing method of the 3D memory device, the high-K dielectric layer in the gap of the grid line is etched back through wet etching, so that the high-K dielectric layer is not arranged on the side wall and the bottom of the gap of the grid line, the problem of electric leakage of the device caused by the fact that the cleaning agent is etched back along the high-K dielectric layer in the subsequent wet cleaning step is solved, and the yield and the reliability of the device are improved. In addition, the high-K dielectric layer is etched back by adopting wet etching, so that the cost is lower compared with that of dry etching.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

FIGS. 1a and 1b show partial views of a 3D memory device according to the prior art;

FIGS. 2a and 2b show an equivalent circuit diagram and a schematic structural diagram of a memory cell string of a 3D memory device, respectively;

FIG. 3 illustrates a perspective view of a 3D memory device according to an embodiment of the present invention;

fig. 4a to 4g illustrate cross-sectional views of stages of a method of manufacturing a 3D memory device according to an embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region, it can be directly on the other layer or region or intervening layers or regions may also be present in the structure of the device. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.

In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the device are described to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

Fig. 1a and 1b show partial views of a 3D memory device according to the prior art. As shown in fig. 1a, an insulating stacked structure is formed on a surface of a substrate 101, a trench pillar 110 penetrating through the insulating stacked structure is formed, a gate line gap penetrating through the insulating stacked structure is formed, a sacrificial layer in the stacked structure is removed through the gate line gap to form a cavity, and then a high-K dielectric layer 103, a titanium nitride layer 104, a gate conductor layer 109, a first insulating layer 105, and a conductive channel 143 are sequentially formed on the surface of the cavity through the gate line gap, wherein the high-K dielectric layer 103 is made of, for example, AlO. The gate conductor layer 109 is located between the interlayer insulating layers, the high-K dielectric layer 103 is located on the entire sidewall of the cavity, the titanium nitride layer 104 is located between the gate conductor layer 109 and the high-K dielectric layer 103, and the first insulating layer 105 isolates the conductive channel 143 from the gate conductor layer 109.

Further, as shown in fig. 1b, the semiconductor structure is subjected to wet cleaning, and then a polysilicon layer 107 and a second insulating layer 108 are deposited on the surface of the semiconductor structure. However, in the wet cleaning step, since the cleaning agent is etched back along the high-K dielectric layer 103, the polysilicon layer 107 deposited in the subsequent step is also deposited along the etched back gap of the high-K dielectric layer 103, which causes a leakage problem between adjacent conductors.

In addition, when the high-K dielectric layer 103 at the bottom of the gate line gap is removed, the dry etching cost is high.

The inventors of the present application have noticed the above-mentioned problems affecting the yield and reliability of the 3D memory device, and thus have proposed a further improved 3D memory device and a method of manufacturing the same.

The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.

The present invention may be embodied in various forms, some examples of which are described below.

Fig. 2a and 2b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device. The case where the memory cell string includes 4 memory cells is shown in this embodiment. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 2a, the memory cell string 100 has a first terminal connected to a bit line BL and a second terminal connected to a source line SL. The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first select transistor Q1, memory transistors M1-M4, and a second select transistor Q2. The gate of the first select transistor Q1 is connected to a string select line SSL, and the gate of the second select transistor Q2 is connected to a ground select line GSL. The gates of the memory transistors M1 through M4 are connected to corresponding ones of the word lines WL1 through WL4, respectively.

As shown in fig. 2b, the first select transistor Q1 and the second select transistor Q2 of the memory cell string 100 include

gate conductors

122 and 123, respectively, and the memory transistors M1 to M4 include gate conductors 121, respectively. The

gate conductors

121, 122, and 123 correspond to a stacking order of transistors in the memory cell string 100, and adjacent gate conductors are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. Channel pillar 110 extends through the gate stack structure. In the middle portion of the channel pillar 110, a tunnel dielectric layer 112, a charge storage layer 113, and a blocking dielectric layer 114 are interposed between the gate conductor 121 and the channel layer 111, thereby forming memory transistors M1 through M4. A blocking dielectric layer 114 is sandwiched between the

gate conductors

122 and 123 and the channel layer 111 at both ends of the channel pillar 110, thereby forming a first selection transistor Q1 and a second selection transistor Q2.

In this embodiment, the channel layer 111 is composed of, for example, doped polysilicon, the tunneling dielectric layer 112 and the blocking dielectric layer 114 are respectively composed of an oxide such as silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride containing particles of a metal or a semiconductor, and the

gate conductors

121, 122, and 123 are composed of a metal such as tungsten. The channel layer 111 serves to provide channel regions for controlling the selection transistor and the memory transistor, and the doping type of the channel layer 111 is the same as that of the selection transistor and the memory transistor. For example, for N-type select and memory transistors, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of channel pillar 110 is channel layer 111, and tunnel dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 form a stacked structure around the core sidewall. In an alternative embodiment, the core of channel pillar 110 is an additional insulating layer, and channel layer 111, tunnel dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 form a stacked structure surrounding the core.

In this embodiment, the first and second selection transistors Q1 and Q2, and the memory transistors M1 to M4 use the common channel layer 111 and the blocking dielectric layer 114. In the channel pillar 110, the channel layer 111 provides source-drain regions and a channel layer of a plurality of transistors. In an alternative embodiment, the epitaxial layers and the blocking dielectric layers of the first and second select transistors Q1 and Q2 and the epitaxial layers and the blocking dielectric layers of the memory transistors M1 to M4 may be formed separately in steps independent of each other.

In a write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 through M4 using FN tunneling efficiency. Taking memory transistor M2 as an example, while the source line SL is grounded, the ground select line GSL is biased to a voltage of about zero volts, so that the select transistor Q2 corresponding to the ground select line GSL is turned off, and the string select line SSL is biased to a high voltage VDD, so that the select transistor Q1 corresponding to the string select line SSL is turned on. Further, BIT line BIT2 is grounded, word line WL2 is biased at the programming voltage VPG, e.g., around 20V, and the remaining word lines are biased at the low voltage VPS 1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 through the tunneling dielectric layer 112, thereby converting data into charges stored in the charge storage layer 113 of the memory transistor M2.

In a read operation, the memory cell string 100 determines the amount of charge in the charge storage layer from the on-state of a selected one of the memory transistors M1 through M4, thereby obtaining data indicative of the amount of charge. Taking the memory transistor M2 as an example, word line WL2 is biased at the read voltage VRD, and the remaining word lines are biased at the high voltage VPS 2. The on state of the memory transistor M2 is related to its threshold voltage, i.e., the amount of charge in the charge storage layer, so that a data value can be determined according to the on state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in a conductive state, and therefore, the conductive state of the memory cell string 100 depends on the conductive state of the memory transistor M2. The control circuit judges the conductive state of the memory transistor M2 based on the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

Fig. 3 shows a perspective view of a 3D memory device. For clarity, the respective insulating layers in the 3D memory device are not shown in fig. 3.

The 3D memory device 200 shown in this embodiment includes 4 x 4 for a total of 16 memory cell strings 100, each memory cell string 100 including 4 memory cells, thereby forming a memory array of 4 x 4 for a total of 64 memory cells. It is understood that the present invention is not limited thereto and the 3D memory device may include any number of memory cell strings, for example, 1024, and the number of memory cells in each memory cell string may be any number, for example, 32 or 64.

In the 3D memory device 200, the memory cell strings respectively include the respective channel pillars 110, and the

common gate conductors

121, 122, and 123. The

gate conductors

121, 122, and 123 correspond to a stacking order of transistors in the memory cell string 100, and adjacent gate conductors are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure 120. The interlayer insulating layer is not shown in the figure.

The internal structure of the channel pillar 110 is shown in fig. 2b and will not be described in detail. The channel pillars 110 penetrate through the gate stack structure 120 and are arranged in an array, and a plurality of channel pillars 110 in a same column have first ends commonly connected to a same bit line (i.e., one of the bit lines BL1 to BL 4), second ends commonly connected to the substrate 101, and second ends forming a common source connection through the substrate 100.

The gate conductor 122 of the first selection transistor Q1 is divided into different gate lines by a gate line slit (gate line slit) 161. The gate lines of the channel pillars 110 in the same row are commonly connected to the same string selection line (i.e., one of the string selection lines SSL1 through SSL 4).

The gate conductors 121 of memory transistors M1 and M4 are each connected to a corresponding word line. If the gate conductors 121 of the memory transistors M1 and M4 are divided into different gate lines by the gate line slit 171, the gate lines of the same layer reach the interconnect layer 132 via respective conductive paths 131, are thereby interconnected with each other, and are then connected to the same word line (i.e., one of the word lines WL1 to WL 4) via the conductive path 133.

The gate conductors of the second select transistors Q2 are connected in one piece. If the gate conductor 123 of the second selection transistor Q2 is divided into different gate lines by the gate line slit 171, the gate lines reach the interconnection layer 132 via respective conductive paths 131 to be interconnected with each other, and then are connected to the same ground selection line GSL via the conductive path 133.

Dummy channel pillar 140 may be the same or different in internal structure from channel pillar 110 and passes through at least a portion of the gate conductor in the gate stack structure. In the final 3D memory device, the dummy channel pillars 140 are not connected to the bit lines, thereby providing only a mechanical support function, and are not used to form the select transistors and the memory transistors. Therefore, the dummy channel pillar 131 does not form an effective memory cell.

Fig. 4a to 4g illustrate cross-sectional views of stages of a method of manufacturing a 3D memory device according to an embodiment of the present invention. Fig. 4a to 4g show, for example, cross-sectional views along the dashed line AA in fig. 3.

The method starts with a semiconductor structure having formed thereon an insulating stack structure on a semiconductor substrate 101, as shown in fig. 4 a.

The semiconductor structure includes a semiconductor substrate 101 and an insulating stacked structure thereon. The insulating stack structure includes a plurality of interlayer insulating layers 102 and a plurality of sacrificial layers 142 that are alternately stacked. In this embodiment, the semiconductor substrate 101 is, for example, a single crystal silicon substrate, the interlayer insulating layer 102 is, for example, composed of silicon oxide, and the sacrifice layer 142 is, for example, composed of silicon nitride.

In order to form a conductive path from the gate conductor to the word line, the plurality of sacrificial layers 142 are, for example, patterned to be stepped (not shown in fig. 4a, refer to fig. 3), i.e., an edge portion of each sacrificial layer 142 is exposed with respect to an overlying sacrificial layer to provide an electrical connection region. After the patterning step of the plurality of sacrificial layers 142, the insulating stack structure is covered with the protective layer 141, and the channel pillar 110 penetrating the insulating stack structure is formed. Sacrificial layer 142 will be replaced with a gate conductor that is further connected to a word line, as described below.

In order to facilitate a program operation of a memory cell in the 3D memory device, a plurality of well regions and CMOS circuits (not shown) for driving selection transistors and memory transistors are formed in the semiconductor substrate 101.

Further, after the gate line slit 106 penetrating the insulating stacked structure is formed, the sacrificial layer 142 is removed through the gate line slit to form a cavity, as shown in fig. 4a and 4 b.

In this step, when the gate line slit 106 is formed, anisotropic etching, for example, dry etching such as ion milling etching, plasma etching, reactive ion etching, or laser ablation may be used. For example, by controlling the etching time so that the etching is stopped near the surface of the semiconductor substrate 101.

In this embodiment, the gate line slit 106 divides the gate conductor into a plurality of gate lines. For this, the gate line slit 106 penetrates the insulating laminated structure.

In forming the cavity, the sacrificial layer 142 in the insulation stack structure is removed by isotropic etching using the gate line slit 106 as an etchant path to form the cavity. The isotropic etching may employ selective wet etching or vapor etching. An etching solution is used as an etchant in wet etching, wherein the semiconductor structure is immersed in the etching solution. Etching gases are used as etchants in vapor phase etching, wherein the semiconductor structure is exposed to the etching gas.

In the case where the interlayer insulating layer 102 and the sacrificial layer 142 in the insulating stacked layer structure are composed of silicon oxide and silicon nitride, respectively, a phosphoric acid solution may be used as an etchant in wet etching, and C may be used in vapor phase etching₄F₈、C₄F₆、CH₂F₂And O₂One or more of (a). In the etching step, the gate line slit 106 is filled with an etchant. The end portion of the sacrificial layer 142 in the insulation stack structure is exposed in the opening of the gate line slit 106, and thus, the sacrificial layer 142 is contacted to the etchant. The etchant gradually etches the sacrificial layer 142 from the opening of the gate line slit 106 toward the inside of the insulating stacked structure. The etching removes the sacrificial layer 142 with respect to the interlayer insulating layer 102 in the insulating stack structure due to the selectivity of the etchant.

Preferably, after the above-described wet etching step, an additional etching step may be employed to remove an etching product (e.g., silicon oxide) attached on the interlayer insulating layer 102, so that the exposed surface of the interlayer insulating layer 102 in the cavity is planarized.

Further, a high-K dielectric layer 103 is formed on the surfaces of the cavity and the gate line slit via the gate line slit 106, as shown in fig. 4 c.

In this step, a dielectric material is deposited in the gate line slits 106 and the cavities by a deposition process such as Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or Chemical Vapor Deposition (CVD), and the dielectric material is etched back, and only the dielectric material on the gate line slits 106 and the surfaces of the cavities remains, thereby forming the high-K dielectric layer 103. The material of the high-K dielectric layer 103 is aluminum oxide (AlO).

Preferably, the dielectric material on the surface of the semiconductor structure is subjected to chemical mechanical polishing to thin or remove the dielectric material on the surface of the semiconductor structure before the step of etching back the dielectric material. The surface of the final semiconductor structure has a high-K dielectric layer 103 or no high-K dielectric layer 103.

Further, a titanium nitride layer 104 is formed on the surfaces of the cavity and the gate line gap through the gate line gap 106, as shown in fig. 4 d.

In this step, a TiN material is deposited in the gate line gap 106 and the cavity by a deposition process such as Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or Chemical Vapor Deposition (CVD), and the TiN material is etched back, so that only one layer of the TiN material on the surface of the high-K dielectric layer 103 remains, thereby forming the titanium nitride layer 104.

Preferably, the TiN material on the surface of the semiconductor is chemically mechanically polished to thin or remove the TiN material on the surface of the semiconductor structure before the step of etching back the TiN material. The surface of the final semiconductor structure has titanium nitride layer 104 or no titanium nitride layer 104.

Further, a metal material is deposited in the cavity through the gate line slit 106, and the metal material and the titanium nitride layer 104 are etched back, as shown in fig. 4 e.

In forming the gate conductor 109, the gate line slit 106 and the cavity are filled with a metal layer by Atomic Layer Deposition (ALD) using the gate line slit 106 as a deposition path.

In this embodiment, the metal layer is composed of tungsten, for example. The precursor source used in atomic layer deposition is, for example, tungsten hexafluoride WF₆The reducing gas used is, for example, silane SiH₄Or diborane B₂H₆. In the step of atomic layer deposition, tungsten hexafluoride is usedWF₆With silane SiH₄The chemical adsorption of the reaction product of (2) to obtain the tungsten material to realize the deposition process.

Further, the metal material and the titanium nitride layer 104 are etched back, the metal material and the titanium nitride layer 104 in the gap of the gate line are removed, and only the metal material and the titanium nitride layer 104 in the cavity are remained.

Further, the high-K dielectric layer 103 is etched back, as shown in fig. 4 f.

In this step, the high-K dielectric layer 103 exposed on the surface of the semiconductor structure and in the gate line gap is removed by a wet etching process, and only the high-K dielectric layer 103 between the titanium nitride layer 104 and the gate conductor layer 109 remains.

The wet etching process for removing the high-K dielectric layer 103 is, for example, to use phosphoric acid (H3PO4) at 160 ℃, and the semiconductor structure is soaked in the solution, so that the etching process is stopped after the high-K dielectric layer 103 is exposed in the gate line gap 106. Further, the high-K dielectric layer 103 in the semiconductor structure is processed by Rapid Thermal Annealing (RTA) in which the heating rate is 60A/min and the temperature is 1100 ℃.

Further, a first insulating layer 105 and a conductive via 106 are formed in the gate line slit, as shown in fig. 4 g.

In this step, an insulating material is deposited in the gate line slit 106 by a deposition process such as Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or Chemical Vapor Deposition (CVD), and then a via hole penetrating the insulating material is formed, and a conductive material is deposited in the via hole to form the conductive via 143.

In this embodiment, the first insulating layer 105 isolates the conductive channel from the gate conductor layer 109.

After this step, the method further includes removing the protective layer 141 on the surface of the semiconductor structure, cleaning the semiconductor structure, and forming a polysilicon layer 144 and a stacked structure 145 on the surface of the semiconductor structure, wherein the stacked structure 145 is, for example, an oxide-nitride stacked structure.

In this embodiment, since the high-K dielectric layer 103 is etched back, after the protective layer 141 on the surface of the semiconductor structure is removed, the high-K dielectric layer 103 does not exist between the first insulating layers 105 of the gate stack structure, and there is no other material, so that the phenomenon of etching back along the high-K dielectric layer 103 by cleaning does not occur in the subsequent cleaning step, thereby reducing the problem of leakage between adjacent conductors of the device.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method of manufacturing a 3D memory device, comprising:

forming an insulating stack structure on a substrate, the insulating stack structure including a plurality of sacrificial layers and a plurality of interlayer insulating layers alternately stacked;

forming a plurality of trench pillars penetrating the insulating stack structure;

forming a plurality of gate line slits penetrating the insulating laminated structure;

removing the plurality of sacrificial layers through the gate line gaps to form a cavity;

sequentially forming a high-K dielectric layer, a titanium nitride layer and a gate conductor in the cavity;

forming a first insulating layer and a conductive channel in the gate line slit,

and the high-K dielectric layer and the titanium nitride layer are positioned between adjacent interlayer insulating layers in the direction vertical to the surface of the substrate.

2. The method of manufacturing of claim 1, wherein the step of sequentially forming a high-K dielectric layer, a titanium nitride layer, and a gate conductor in the cavity comprises:

depositing a high-K dielectric material in the gate line gap and the cavity, and etching back the high-K dielectric material to form a high-K dielectric layer covering the gate line gap and the surface of the cavity;

depositing a TiN material in the gate line gap and the cavity, and etching back the TiN material to form a titanium nitride layer covering the gate line gap and the surface of the cavity;

and depositing a metal material in the gate line gap and the cavity, and etching back the metal material to form a gate conductor filling the cavity.

3. The method of manufacturing according to claim 2, wherein after the step of etching back the metal material to form the gate conductor filling the cavity, further comprising:

carrying out second etching back on the titanium nitride layer, and removing the titanium nitride layer exposed in the gap of the grid line;

and carrying out secondary back etching on the high-K dielectric layer, and removing the high-K dielectric layer exposed in the gap of the grid line.

4. The method of claim 3, wherein the high-K dielectric layer is made of aluminum oxide.

5. The manufacturing method according to claim 3 or 4, wherein the high-K dielectric layer is etched back for the second time by using phosphoric acid with the temperature of 160 ℃.

6. The method of manufacturing according to claim 1, wherein between the steps of forming an insulating stack structure on a substrate and forming a plurality of channel pillars penetrating the insulating stack structure, further comprising:

and forming a protective layer on the surface of the insulation laminated structure.

7. The method of manufacturing according to claim 1, further comprising, after the step of forming the first insulating layer and the conductive via in the gate line slit:

removing the protective layer and cleaning the semiconductor structure;

and forming a polysilicon layer and a laminated structure on the surface of the insulation laminated structure, wherein the laminated structure comprises oxide-nitride.

8. A 3D memory device comprising:

a substrate;

a gate stack structure over the substrate, the gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers that are alternately stacked;

a plurality of channel pillars extending through the gate stack structure,

the gate structure comprises a gate conductor, a gate insulating layer, a gate dielectric layer, a titanium nitride layer and a gate conductor, wherein the high-K dielectric layer and the titanium nitride layer are arranged between the gate conductor and the interlayer insulating layer and are only positioned between adjacent interlayer insulating layers in the direction vertical to the surface of the substrate.

9. The 3D memory device of claim 8, wherein the material of the high K dielectric layer is aluminum oxide.

10. The 3D memory device of claim 8, further comprising: and the grid line gap penetrates through the grid laminated structure and divides the plurality of grid conductors into a plurality of grid lines.

11. The 3D memory device of claim 10, further comprising: the first insulating layer and the conductive channel are positioned in the grid line gap, and the first insulating layer isolates the conductive channel from the grid laminated structure.