CN114637368B

CN114637368B - Current trimming circuit

Info

Publication number: CN114637368B
Application number: CN202210288852.XA
Authority: CN
Inventors: 张兆华
Original assignee: Huichun Technology Chengdu Co ltd
Current assignee: Huichun Technology Chengdu Co ltd
Priority date: 2022-03-22
Filing date: 2022-03-22
Publication date: 2024-06-04
Anticipated expiration: 2042-03-22
Also published as: CN114637368A

Abstract

The application provides a current trimming circuit which comprises a reference current output circuit, a first current dividing circuit, a first mirror image circuit, a second current dividing circuit and a second mirror image circuit which are connected in sequence; the reference current output circuit is used for outputting a reference current according to the band gap reference output voltage; the first current halving circuit is used for halving the reference current and outputting a first halving current; the first mirror circuit is used for mirroring the branch current and outputting a first mirror current; the second current halving circuit is used for halving the first mirror image current to obtain second halving current, and outputting a second halving current to the second mirror image circuit; the second mirror circuit is used for mirroring the second halved current to obtain a second mirror current, and the second mirror current is used as a trimming current of the reference current. The application enhances the driving capability and input matching property of the current by using a mirror current method, and can realize high-precision trimming of the current and improve the precision of the output current.

Description

Current trimming circuit

Technical Field

The application relates to the technical field of electronic circuits, in particular to a current trimming circuit.

Background

With the progress of the age, technology is becoming more and more popular, and chip circuits are fully integrated into the life of people and are indistinct. Generally, the chip circuit has small volume, small voltage and small current, so the chip circuit should be used as correctly as possible, and the deviation cannot be too large.

In the existing trimming circuit, the width-to-length ratio of the MOSFET is generally debugged, so that the trimming accuracy is limited, and the trimming is too simplified, so that the matching performance of an input signal, the current stability and the driving capability are not considered.

Disclosure of Invention

The application aims to provide a current trimming circuit, which is used for generating reference current for voltage output by a band gap reference through an operational amplifier and a cam structure, then trimming the reference current with high precision, enhancing current driving capability and input matching property by using a mirror current method, controlling independent current switches of trimming precision, avoiding mutual influence, and being capable of realizing trimming of the current with high precision and simultaneously improving the precision of output current.

In a first aspect, an embodiment of the present application provides a current trimming circuit, including: the reference current output circuit, the first current dividing circuit, the first mirror image circuit, the second current dividing circuit and the second mirror image circuit are sequentially connected; the reference current output circuit is used for outputting reference current to the first current dividing circuit according to the band gap reference output voltage; the first current halving circuit is used for halving the reference current and outputting a first quantity of first halving current to the first mirror circuit; the first mirror circuit is used for mirroring the first quantity of branch current and outputting the first quantity of first mirror current to the second current dividing circuit; the second current halving circuit is used for halving the first mirror current of the first quantity to obtain the second halving current of the second quantity, and outputting a second halving current to the second mirror circuit; the second number is the first number multiplied by a specified multiple; the second mirror circuit is used for mirroring the second halved current to obtain a third quantity of second mirror currents, and the second mirror currents are used as trimming currents of the reference current.

In an alternative embodiment, the reference current output circuit includes: the self-starting circuit comprises an operational amplifier, a self-starting circuit and a current output circuit; the non-inverting input end of the operational amplifier is connected with the band-gap reference output voltage, and the inverting input end and the output end are both connected with the self-starting circuit to form a feedback loop; the output end of the operational amplifier and the self-starting circuit are both connected with the current output circuit; the self-starting circuit is used for accelerating the establishment of a feedback loop; the current output circuit is used for outputting a reference current to the first current dividing circuit.

In an alternative embodiment, the self-starting circuit includes: the buffer, the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube and the third NMOS tube; the drains of the first PMOS tube and the second PMOS tube are connected with an analog power supply voltage AVCC; the grid electrode of the first PMOS tube is connected with the source electrode, and the drain electrode of the second NMOS tube, the source electrode of the second PMOS tube and the input end of the buffer are connected; the source electrode of the second PMOS tube is connected with the grid electrode and the source electrode of the first PMOS tube, the drain electrode of the second NMOS tube and the input end of the buffer; the drain electrode of the first NMOS tube is connected with the output end of the operational amplifier; the source electrode of the first NMOS tube is connected with the drain electrode of the third NMOS tube; the grid electrode of the third NMOS tube is connected with the output end of the buffer; the drain electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube; and a source electrode of the third NMOS tube is connected with an analog ground voltage VSSA.

In an alternative embodiment, the current output circuit includes: the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube and the first resistor; the grid electrodes of the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube are all connected with the output end of the operational amplifier; drain electrodes of the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube are all connected with the AVCC; the source electrode of the third PMOS tube is connected with the drain electrode of the fourth NMOS tube; the source electrode of the fourth PMOS tube is connected with the drain electrode of the fifth NMOS tube; the source electrode of the fifth PMOS tube is connected with the drain electrode of the sixth NMOS tube; the grid electrodes of the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube are all connected with a reference voltage VREF1; the drain electrode of the fourth NMOS tube is connected with the source electrode of the third PMOS tube; the source electrode of the fourth NMOS tube is connected with VSSA through a first resistor; the drain electrode of the fifth NMOS tube is connected with the source electrode of the fourth PMOS tube; the source electrode of the fifth NMOS tube outputs a reference current to be trimmed to the first current dividing circuit; the drain electrode of the sixth NMOS tube is connected with the source electrode of the fifth PMOS tube; the source electrode of the sixth NMOS tube is connected with the non-trimming reference current.

In an alternative embodiment, the first current dividing circuit includes: a first number of parallel first NMOS transistor pairs; the first NMOS tube pair comprises two NMOS tubes connected in series; in each first NMOS tube pair, the drain electrode of one NMOS tube is connected with the reference current to be trimmed, and the source electrode is connected with the drain electrode of the other NMOS tube; the source electrode of the other NMOS tube outputs a first equal current; the grid electrode of the other NMOS tube is controlled by a first enabling end; and the gates of all the corresponding NMOS transistors in the parallel first NMOS transistor pair are connected.

In an alternative embodiment, the first mirroring circuit includes: a number of second NMOS transistor pairs connected in parallel equal to the first number; in each second NMOS tube pair, the source electrode of one NMOS tube is connected with the drain electrode of the other NMOS tube; the drain electrode of the NMOS tube outputs a first mirror current; the source electrode of the other NMOS tube is connected with the first equal current; the grid electrode of the other NMOS tube is controlled by a first enabling end; and the gates of all the corresponding NMOS transistors in the parallel second NMOS transistor pair are connected.

In an alternative embodiment, the second current dividing circuit includes: a second number of third NMOS transistor pairs in parallel; the third NMOS tube pair comprises two NMOS tubes connected in series; in each third NMOS tube pair, the grid electrode of one NMOS tube is controlled by a second enabling end, the drain electrode is connected with an AVCC, and the source electrode is connected with the drain electrode of the other NMOS tube; the source electrode of the other NMOS tube outputs a second equal current, and the grid electrode is connected with VREF1; and the gates of all the corresponding NMOS transistors in the third NMOS transistor pair connected in parallel are connected.

In an alternative embodiment, the second mirroring circuit includes: a third number of fourth NMOS transistor pairs in parallel; the fourth NMOS tube pair comprises two NMOS tubes connected in series; in each fourth NMOS tube pair, the grid electrode of one NMOS tube is controlled by a second enabling end, the drain electrode is connected with an AVCC, and the source electrode is connected with the drain electrode of the other NMOS tube; the source electrode of the other NMOS tube outputs a second mirror current; the grid electrode of the other NMOS tube is connected with the control end; and the gates of all the corresponding NMOS transistors in the fourth NMOS transistor pair which are connected in parallel are connected.

In an alternative embodiment, in the current trimming circuit, the first number is 4, the second number is 16, and the third number is 31.

In an optional embodiment, the third number of fourth NMOS transistor pairs connected in parallel, and the gate of the other NMOS transistor in one fourth NMOS transistor pair is connected to the first gate voltage; the grid electrode of the other NMOS tube in the pair of the two fourth NMOS tubes is connected with a second grid voltage; the grid electrode of the other NMOS tube in the four fourth NMOS tubes is connected with a third grid voltage; the grid electrode of the other NMOS tube in the eight fourth NMOS tubes is connected with a fourth grid voltage; the grid electrode of the other NMOS tube in the sixteen fourth NMOS tubes is connected with a fifth grid voltage.

The embodiment of the application has the following beneficial effects:

The application provides a current trimming circuit, which is characterized in that reference current is generated on voltage output by a band gap reference through an operational amplifier and a cascode structure, then mirror images of MOSFET (metal oxide semiconductor field effect transistor) are utilized to obtain current mirror images, the mirror images are matched with the mirror images, and then the mirror images are matched to obtain controllable current, so that the controllable current can be trimmed with high precision. The circuit provided by the application mainly utilizes a mirror current method to enhance the driving capability of current, adopts mirror current to perform width-to-length ratio conversion in terms of input matching, and controls independent current switches of fine adjustment precision without mutual influence.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a block diagram of a current trimming circuit according to an embodiment of the present application;

FIG. 2 is a block diagram of a reference current output circuit according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a first current divider circuit and a first mirror circuit according to an embodiment of the present application;

FIG. 4 is a block diagram of a second current sharing circuit according to an embodiment of the present application;

fig. 5 is a block diagram of a second mirror circuit according to an embodiment of the present application.

Detailed Description

The technical solutions of the present application will be clearly and completely described in connection with the embodiments, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

At present, in a trimming circuit, the width-to-length ratio of a MOSFET is generally debugged, so that the trimming precision is limited, and in addition, the trimming is too simplified, the stability of current and the matching of input signals are ignored, and the driving capability of current also can be insufficient.

Based on this, the embodiment of the application provides a current trimming circuit, which generates a reference current for the voltage output by a band gap reference through an operational amplifier and a cascode structure, then carries out high-precision trimming on the reference current, enhances the driving capability and the input matching of the current by using a mirror current method, and can well improve the precision of the output current while realizing the high-precision trimming of the current.

For the convenience of understanding the present embodiment, a current trimming circuit disclosed in the embodiment of the present application will be described in detail.

As shown in fig. 1, an embodiment of the present application provides a current trimming circuit, which includes: the reference current output circuit 11, the first current dividing circuit 12, the first mirror circuit 13, the second current dividing circuit 14, and the second mirror circuit 15 are connected in this order.

The reference current output circuit 11 is configured to output a reference current to the first current dividing circuit 12 based on the bandgap reference output voltage. The reference current output circuit 11 generates and outputs a reference current as a trimming-carried reference current through an operational amplifier, a self-starting circuit, and a current output circuit.

The first current dividing circuit 12 divides the reference current into equal parts, and outputs a first divided current of a first amount to the first mirror circuit 13.

The first mirror circuit 13 mirrors the first number of branch currents, and outputs the first number of first mirror currents to the second current dividing circuit 14.

By equally dividing the total current, etc., and mirroring each branch of the divided current, the stability of the current and its driving capability can be enhanced.

The second current halving circuit 14 is configured to halve the first amount of the first mirror current to obtain a second amount of the second halving current, and output a second halving current to the second mirror circuit 15; the second number is the first number multiplied by a specified multiple.

The second mirror circuit 15 is configured to mirror the second divided current to obtain a third amount of second mirror current, and uses the second mirror current as a trimming current of the reference current.

By again aliquoting the current after the first mirroring, the aspect ratio of the MOSFET is changed in this; then, one part of the current obtained after the secondary halving is selected for mirroring, and each branch of the current obtained by the secondary halving is mirrored, so that the width-to-length ratio and the grid voltage of the MOSFET are equal, and the currents are equal; the second mirror current output at this time is the trimming current of the reference current, the trimming current has high precision, and each mirror branch can be controlled by the control end so as to achieve the purpose of trimming.

According to the current trimming circuit provided by the embodiment of the application, the reference current is output to the voltage output by the band gap reference through the reference current output circuit, and then the trimming current of the reference current is output by the equal division circuit and the mirror image circuit, and the driving capability and the input matching property of the current are enhanced by using the mirror image current method, so that the accuracy of the output current can be well improved while the trimming of the current with high accuracy is realized.

The embodiment of the application also provides another current trimming circuit which is realized on the basis of the circuit of the embodiment; this embodiment focuses on the specific structure and operation principle of the current trimming circuit.

An embodiment of the present application provides a current trimming circuit, as shown in fig. 1, including: the reference current output circuit 11, the first current dividing circuit 12, the first mirror circuit 13, the second current dividing circuit 14, and the second mirror circuit 15 are connected in this order.

Referring to fig. 2, in the current trimming circuit provided in the embodiment of the present application, the reference current output circuit 11 specifically includes: an operational amplifier OP, a self-starting circuit 21 and a current output circuit 22.

The non-inverting input end of the operational amplifier OP is connected with the band-gap reference output voltage VREF, and the inverting input end and the output end are both connected with the self-starting circuit 21 to form a feedback loop; the output terminal of the operational amplifier OP and the self-starting circuit 21 are both connected to the current output circuit 22.

The self-starting circuit 21 specifically includes: buffer and first PMOS pipe M0, second PMOS pipe M1, first NMOS pipe M2, second NMOS pipe M3 and third NMOS pipe M4. The drains of the first PMOS tube M0 and the second PMOS tube M1 are connected with an analog power supply voltage AVCC; the grid electrode and the source electrode of the first PMOS tube M0 are connected, and the drain electrode of the second NMOS tube M3, the source electrode of the second PMOS tube M1 and the input end of the Buffer are connected; the source electrode of the second PMOS tube M1 is connected with the grid electrode and the source electrode of the first PMOS tube M0, the drain electrode of the second NMOS tube M3 and the input end of the Buffer; the drain electrode of the first NMOS tube M2 is connected with the output end of the operational amplifier OP; the source electrode of the first NMOS tube M2 is connected with the drain electrode of the third NMOS tube M4; the grid electrode of the third NMOS tube M4 is connected with the output end of the Buffer; the drain electrode of the third NMOS tube M4 is connected with the source electrode of the first NMOS tube M2; the source of the third NMOS transistor M4 is connected to the analog ground voltage VSSA.

The self-starting circuit 21 described above is used to accelerate the establishment of the feedback loop. The non-inverting input end of the operational amplifier is connected with the reference voltage VREF, and the inverting input end of the operational amplifier is connected with the output of one branch of the cascode structure, wherein the input signal of the cascode structure is the output of the operational amplifier, so that a feedback loop is formed. Wherein M0-M4 and Buffer form a feedforward path, which belongs to a self-starting circuit and accelerates the establishment of a loop.

The current output circuit 22 specifically includes: the third PMOS tube M5, the fourth PMOS tube M6, the fifth PMOS tube M7, the fourth NMOS tube M8, the fifth NMOS tube M8, the sixth NMOS tube M10 and the first resistor R1;

The grid electrodes of the third PMOS tube M5, the fourth PMOS tube M6 and the fifth PMOS tube M7 are all connected with the output end of the operational amplifier OP; the drains of the third PMOS tube M5, the fourth PMOS tube M6 and the fifth PMOS tube M7 are all connected with an analog power supply voltage AVCC; the source electrode of the third PMOS tube M5 is connected with the drain electrode of the fourth NMOS tube M8; the source electrode of the fourth PMOS tube M6 is connected with the drain electrode of the fifth NMOS tube M9; the source electrode of the fifth PMOS tube M7 is connected with the drain electrode of the sixth NMOS tube M10; the grid electrodes of the fourth NMOS tube M8, the fifth NMOS tube M9 and the sixth NMOS tube M10 are all connected with a reference voltage VREF1; the drain electrode of the fourth NMOS tube M8 is connected with the source electrode of the third PMOS tube M5; the source electrode of the fourth NMOS tube M8 is connected with an analog ground voltage VSSA through a first resistor R1; the drain electrode of the fifth NMOS tube M9 is connected with the source electrode of the fourth PMOS tube M6; the source electrode of the fifth NMOS tube M9 outputs a reference current to be trimmed to the first current dividing circuit; the drain electrode of the sixth NMOS tube M10 is connected with the source electrode of the fifth PMOS tube M7; the source of the sixth NMOS transistor M10 is connected with the non-trimming reference current V0. V0 is a reference current which is not modified, and VREF1 can be equal.

The current output circuit 22 is configured to output the reference current to be trimmed to the first current dividing circuit 12.

When the current loop is not established yet, the first PMOS tube M0 pulls up the voltage of the input end of the Buffer, and the third NMOS tube M4 is started through the Buffer; the first NMOS tube M2 is a switch and is in an on state when in operation, so that the grid voltages of the three PMOS tubes M5, M6 and M7 can be pulled down, and the three PMOS tubes are further started; at this time, due to the existence of the reference voltage VREF1, currents are generated on the third PMOS tube M5, the fourth NMOS tube M8 and the first resistor R1, and then voltages are formed on the first resistor R1; at this time, the operational amplifier OP has voltages at both ends, and the OP will start to work normally. The self-starting circuit 21 and the current output circuit 22 can quickly and stably establish starting and output reference current to be trimmed.

Referring to fig. 3, in the current trimming circuit provided in the embodiment of the present application, the first current dividing circuit 12 specifically includes: a first number of parallel first NMOS transistor pairs; the first NMOS transistor pair comprises two NMOS transistors connected in series.

In the embodiment of the present application, the first number is preferably 4, that is, M11-M18 shown in fig. 3, and 4 pairs of parallel NMOS transistors are used.

In each first NMOS tube pair, for example, M11 and M12, the drain electrode of one NMOS tube M11 is connected with the reference current to be repaired, and the source electrode is connected with the drain electrode of the other NMOS tube M12; the source electrode of the other NMOS tube M12 outputs a first equal current; the grid electrode of the other NMOS tube M12 is controlled by a first enabling end; in the parallel first NMOS tube pair, the grid electrodes of all corresponding NMOS tubes are connected. M27 is the first enable terminal, active high.

The current output by the trimming branch passes through M11-M18, and the total current is equally divided into 4 equal parts.

As shown in fig. 3, in the current trimming circuit provided in the embodiment of the present application, the first mirror circuit 13 specifically includes: and the same number of second NMOS tube pairs connected in parallel as the first number.

In the embodiment of the present application, the first number is preferably 4, and the first mirror circuit also includes 4 parallel NMOS transistor pairs, that is, M19-M26 shown in fig. 3, and a total of 4 parallel NMOS transistor pairs.

In each second NMOS transistor pair, for example, M19 and M20, the source of one NMOS transistor M19 is connected to the drain of the other NMOS transistor M20; the drain electrode of the NMOS tube M19 outputs a first mirror current; the source electrode of the other NMOS tube M20 is connected with the first equal current; the grid electrode of the other NMOS tube M20 is controlled by a first enabling end; and the gates of all the corresponding NMOS transistors in the parallel second NMOS transistor pair are connected. M27 is the first enable terminal, active high.

The first mirror circuit mirrors the 4 branches of the obtained current, so that the stability of the current and the driving capability of the current are enhanced, and M19-M26 are mirror outputs.

Referring to fig. 4, in the current trimming circuit provided in the embodiment of the present application, the second current dividing circuit 14 specifically includes: a second number of third NMOS transistor pairs in parallel; the third NMOS transistor pair comprises two NMOS transistors connected in series.

In the embodiment of the present application, the second number is preferably 16, that is, M28-M59 in fig. 4, and 16 pairs of NMOS transistors.

In each of the third NMOS transistor pairs, for example, M28 and M32, the gate of one NMOS transistor M28 is controlled by the second enable terminal, the drain of M28 is connected to the analog supply voltage AVCC, and the source of M28 is connected to the drain of the other NMOS transistor M32; the source electrode of the other NMOS tube M32 outputs a second divided current, and the grid electrode of the other NMOS tube M32 is connected with a reference voltage VREF1; and in the third NMOS tube pair connected in parallel, the grid electrodes of all the corresponding NMOS tubes are connected. M60 is the second enable terminal, active high.

By the second current dividing circuit, the 4 parts of current are divided into 16 parts, M28-M59 are the results obtained by the dividing circuit, and the aspect ratio of the MOSFET is changed; cross-hatching can be used in subsequent layouts to match the input signals in subsequent circuit designs.

Referring to fig. 5, in the current trimming circuit provided in the embodiment of the present application, the second mirror circuit 15 specifically includes: a third number of fourth NMOS transistor pairs in parallel; the fourth NMOS tube pair comprises two NMOS tubes connected in series;

in the embodiment of the present application, the third number is preferably 31, that is, M61-M122 in fig. 5, and the total number of the pairs of NMOS transistors is 31.

In each of the fourth NMOS transistor pairs, for example, M61 and M69, the gate of one NMOS transistor M61 is controlled by the second enable terminal, the drain of M61 is connected to the analog supply voltage AVCC, and the source of M61 is connected to the drain of the other NMOS transistor M69; the source electrode of the other NMOS tube M69 outputs a second mirror current; the grid electrode of the other NMOS tube M69 is connected with the control end; and in the fourth NMOS tube pair connected in parallel, the grid electrodes of all the corresponding NMOS tubes are connected. M60 is the second enable terminal, active high.

After the second halving, 1 part of the 16 current was again selected and 31 parts were mirrored. The number of copies can be increased if necessary, and the aspect ratio and gate voltage of the MOSFET are equal, and the current is equal. The current is not equally divided by the current Fang Zong, but is changed from 16 to 31, as in M61-M122 of FIG. 5.

As shown in fig. 5, in a third number of fourth NMOS transistor pairs connected in parallel, the gate of the other NMOS transistor in one fourth NMOS transistor pair is connected to a first gate voltage C0; the grid electrode of the other NMOS tube in the pair of the two fourth NMOS tubes is connected with a second grid voltage C1; the grid electrode of the other NMOS tube in the four fourth NMOS tube pairs is connected with a third grid voltage C2; the grid electrode of the other NMOS tube in the eight fourth NMOS tube pairs is connected with a fourth grid voltage C3; and the grid electrode of the other NMOS tube in the sixteen fourth NMOS tube pairs is connected with a fifth grid voltage C4.

The 5 control ends of C0, C1, C2, C3 and C4 are used for respectively controlling the conduction of 1 part, 2 parts, 4 parts, 8 parts and 16 parts so as to achieve the purpose of trimming, wherein the output ends of C0 to C4 are equal to the grid voltage before mirroring. In the method, each part uses two NMOS in series, the upper NMOS is always in a conducting state, the high level is cut off, the low level is conducted according to the characteristics of the NMOS, the control end is in a grid, and the control end is conducted when the low level is input, so that the control end can work normally and participate in trimming.

The V1 output is the adjustable current with high precision. According to the current trimming circuit provided by the embodiment of the application, the reference current is output to the voltage output by the band gap reference through the reference current output circuit, then the trimming current of the reference current is output by the halving circuit and the mirror circuit, the driving capability of the current is enhanced by utilizing the mirror current method, the mirror-image current is adopted to perform the width-to-length ratio conversion in the aspect of input matching, the current switches for controlling the trimming precision are independent and are not influenced, the large current is divided into small currents, the sum of the small currents is selected and output, and the precision of the output current can be well improved while the trimming of the high precision of the current is realized.

In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

Finally, it should be noted that: the above examples are only specific embodiments of the present application, and are not intended to limit the scope of the present application, but it should be understood by those skilled in the art that the present application is not limited thereto, and that the present application is described in detail with reference to the foregoing examples: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A current trimming circuit, the current trimming circuit comprising: the reference current output circuit, the first current dividing circuit, the first mirror image circuit, the second current dividing circuit and the second mirror image circuit are sequentially connected;

the reference current output circuit is used for outputting reference current to the first current dividing circuit according to the band gap reference output voltage;

The first current halving circuit is used for halving the reference current and outputting a first quantity of first halving current to the first mirror circuit;

The first mirror circuit is used for mirroring the first quantity of branch current and outputting the first quantity of first mirror current to the second current dividing circuit;

the second current halving circuit is used for halving the first mirror current of the first quantity to obtain the second halving current of the second quantity, and outputting a second halving current to the second mirror circuit; the second number is the first number multiplied by a specified multiple;

The second mirror circuit is configured to mirror the second current to obtain a third number of second mirror currents, and take the second mirror currents as trimming currents of the reference currents.

2. The current trimming circuit of claim 1, wherein the reference current output circuit comprises: the self-starting circuit comprises an operational amplifier, a self-starting circuit and a current output circuit;

the non-inverting input end of the operational amplifier is connected with the band gap reference output voltage, and the inverting input end and the output end of the operational amplifier are both connected with the self-starting circuit to form a feedback loop; the output end of the operational amplifier and the self-starting circuit are both connected with the current output circuit;

The self-starting circuit is used for accelerating the establishment of the feedback loop;

the current output circuit is used for outputting reference current to the first current dividing circuit.

3. The current trimming circuit according to claim 2, wherein the self-starting circuit comprises: the buffer, the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube and the third NMOS tube;

the drains of the first PMOS tube and the second PMOS tube are connected with an analog power supply voltage AVCC; the grid electrode of the first PMOS tube is connected with the source electrode, and the drain electrode of the second NMOS tube, the source electrode of the second PMOS tube and the input end of the buffer are connected; the source electrode of the second PMOS tube is connected with the grid electrode and the source electrode of the first PMOS tube, the drain electrode of the second NMOS tube and the input end of the buffer; the drain electrode of the first NMOS tube is connected with the output end of the operational amplifier; the source electrode of the first NMOS tube is connected with the drain electrode of the third NMOS tube; the grid electrode of the third NMOS tube is connected with the output end of the buffer; the drain electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube; and a source electrode of the third NMOS tube is connected with an analog ground voltage VSSA.

4. The current trimming circuit of claim 3, wherein the current output circuit comprises: the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube and the first resistor;

The grid electrodes of the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube are all connected with the output end of the operational amplifier; drain electrodes of the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube are all connected with the AVCC; the source electrode of the third PMOS tube is connected with the drain electrode of the fourth NMOS tube; the source electrode of the fourth PMOS tube is connected with the drain electrode of the fifth NMOS tube; the source electrode of the fifth PMOS tube is connected with the drain electrode of the sixth NMOS tube; the grid electrodes of the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube are all connected with a reference voltage VREF1; the drain electrode of the fourth NMOS tube is connected with the source electrode of the third PMOS tube; the source electrode of the fourth NMOS tube is connected with the VSSA through the first resistor; the drain electrode of the fifth NMOS tube is connected with the source electrode of the fourth PMOS tube; the source electrode of the fifth NMOS tube outputs a reference current to be trimmed to the first current dividing circuit; the drain electrode of the sixth NMOS tube is connected with the source electrode of the fifth PMOS tube; and the source electrode of the sixth NMOS tube is connected with the non-trimming reference current.

5. The current trimming circuit of claim 4, wherein the first current dividing circuit comprises: a first number of parallel first NMOS transistor pairs; the first NMOS tube pair comprises two NMOS tubes connected in series;

in each first NMOS tube pair, the drain electrode of one NMOS tube is connected with the reference current to be trimmed, and the source electrode is connected with the drain electrode of the other NMOS tube; the source electrode of the other NMOS tube outputs a first equal current; the grid electrode of the other NMOS tube is controlled by a first enabling end;

and the gates of all the corresponding NMOS tubes in the parallel first NMOS tube pair are connected.

6. The current trimming circuit of claim 5, wherein the first mirror circuit comprises: a number of second NMOS transistor pairs connected in parallel equal to the first number;

The source electrode of one NMOS tube is connected with the drain electrode of the other NMOS tube in each second NMOS tube pair; the drain electrode of the NMOS tube outputs a first mirror current; the source electrode of the other NMOS tube is connected with the first equal current; the grid electrode of the other NMOS tube is controlled by a first enabling end;

and the gates of all the corresponding NMOS tubes in the parallel second NMOS tube pair are connected.

7. The current trimming circuit of claim 6, wherein the second current halving circuit comprises: a second number of third NMOS transistor pairs in parallel; the third NMOS tube pair comprises two NMOS tubes connected in series;

In each third NMOS tube pair, the grid electrode of one NMOS tube is controlled by a second enabling end, the drain electrode is connected with the AVCC, and the source electrode is connected with the drain electrode of the other NMOS tube; the source electrode of the other NMOS tube outputs a second equal current, and the grid electrode of the other NMOS tube is connected with VREF1;

And the gates of all the corresponding NMOS transistors in the third NMOS transistor pair connected in parallel are connected.

8. The current trimming circuit of claim 7, wherein the second mirror circuit comprises: a third number of fourth NMOS transistor pairs in parallel; the fourth NMOS tube pair comprises two NMOS tubes connected in series;

In each pair of the fourth NMOS transistors, the grid electrode of one NMOS transistor is controlled by a second enabling end, the drain electrode is connected with the AVCC, and the source electrode is connected with the drain electrode of the other NMOS transistor; the source electrode of the other NMOS tube outputs a second mirror current; the grid electrode of the other NMOS tube is connected with the control end;

And the gates of all the corresponding NMOS transistors in the fourth NMOS transistor pair which are connected in parallel are connected.

9. The current trimming circuit of claim 8, wherein the first number is 4, the second number is 16, and the third number is 31.

10. The current trimming circuit of claim 9, wherein,

A third number of fourth NMOS transistor pairs in parallel,

The grid electrode of the other NMOS tube in the pair of the fourth NMOS tubes is connected with a first grid voltage;

the grid electrode of the other NMOS tube in the pair of the two fourth NMOS tubes is connected with a second grid voltage;

the grid electrode of the other NMOS tube in the four fourth NMOS tube pairs is connected with a third grid voltage;

the grid electrode of the other NMOS tube in the eight fourth NMOS tube pairs is connected with a fourth grid voltage;

and the grid electrode of the other NMOS tube in the sixteen fourth NMOS tube pairs is connected with a fifth grid voltage.