CN114326895B - Comparator circuit capable of expanding input range - Google Patents
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Abstract
The invention provides a comparator circuit capable of expanding an input range, which comprises: the first-stage comparison circuit is connected with a power supply voltage VCC and is used for converting the differential voltage into differential current; the second-stage comparison circuit is connected with the first-stage comparison circuit and is used for mirroring and comparing the differential current; the first common ends of the first-stage comparison circuit and the second-stage comparison circuit are connected to a positive terminal voltage VP of the differential signal, and the second common ends are connected to a negative terminal voltage VN; and the upper end of the third-stage comparison circuit is connected with the second-stage comparison circuit, the lower end of the third-stage comparison circuit is connected to a circuit reference ground GND, and the third-stage comparison circuit is used for converting the voltage thresholds of the power supply voltage VCC-positive end voltage VP or negative end voltage VN of the differential output voltage of the first-stage comparison circuit and the second-stage comparison circuit into the voltage thresholds of the normal power supply voltage VCC-circuit reference ground GND. The invention supports the input of the positive and negative voltage comparator, expands the input range of the conventional comparator, and has the characteristics of wide common mode input range, high integration level, high flexibility and the like.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a comparator circuit with an expandable input range.
Background
A conventional comparator circuit is shown in fig. 1, wherein Vb provides a tail current source bias voltage, a threshold voltage of the MOS transistor is VTH, voltages at two ends of a drain source of the MOS transistor are VDS, and voltages at two ends of a gate source of the MOS transistor are VGS, so that it is ensured that the PM1 transistor does not enter a cut-off region under the condition that: VP + V THPM1 ≤VCC-V DSPM3 (ii) a Namely: VP is less than or equal to VCC-V DSPM3 -V THPM1 (ii) a The conditions to ensure that the PM1 tube does not enter the linear zone are: VP + V THPM1 ≥V GSNM1 Namely: VP is not less than V GSNM1 -V THPM1 。
In summary, the input range of the comparator VP is: VGSNM1-VTHPM1 is not less than VP not less than VCC-VDSPM3-VTHPM1. Generally speaking, if the threshold voltages of the PMOS transistor and the NMOS transistor are equal or close, the minimum input voltage range of VP is close to 0. Therefore, when the input voltage across the comparator is close to 0 or is a negative voltage, the conventional comparator cannot compare the two voltages well or even cannot compare the two voltages, thereby causing the comparator circuit to fail.
Disclosure of Invention
In view of this, the embodiment of the present disclosure provides a comparator circuit with an expandable input range, where the comparator circuit adopts a floating structure, supports the input of a positive-negative voltage comparator, expands the input range of a conventional comparator, and when the input range of the comparator is low or negative, an input differential pair transistor of the comparator is still in a saturation region, and has a maximum Gm transconductance value, so as to ensure that the flip rate of the comparator is not affected, and the comparator circuit has the characteristics of a wide common-mode input range, a high integration level, high activity, and the like.
In order to achieve the above purpose, the invention provides the following technical scheme:
an input range extendable comparator circuit comprising:
the first-stage comparison circuit is connected with a power supply voltage VCC and is used for converting the differential voltage into differential current;
the second-stage comparison circuit is connected with the first-stage comparison circuit and is used for mirroring and comparing the differential current;
the first common end of the first-stage comparison circuit and the second-stage comparison circuit is connected to a positive terminal voltage VP of the differential signal through a resistor R1, and the second common end is connected to a negative terminal voltage VN of the differential signal through a resistor R2;
the comparator circuit further comprises a third-stage comparison circuit, wherein the upper end of the third-stage comparison circuit is connected with the second-stage comparison circuit, the lower end of the third-stage comparison circuit is connected to a circuit reference ground GND, and the third-stage comparison circuit is used for converting the voltage thresholds of the power supply voltage VCC-positive end voltage VP or negative end voltage VN of the differential output voltages of the first-stage comparison circuit and the second-stage comparison circuit into the voltage thresholds of the normal power supply voltage VCC-circuit reference ground GND.
Further, the first-stage comparison circuit includes MOS pipe PM1, MOS pipe PM2, MOS pipe PM9, MOS pipe NM1, MOS pipe NM2, MOS pipe NM3 and MOS pipe NM4, the source of MOS pipe PM9 is accessed to the power supply voltage VCC, and the drain is connected respectively the source of MOS pipe PM1 and MOS pipe PM2, the drain of MOS pipe PM1 is connected the drain and the gate of MOS pipe NM1, the gate of MOS pipe NM2, and the drain of MOS pipe NM3, the drain of MOS pipe PM2 is connected the drain and the gate of MOS pipe NM4, the gate of MOS pipe NM3, and the drain of MOS pipe NM2, the sources of MOS pipe NM1, MOS pipe NM2, MOS pipe NM3 and MOS pipe NM4 are connected respectively to the first common terminal.
Further, the gate of the MOS transistor PM9 is connected to a tail current source bias voltage.
Further, the gate of the MOS transistor PM1 is connected to the positive terminal voltage VP of the differential signal, and the gate of the MOS transistor PM2 is connected to the negative terminal voltage VN of the differential signal.
Further, the second-stage comparison circuit includes a current mirror composed of a MOS transistor PM3, a MOS transistor PM4, a MOS transistor PM5, a MOS transistor PM6, a MOS transistor NM5, a MOS transistor NM6, a MOS transistor NM7, and a MOS transistor NM8, the differential output voltage V1 of the first-stage comparison circuit is connected to the gates of the MOS transistors NM5 and NM8, the differential output voltage V2 of the first-stage comparison circuit is connected to the gates of the MOS transistors NM6 and NM7, the drains of the MOS transistors NM5, NM6, NM7, and NM8 are connected to the drains of the MOS transistors PM3, PM4, PM5, and PM6, respectively, to form a mirror image, and the sources of the MOS transistors NM5, NM6, NM7, and NM8 are connected to the second common terminal, respectively.
Further, the third-stage comparison circuit includes a MOS transistor PM7, a MOS transistor PM8, a MOS transistor NM9 and a MOS transistor NM10, the differential output voltage V3 of the second-stage comparison circuit is connected to the gate of the MOS transistor NM10, the differential output voltage V4 of the second-stage comparison circuit is connected to the gate of the MOS transistor NM9, the drain of the NM9 is connected to the drain of the MOS transistor PM7 and the gate of the MOS transistor PM8, the drain of the MOS transistor NM10 is connected to the drain of the MOS transistor PM8, the gate of the MOS transistor PM7 and the output of the comparator circuit, and the sources of the MOS transistor NM9 and the MOS transistor NM10 are connected to the circuit reference ground GND.
Further, the width-to-length ratio of the MOS transistor NM1 is smaller than the width-to-length ratio of the MOS transistor PM1.
Further, the threshold voltage of the MOS transistor NM1 is smaller than the threshold voltage of the MOS transistor PM1.
Furthermore, MOS pipe PM1, MOS pipe PM2, MOS pipe PM3, MOS pipe PM4, MOS pipe PM5, MOS pipe PM6, MOS pipe PM7, MOS pipe PM8, MOS pipe PM9 are all P type MOS transistors.
Further, the MOS transistor NM1, the MOS transistor NM2, the MOS transistor NM3, the MOS transistor NM4, the MOS transistor NM5, the MOS transistor NM6, the MOS transistor NM7, the MOS transistor NM8, the MOS transistor NM9, and the MOS transistor NM10 are all N-type MOS transistors.
Compared with the traditional comparator circuit, the comparator circuit with the expandable input range can realize lower input voltage and even negative voltage of the comparator, greatly expands the input range of the comparator, and has the characteristics of wide common-mode input range, high integration level, high flexibility and the like, and the input differential pair transistors of the comparator are still in a saturation region and have the maximum Gm transconductance value when the input range of the comparator is lower or negative voltage, so that the turnover rate of the comparator is not influenced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a conventional comparator circuit;
fig. 2 is a circuit structure of a comparator with an expandable input range according to an embodiment of the present invention.
Detailed Description
The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure of the present disclosure. It is to be understood that the embodiments described are only a few embodiments of the present disclosure, and not all embodiments. The disclosure may be carried into practice or applied to various other specific embodiments, and various modifications and changes may be made in the details within the description and the drawings without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without inventive step, are intended to be within the scope of the present disclosure.
It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the disclosure, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present disclosure, and the drawings only show the components related to the present disclosure rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
The disclosed embodiment provides a comparator circuit with an expandable input range, comprising:
the first-stage comparison circuit is connected with a power supply voltage VCC and is used for converting the differential voltage into differential current;
the second-stage comparison circuit is connected with the first-stage comparison circuit and is used for mirroring and comparing the differential current;
the first common end of the first-stage comparison circuit and the second-stage comparison circuit is connected to a positive end voltage VP of the differential signal through a resistor R1, and the second common end is connected to a negative end voltage VN of the differential signal through a resistor R2;
the comparator circuit further comprises a third-stage comparison circuit, wherein the upper end of the third-stage comparison circuit is connected with the second-stage comparison circuit, the lower end of the third-stage comparison circuit is connected to a circuit reference ground GND, and the third-stage comparison circuit is used for converting a voltage threshold from a power supply voltage VCC to a positive terminal voltage VP or a negative terminal voltage VN of differential output voltages of the first-stage comparison circuit and the second-stage comparison circuit to a voltage threshold from a normal power supply voltage VCC to the circuit reference ground GND.
As shown in fig. 2, a comparator circuit for extending an input range proposed by the embodiment of the present disclosure is shown in fig. 2.
The first-stage comparison circuit comprises an MOS tube PM1, an MOS tube PM2, an MOS tube PM9, an MOS tube NM1, an MOS tube NM2, an MOS tube NM3 and an MOS tube NM4, wherein the source electrode of the MOS tube PM9 is connected with a power supply voltage VCC, the grid electrode of the MOS tube PM9 is connected with a tail current source bias voltage, the drain electrode of the MOS tube PM9 is respectively connected with the source electrodes of the MOS tube PM1 and the MOS tube PM2, the grid electrode of the MOS tube PM1 is connected with a positive terminal voltage VP of a differential signal, and the grid electrode of the MOS tube PM2 is connected with a negative terminal voltage VN of the differential signal; the drain electrode of MOS pipe PM1 is connected the drain electrode and the grid of MOS pipe NM1, the grid of MOS pipe NM2, and the drain electrode of MOS pipe NM3, the drain electrode of MOS pipe PM2 is connected the drain electrode and the grid of MOS pipe NM4, the grid of MOS pipe NM3, and the drain electrode of MOS pipe NM2, the source electrode of MOS pipe NM1, MOS pipe NM2, MOS pipe NM3 and MOS pipe NM4 is connected to respectively first common port.
The second-stage comparison circuit comprises a current mirror composed of an MOS tube PM3, an MOS tube PM4, an MOS tube PM5, an MOS tube PM6, an MOS tube NM5, an MOS tube NM6, an MOS tube NM7 and an MOS tube NM8, wherein a differential output voltage V1 of the first-stage comparison circuit is connected to the MOS tube NM5 and a grid electrode of the MOS tube NM8, a differential output voltage V2 of the first-stage comparison circuit is connected to the MOS tube NM6 and a grid electrode of the MOS tube NM7, drain electrodes of the MOS tube NM5, the MOS tube NM6, the MOS tube NM7 and the MOS tube NM8 are respectively connected with drain electrodes of the MOS tube PM3, the MOS tube PM4, the MOS tube PM5 and the MOS tube PM6 to form a mirror image, and source electrodes of the MOS tube NM5, the MOS tube NM6, the MOS tube NM7 and the MOS tube NM8 are respectively connected to the second common terminal.
The third-stage comparison circuit comprises a MOS tube PM7, a MOS tube PM8, a MOS tube NM9 and a MOS tube NM10, the differential output voltage V3 of the second-stage comparison circuit is connected to the grid of the MOS tube NM10, the differential output voltage V4 of the second-stage comparison circuit is connected to the grid of the MOS tube NM9, the drain of the NM9 is connected with the drain of the MOS tube PM7 and the grid of the MOS tube PM8, the drain of the MOS tube NM10 is connected with the drain of the MOS tube PM8, the grid of the MOS tube PM7 and the output of the comparator circuit, and the sources of the MOS tube NM9 and the MOS tube NM10 are connected to the circuit reference ground GND.
In the first-stage comparison circuit, when the positive end voltage VP is smaller than the negative end voltage VN, the voltage of the differential output voltage node V1 is greater than the voltage of the differential output voltage node V2; when the positive terminal voltage VP is greater than the negative terminal voltage VN, the differential output voltage node V1 voltage is less than the differential output voltage node V2 voltage.
In the second-stage comparison circuit, when the voltage of the differential output voltage node V1 is greater than the voltage of the differential output voltage node V2, the voltage of the differential output voltage node V3 is greater than the voltage of the differential output voltage node V4; when the differential output voltage node V1 voltage is less than the differential output voltage node V2 voltage, the differential output voltage node V3 voltage is less than the differential output voltage node V4 voltage.
In the third-stage comparison circuit, when the voltage of the differential output voltage node V3 is greater than the voltage of the differential output voltage node V4, the VOUT output is at a low level; when the differential output voltage node V3 voltage is less than the differential output voltage node V4 voltage, VOUT output is high.
When the positive terminal voltage VP = the negative terminal voltage VN, the VOUT output state is indefinite.
The input range of the comparator circuit is derived by setting the threshold voltage of the MOS transistor as V TH The voltage at the two ends of the drain and the source of the MOS tube is V DS The voltage at two ends of the gate source of the MOS tube is V Gs The bias current flowing through the tail current of the MOS transistor PM9 is I B ，R1＝R2＝R。
(1) The condition for ensuring that the MOS transistor PM1 does not enter the cut-off region is represented by formula 1:
VP+V THPM1 ≤VCC-V DSPM9 (formula 1)
Namely: VP is less than or equal to VCC-V DSPM9 -V THPM1
(2) The condition for ensuring that the MOS transistor PM1 does not enter the linear region is represented by formula 2:
VP+V THPM1 ≥V GSNM1 + V5 (type 2)
And:
from the above two equations, we can obtain:
in general, near the flip point of the comparator, the positive terminal voltage VP and the negative terminal voltage VN are approximately equal, so the above equation can be approximately converted to equation 3:
further elimination of VP affords formula 4:
according to the formula, the threshold voltage and tail current I of the MOS tube NM1 and the MOS tube PM1 are selected reasonably B The resistance R, the width-length ratio and other parameters, such as setting the width-length ratio of the MOS tube NM1 to be far smaller than the width-length ratio of the MOS tube PM1, the threshold voltage of the MOS tube NM1 to be smaller than the threshold voltage of the MOS tube PM1, and the smaller tail current I B And the resistor R and the like can ensure the solution of the formula, so that the input range of the voltage VP of the positive terminal can be lowered to any value within the range of ensuring the normal withstand voltage of the device.
In summary, the floating structure is adopted in the embodiment of the disclosure, the input range of the comparator can be greatly expanded, especially for low voltage and negative voltage ranges, the low voltage input and negative voltage input are supported, and the floating structure has the advantages of high integration level, simple circuit structure, high reliability and the like.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (7)
1. An input range extendable comparator circuit, comprising:
the first-stage comparison circuit is connected with a power supply voltage VCC and used for converting differential voltage into differential current, the first-stage comparison circuit comprises a MOS tube PM1, a MOS tube PM2, a MOS tube PM9, a MOS tube NM1, a MOS tube NM2, a MOS tube NM3 and a MOS tube NM4, the source of the MOS tube PM9 is connected with the power supply voltage VCC, the drain of the MOS tube PM9 is respectively connected with the sources of the MOS tube PM1 and the MOS tube PM2, the drain of the MOS tube PM1 is connected with the drain and the gate of the MOS tube NM1, the gate of the MOS tube NM2 and the drain of the MOS tube NM3, the drain of the MOS tube PM2 is connected with the drain and the gate of the MOS tube NM4, the gate of the MOS tube NM3 and the drain of the MOS tube NM2, the sources of the MOS tubes NM1, NM2, NM3 and NM4 are respectively connected with a first common terminal, the gate of the MOS tube PM9 is connected with a tail bias voltage, the gate of the MOS tube PM1 is connected with the negative terminal of the differential signal voltage, and the gate of the MOS tube PM2 is connected with the negative terminal voltage of the differential voltage;
the second-stage comparison circuit is connected with the first-stage comparison circuit and is used for mirroring and comparing the differential current;
the first common end of the first-stage comparison circuit and the second-stage comparison circuit is connected to a positive terminal voltage VP of the differential signal through a resistor R1, and the second common end is connected to a negative terminal voltage VN of the differential signal through a resistor R2;
the comparator circuit further comprises a third-stage comparison circuit, wherein the upper end of the third-stage comparison circuit is connected with the second-stage comparison circuit, the lower end of the third-stage comparison circuit is connected to a circuit reference ground GND, and the third-stage comparison circuit is used for converting the voltage thresholds of the power supply voltage VCC-positive end voltage VP or negative end voltage VN of the differential output voltages of the first-stage comparison circuit and the second-stage comparison circuit into the voltage thresholds of the normal power supply voltage VCC-circuit reference ground GND.
2. The extendable input range comparator circuit according to claim 1, wherein said second stage comparator circuit includes a current mirror formed by MOS transistors PM3, PM4, PM5, PM6, NM5, NM6, NM7 and NM8, said first stage comparator circuit has a differential output voltage V1 connected to the gates of said NM5 and NM8, said first stage comparator circuit has a differential output voltage V2 connected to the gates of said NM6 and NM7, said MOS transistors NM5, NM6, NM7 and NM8 have drains connected to the drains of said PM3, PM4, PM5 and PM6, respectively, forming a mirror image, and said MOS transistors NM5, NM6, NM7 and NM8 have sources connected to said second common terminal, respectively.
3. The extendable input range comparator circuit according to claim 2, wherein said third stage comparator circuit comprises a MOS transistor PM7, a MOS transistor PM8, a MOS transistor NM9 and a MOS transistor NM10, said second stage comparator circuit has a differential output voltage V3 connected to a gate of said MOS transistor NM10, said second stage comparator circuit has a differential output voltage V4 connected to a gate of said MOS transistor NM9, a drain of said NM9 is connected to a drain of said MOS transistor PM7 and a gate of said MOS transistor PM8, a drain of said MOS transistor NM10 is connected to a drain of said MOS transistor PM8, a gate of said MOS transistor PM7 and an output of said comparator circuit, and sources of said MOS transistors NM9 and NM10 are connected to said circuit reference ground GND.
4. The scalable input-range comparator circuit of claim 3, wherein the width-to-length ratio of the MOS transistor NM1 is smaller than the width-to-length ratio of the MOS transistor PM1.
5. The scalable input-range comparator circuit of claim 3, wherein the threshold voltage of the MOS transistor NM1 is smaller than the threshold voltage of the MOS transistor PM1.
6. The comparator circuit capable of expanding the input range according to claim 4 or 5, wherein the MOS transistor PM1, the MOS transistor PM2, the MOS transistor PM3, the MOS transistor PM4, the MOS transistor PM5, the MOS transistor PM6, the MOS transistor PM7, the MOS transistor PM8, and the MOS transistor PM9 are all P-type MOS transistors.
7. The comparator circuit with an expandable input range according to claim 4 or 5, wherein the MOS transistor NM1, the MOS transistor NM2, the MOS transistor NM3, the MOS transistor NM4, the MOS transistor NM5, the MOS transistor NM6, the MOS transistor NM7, the MOS transistor NM8, the MOS transistor NM9 and the MOS transistor NM10 are all N-type MOS transistors.
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| CN115996044B (en) * | 2023-03-22 | 2023-06-02 | 江苏润石科技有限公司 | Fast comparator |
| CN117278004B (en) * | 2023-11-21 | 2024-02-06 | 拓尔微电子股份有限公司 | Comparison circuit |
| CN117997347A (en) * | 2024-02-01 | 2024-05-07 | 灿芯半导体(上海)股份有限公司 | Dynamic comparator circuit applied to wide input common-mode voltage range in SARADC |
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| US20050218938A1 (en) * | 2004-03-23 | 2005-10-06 | Sanyo Electric Co., Ltd. | Comparator circuit |
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