CN114637358A - Power supply circuit and electronic equipment - Google Patents
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- CN114637358A CN114637358A CN202210287564.2A CN202210287564A CN114637358A CN 114637358 A CN114637358 A CN 114637358A CN 202210287564 A CN202210287564 A CN 202210287564A CN 114637358 A CN114637358 A CN 114637358A
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The invention provides a power supply circuit and an electronic device, wherein the power supply circuit comprises: the bias voltage generating module is used for generating bias voltage based on the power supply voltage of the power supply circuit; the bias voltage step-down module is used for performing step-down processing on the bias voltage to obtain a target bias voltage; the bias current generating module is used for generating a target bias current according to the target bias voltage; and the power supply current output module is used for generating a target power supply current according to the target bias current. The power supply circuit still cannot influence the output of the power supply current under the condition of modulating the power supply voltage, namely the power supply circuit can reduce the requirement on the power supply voltage while ensuring the basic characteristic of the output current.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a power supply circuit and an electronic device.
Background
With the continuous development of science and technology, various electronic devices have been widely applied to the life and work of people, and great convenience is brought to the daily life of people.
Based on different electronic devices, the operating voltages of normal operations of the electronic devices are different, and in many application scenarios, most of the electronic devices need a relatively small power supply voltage to drive the electronic devices to be in an operating state.
However, the minimum power voltage required by the current power supply circuit is still relatively large, and the actual circuit requirements cannot be met.
Therefore, how to reduce the power supply voltage of the power supply circuit is an urgent technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, to solve the above problems, the present invention provides a power supply circuit and an electronic device, and the technical solution is as follows:
a power supply circuit, the power supply circuit comprising:
a bias voltage generation module for generating a bias voltage based on a supply voltage of the power supply circuit;
the bias voltage step-down module is used for performing step-down processing on the bias voltage to obtain a target bias voltage;
the bias current generation module is used for generating a target bias current according to the target bias voltage;
and the power supply current output module is used for generating a target power supply current according to the target bias current.
Preferably, in the above power supply circuit, the bias voltage generation module includes: a first resistor and a first field effect transistor;
wherein a first end of the first resistor is connected to the power supply voltage;
the second end of the first resistor is connected with the drain electrode of the first field effect transistor;
the source electrode of the first field effect transistor is grounded;
and the drain electrode of the first field effect transistor is connected with the grid electrode of the first field effect transistor, and the connection node is used as the output end of the bias voltage generation module.
Preferably, in the above power supply circuit, the bias voltage step-down module includes: the second field effect transistor and the bias voltage reduction unit;
the grid electrode of the second field effect transistor is used for receiving the bias voltage;
the drain electrode of the second field effect transistor is connected with the power supply voltage;
the source electrode of the second field effect transistor is connected with the input end of the bias voltage reduction unit;
the grounding end of the bias voltage reduction unit is grounded;
and the output end of the bias voltage reduction unit is used as the output end of the bias voltage reduction module.
Preferably, in the above power supply circuit, the bias voltage step-down unit includes: a second resistor and a third resistor;
a first end of the second resistor is used as an input end of the bias voltage reduction unit;
the second end of the second resistor is connected with the first end of the third resistor, and a connection node is used as the output end of the bias voltage reduction unit;
and the second end of the third resistor is used as the grounding end of the bias voltage reduction unit.
Preferably, in the power supply circuit, the second fet is a zero-threshold fet.
Preferably, in the above power supply circuit, the bias current generating module includes: the third field effect transistor, the fourth field effect transistor and the fourth resistor;
wherein, the grid of the third field effect transistor is used for receiving the target bias voltage;
the source electrode of the third field effect transistor is grounded through the fourth resistor;
the drain electrode of the third field effect transistor is connected with the drain electrode of the fourth field effect transistor;
the source electrode of the fourth field effect transistor is connected with the power supply voltage;
and the grid electrode of the fourth field effect transistor is connected with the drain electrode of the fourth field effect transistor, and the connection node is used as the output end of the bias current generation module.
Preferably, in the power supply circuit, the third fet is a zero-threshold fet.
Preferably, in the above power supply circuit, the power supply current output module includes: a plurality of supply current output units;
each of the supply current output units is used for mirroring the target bias current to generate a target supply current.
Preferably, in the above power supply circuit, the supply current output unit includes: a fifth field effect transistor;
the grid electrode of the fifth field effect transistor is connected with the output end of the bias current generation module;
the source electrode of the fifth field effect transistor is connected with the power supply voltage;
and the drain electrode of the fifth field effect transistor is used as the output end of the power supply current output unit.
An electronic device comprising the power supply circuit of any of the above.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a power supply circuit, comprising: a bias voltage generation module for generating a bias voltage based on a supply voltage of the power supply circuit; the bias voltage reduction module is used for reducing the bias voltage to obtain a target bias voltage; the bias current generation module is used for generating a target bias current according to the target bias voltage; and the power supply current output module is used for generating a target power supply current according to the target bias current.
In the power supply circuit, a bias voltage generating module generates a bias voltage based on the power supply voltage of the power supply circuit, and the voltage reduction processing of the bias voltage is realized by controlling the voltage reduction degree of a bias voltage reduction module so as to reduce the power supply voltage required by the normal work of the power supply circuit; in addition, the power supply circuit still does not affect the output of the power supply current under the condition of modulating the power supply voltage, namely the power supply circuit can reduce the requirement on the power supply voltage while ensuring the basic characteristics of the output current.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a power supply circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a partial circuit structure of a power supply circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a partial circuit structure of another power supply circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a partial circuit structure of another power supply circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a partial circuit structure of another power supply circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another power supply circuit according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a partial circuit structure of another power supply circuit according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a power supply circuit according to an embodiment of the present invention.
The power supply circuit includes:
a bias voltage generating module 11, wherein the bias voltage generating module 11 is configured to generate a bias voltage based on a power supply voltage VDD of the power supply circuit.
And the bias voltage reducing module 12 is used for reducing the bias voltage to obtain a target bias voltage, wherein the bias voltage reducing module 12 is used for reducing the bias voltage.
A bias current generating module 13, wherein the bias current generating module 13 is configured to generate a target bias current according to the target bias voltage.
A supply current output module 14, wherein the supply current output module 14 is configured to generate a target supply current according to the target bias current.
In this embodiment, a voltage receiving end of the bias voltage generating module 11 is connected to the power supply voltage VDD, a ground end of the bias voltage generating module 11 is grounded GND, and an output end of the bias voltage generating module 11 is connected to an input end of the bias voltage dropping module 12.
The voltage receiving end of the bias voltage step-down module 12 is connected to the power voltage VDD, the ground end of the bias voltage step-down module 12 is grounded GND, and the output end of the bias voltage step-down module 12 is connected to the input end of the bias current generation module 13.
The voltage receiving end of the bias current generating module 13 is connected to the power supply voltage VDD, the ground end of the bias current generating module 13 is grounded GND, and the output end of the bias current generating module 13 is connected to the input end of the supply current output module 14.
The voltage receiving end of the power supply current output module 14 is connected to the power supply voltage VDD, and the output end of the power supply current output module 14 is used as the power supply current output end I of the power supply circuitOUT。
In the power supply circuit, a bias voltage generating module 11 generates a bias voltage based on a power supply voltage VDD of the power supply circuit, and the voltage reduction processing of the bias voltage is realized by controlling the voltage reduction degree of a bias voltage reducing module 12 so as to reduce the power supply voltage required by the normal work of the power supply circuit; in addition, the power supply circuit still does not affect the output of the power supply current under the condition of modulating the power supply voltage, namely the power supply circuit can reduce the requirement on the power supply voltage while ensuring the basic characteristics of the output current.
Optionally, in another embodiment of the present invention, referring to fig. 2, fig. 2 is a schematic diagram of a partial circuit structure of a power supply circuit according to an embodiment of the present invention.
The bias voltage generating module 11 includes: a first resistor R1 and a first field effect transistor M1.
Wherein a first end of the first resistor R1 is connected to the power supply voltage VDD.
The second end of the first resistor R1 is connected to the drain of the first FET M1.
The source of the first field effect transistor M1 is grounded GND.
The drain of the first fet M1 is connected to the gate of the first fet M1, and the connection node is used as the output terminal of the bias voltage generation module 11.
In this embodiment, a first end of the first resistor R1 is connected to the power supply voltage VDD as a voltage receiving end of the bias voltage generating module 11.
The source of the first fet M1 is grounded GND as the ground of the bias voltage generating module 11.
The connection node of the drain and the gate of the first field effect transistor M1 is used as the output terminal of the bias voltage generation module 11, and is connected to the input terminal of the bias voltage reduction module 12.
Optionally, the first fet M1 is an N-type fet.
Optionally, in another embodiment of the present invention, referring to fig. 3, fig. 3 is a schematic diagram of a partial circuit structure of another power supply circuit provided in the embodiment of the present invention.
The bias voltage dropping module 12 includes: a second field effect transistor M2 and a bias voltage dropping unit 121.
Wherein the gate of the second field effect transistor M2 is configured to receive the bias voltage.
The drain of the second fet M2 is connected to the supply voltage VDD.
The source of the second field effect transistor M2 is connected to the input terminal of the bias voltage dropping unit 121.
The ground terminal of the bias voltage dropping unit 121 is grounded to GND.
The output end of the bias voltage dropping unit 121 serves as the output end of the bias voltage dropping module 12.
In this embodiment, the gate of the second fet M2 is used as the input terminal of the bias voltage dropping module 12, and is connected to the output terminal of the bias voltage generating module 11, for receiving the bias voltage.
The drain of the second field effect transistor M2 is used as the voltage receiving terminal of the bias voltage step-down module 12, and is connected to the power supply voltage VDD.
The ground terminal of the bias voltage dropping unit 121 is grounded as the ground terminal GND of the bias voltage dropping module 12.
The output end of the bias voltage dropping unit 121 serves as the output end of the bias voltage dropping module 12, and is connected to the input end of the bias current generating module 13.
Optionally, the second fet M2 is an N-type fet.
Optionally, the second fet M2 is a zero-threshold fet.
Optionally, in another embodiment of the present invention, referring to fig. 4, fig. 4 is a schematic diagram of a partial circuit structure of another power supply circuit provided in an embodiment of the present invention.
The bias voltage dropping unit 121 includes: a second resistor R2 and a third resistor R3.
A first terminal of the second resistor R2 is used as an input terminal of the bias voltage dropping unit 121.
A second terminal of the second resistor R2 is connected to a first terminal of the third resistor R3, and a connection node is used as an output terminal of the bias voltage dropping unit 121.
A second terminal of the third resistor R3 is used as a ground terminal of the bias voltage dropping unit 121.
In this embodiment, a first end of the second resistor R2 is connected to a source of the second fet M2 as an input end of the bias voltage dropping unit 121.
A second end of the third resistor R3 is used as a ground terminal of the offset voltage dropping unit 121, and is also used as a ground terminal of the offset voltage dropping module 12.
A second end of the second resistor R2 is connected to a first end of the third resistor R3, and a connection node is used as an output end of the offset voltage dropping unit 121, which is also an output end of the offset voltage dropping module 12, and is connected to an input end of the offset current generating module 13.
Optionally, in another embodiment of the present invention, referring to fig. 5, fig. 5 is a schematic diagram of a partial circuit structure of another power supply circuit provided in an embodiment of the present invention.
The bias current generating module 13 includes: a third field effect transistor M3, a fourth field effect transistor M4 and a fourth resistor R4.
Wherein the gate of the third field effect transistor M3 is configured to receive the target bias voltage.
The source of the third field effect transistor M3 is grounded through the fourth resistor R4.
The drain electrode of the third field effect transistor M3 is connected with the drain electrode of the fourth field effect transistor R4.
The source electrode of the fourth field effect transistor M4 is connected to the power supply voltage VDD.
The gate of the fourth fet M4 is connected to the drain of the fourth fet M4, and the connection node is used as the output terminal of the bias current generating module 13.
In this embodiment, the source of the fourth fet M4 is used as the voltage receiving terminal of the bias current generating module 13 and is connected to the power supply voltage VDD.
The gate of the third fet M3 is used as the input terminal of the bias current generating module 13, connected to the output terminal of the bias voltage dropping module 12, and configured to receive the target bias voltage.
The ground terminal of the fourth resistor R4 is grounded GND as the ground terminal of the bias current generating module 13.
The connection node of the gate and the drain of the fourth field effect transistor M4 is used as the output terminal of the bias current generating module 13, and is connected to the input terminal of the supply current output module 14.
Optionally, the third fet M3 is an N-type fet.
Optionally, the fourth fet M4 is a P-type fet.
Optionally, the third fet M3 is a zero-threshold fet.
As shown in fig. 5, the branch for limiting the power supply voltage of the power supply circuit is the branch in which the fourth fet M4, the third fet M3 and the fourth resistor R4 are located, and specifically, the voltage difference across the fourth resistor R4 can be expressed as:
wherein, VGS1Is the gate-source voltage of the first fet M1.
Further, since the third fet M3 is a zero-threshold fet, V of the third fet M3 can be assumedDSSufficiently small, then the minimum supply voltage required by the supply circuit to ensure that all fets operate in the saturation region is:
wherein, VSG4Is the source gate voltage of the fourth fet M4.
Therefore, the minimum power supply voltage required by the power supply circuit can be changed by modulating the proportion of the second resistor R2 and the third resistor R3, and the minimum power supply voltage required by the power supply circuit can be further reduced by increasing the proportion of the second resistor R2 and the third resistor R3.
Optionally, in another embodiment of the present invention, referring to fig. 6, fig. 6 is a schematic structural diagram of another power supply circuit provided in the embodiment of the present invention.
The supply current output module 14 includes: a plurality of supply current output units 141.
Each of the supply current output units 141 is configured to mirror the target bias current to generate a target supply current.
In this embodiment, a voltage receiving terminal of the supply current output unit 141 serves as a voltage receiving terminal of the supply current output module 14 and is connected to the power supply voltage VDD.
The input end of the supply current output unit 141 is used as the input end of the supply current output module 14, and is connected to the output end of the bias current generation module 13.
The output terminal of the supply current output unit 141 serves as the output terminal of the supply current output module 14 and also serves as the supply current output terminal I of the supply circuitOUT。
It should be noted that the number of the supply current output units 141 can be increased or decreased according to actual requirements, and the number of the supply current output units 141 is not limited in the embodiment of the present invention.
Optionally, in another embodiment of the present invention, referring to fig. 7, fig. 7 is a schematic diagram of a partial circuit structure of another power supply circuit provided in the embodiment of the present invention.
The supply current output unit 141 includes: and a fifth field effect transistor Mp.
Wherein, the gate of the fifth field effect transistor Mp is connected with the output terminal of the bias current generating module 13.
The source of the fifth field effect transistor Mp is connected to the supply voltage VDD.
The drain of the fifth field effect transistor Mp serves as the output terminal of the supply current output unit 141.
Optionally, the fifth field effect transistor Mp is a P-type field effect transistor.
In this embodiment, the source of the fifth field effect transistor Mp is used as the voltage receiving terminal of the supply current output unit 141, and is also used as the voltage receiving terminal of the supply current output module 14, and is connected to the power supply voltage VDD.
The gate of the fifth field effect transistor Mp is used as the input terminal of the supply current output unit 141, and is also used as the input terminal of the supply current output module 14, and is connected to the output terminal of the bias current generation module 13.
The drain of the fifth field effect transistor Mp is used as the output terminal of the supply current output unit 141, the output terminal of the supply current output module 14, and the supply current output terminal I of the supply circuitOUT。
As shown in fig. 7, since the second fet M2 and the third fet M3 are both zero-threshold fets and the supply current in the power supply circuit is a mirror image of the current flowing through the fourth resistor R4, the current at the supply current output terminal in the power supply circuit can be represented as:
wherein, VGS1Is the gate-source voltage of the first fet M1.
Therefore, the supply current in the supply circuit is only related to the gate-source voltage of the field effect transistor, that is, the supply circuit does not affect the output of the supply current when modulating the supply voltage, that is, the supply circuit can reduce the requirement on the supply voltage while ensuring the basic characteristics of the output current.
Optionally, in another embodiment of the present invention, an electronic device is further provided, and referring to fig. 8, fig. 8 is a schematic structural diagram of the electronic device provided in the embodiment of the present invention.
The electronic device 15 includes the power supply circuit described in the above embodiment.
In this embodiment, the electronic device 15 includes, but is not limited to, an electronic device such as a mobile phone.
The above detailed description is provided for a power supply circuit and an electronic device provided by the present invention, and a specific example is applied in the present document to explain the principle and the implementation of the present invention, and the above description of the embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It should be noted that, in this specification, each embodiment is described in a progressive manner, and each embodiment focuses on differences from other embodiments, and portions that are the same as and similar to each other in each embodiment may be referred to. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include or include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A power supply circuit, characterized in that the power supply circuit comprises:
a bias voltage generation module to generate a bias voltage based on a supply voltage of the power supply circuit;
the bias voltage step-down module is used for performing step-down processing on the bias voltage to obtain a target bias voltage;
the bias current generation module is used for generating a target bias current according to the target bias voltage;
and the power supply current output module is used for generating a target power supply current according to the target bias current.
2. The power supply circuit of claim 1, wherein the bias voltage generating module comprises: a first resistor and a first field effect transistor;
wherein a first end of the first resistor is connected to the power supply voltage;
the second end of the first resistor is connected with the drain electrode of the first field effect transistor;
the source electrode of the first field effect transistor is grounded;
and the drain electrode of the first field effect transistor is connected with the grid electrode of the first field effect transistor, and the connection node is used as the output end of the bias voltage generation module.
3. The power supply circuit of claim 1, wherein the bias voltage dropping module comprises: the second field effect transistor and the bias voltage reduction unit;
the grid electrode of the second field effect transistor is used for receiving the bias voltage;
the drain electrode of the second field effect transistor is connected with the power supply voltage;
the source electrode of the second field effect transistor is connected with the input end of the bias voltage reduction unit;
the grounding end of the bias voltage reduction unit is grounded;
and the output end of the bias voltage reduction unit is used as the output end of the bias voltage reduction module.
4. The power supply circuit according to claim 3, wherein the bias voltage dropping unit includes: a second resistor and a third resistor;
a first end of the second resistor is used as an input end of the bias voltage reduction unit;
the second end of the second resistor is connected with the first end of the third resistor, and a connection node is used as the output end of the bias voltage reduction unit;
and the second end of the third resistor is used as the grounding end of the bias voltage reduction unit.
5. The power supply circuit of claim 3 wherein said second FET is a zero threshold FET.
6. The power supply circuit of claim 1, wherein the bias current generating module comprises: the third field effect transistor, the fourth field effect transistor and the fourth resistor;
wherein, the grid of the third field effect transistor is used for receiving the target bias voltage;
the source electrode of the third field effect transistor is grounded through the fourth resistor;
the drain electrode of the third field effect transistor is connected with the drain electrode of the fourth field effect transistor;
the source electrode of the fourth field effect transistor is connected with the power supply voltage;
and the grid electrode of the fourth field effect transistor is connected with the drain electrode of the fourth field effect transistor, and the connection node is used as the output end of the bias current generation module.
7. The power supply circuit of claim 6 wherein said third fet is a zero threshold fet.
8. The power supply circuit of claim 1, wherein the power supply current output module comprises: a plurality of supply current output units;
each of the supply current output units is used for mirroring the target bias current to generate a target supply current.
9. The power supply circuit according to claim 8, wherein the supply current output unit includes: a fifth field effect transistor;
the grid electrode of the fifth field effect transistor is connected with the output end of the bias current generation module;
the source electrode of the fifth field effect transistor is connected with the power supply voltage;
and the drain electrode of the fifth field effect transistor is used as the output end of the power supply current output unit.
10. An electronic device, characterized in that the electronic device comprises a supply circuit as claimed in any one of claims 1-9.
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| CN202210287564.2A CN114637358B (en) | 2022-03-23 | 2022-03-23 | Power supply circuit and electronic equipment |
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| CN202210287564.2A CN114637358B (en) | 2022-03-23 | 2022-03-23 | Power supply circuit and electronic equipment |
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| JPS63314059A (en) * | 1987-06-17 | 1988-12-22 | Fujitsu Ltd | Bias circuit for power feeding circuit |
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| CN103002636A (en) * | 2012-10-11 | 2013-03-27 | 索尔思光电（成都）有限公司 | Energy-saving drive circuit for providing bias current or driving current drive load |
| CN103092252A (en) * | 2012-10-23 | 2013-05-08 | 深圳先进技术研究院 | Power-independent biasing circuit |
| CN108880254A (en) * | 2018-08-20 | 2018-11-23 | 电子科技大学 | A kind of pre-biased circuit applied to DC-DC converter |
| CN113922770A (en) * | 2021-12-14 | 2022-01-11 | 深圳市时代速信科技有限公司 | Bias control circuit and electronic equipment |
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2022
- 2022-03-23 CN CN202210287564.2A patent/CN114637358B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63314059A (en) * | 1987-06-17 | 1988-12-22 | Fujitsu Ltd | Bias circuit for power feeding circuit |
| CN101097702A (en) * | 2006-06-28 | 2008-01-02 | 三洋电机株式会社 | Voltage regulator |
| CN103002636A (en) * | 2012-10-11 | 2013-03-27 | 索尔思光电（成都）有限公司 | Energy-saving drive circuit for providing bias current or driving current drive load |
| CN103092252A (en) * | 2012-10-23 | 2013-05-08 | 深圳先进技术研究院 | Power-independent biasing circuit |
| CN108880254A (en) * | 2018-08-20 | 2018-11-23 | 电子科技大学 | A kind of pre-biased circuit applied to DC-DC converter |
| CN113922770A (en) * | 2021-12-14 | 2022-01-11 | 深圳市时代速信科技有限公司 | Bias control circuit and electronic equipment |
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