CN114628410A

CN114628410A - Display panel, manufacturing method of transistor of display panel and display device

Info

Publication number: CN114628410A
Application number: CN202210272543.3A
Authority: CN
Inventors: 杨维; 袁广才; 宁策; 王利忠; 周天民; 付雨婷; 雷利平
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2022-03-18
Filing date: 2022-03-18
Publication date: 2022-06-14

Abstract

The utility model provides a display panel and manufacturing method, display device of transistor thereof, belongs to the display technology field. In the method, after a first gate metal layer, an active layer, a gate insulating layer and a second gate metal layer are formed on one side of a substrate, a target part of the active layer can be subjected to conductor processing, then an interlayer dielectric layer and a source drain metal layer are formed, and the source drain metal layer is overlapped with the active layer subjected to conductor processing through a via hole penetrating through the interlayer dielectric layer and the gate insulating layer, so that the transistor is obtained. Wherein, because the interlayer fixing layer comprises at least two insulating material layers, the compactness and the etching resistance are better. Therefore, when the via hole is formed, the contact part of the interlayer dielectric layer and the second gate metal layer is prevented from being broken, and the problem of abnormal display of the display panel is avoided.

Description

Display panel, manufacturing method of transistor of display panel and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display panel, a method for manufacturing a transistor of the display panel, and a display device.

Background

Oxide transistors are widely used in various display panels due to their advantages of small leakage current, long lifetime, etc. Such as a low temperature polycrystalline silicon oxide (LTPO) display panel.

At present, oxide transistors generally include: the first grid metal layer, the active layer, the grid insulating layer, the second grid metal layer, the interlayer dielectric layer and the source-drain metal layer are sequentially stacked along the direction far away from the substrate. The source drain metal layer can be lapped with the active layer through a via hole penetrating through the interlayer dielectric layer and the gate insulating layer.

However, since the conventional interlayer dielectric layer has poor etching resistance and density, when a via hole penetrating through the interlayer dielectric layer is formed, a portion of the interlayer dielectric layer in contact with the second gate metal layer is likely to be broken (Crack), and thus a display panel is likely to suffer from display abnormalities such as defective bright spots.

Disclosure of Invention

The embodiment of the application provides a display panel, a manufacturing method of a transistor of the display panel and a display device. The problem that display abnormity of a display panel is easy to occur in the related technology can be solved, and the technical scheme is as follows:

in one aspect, a method for manufacturing a transistor in a display panel is provided, the method including:

forming a first gate metal layer, an active layer, a gate insulating layer and a second gate metal layer on one side of a substrate, wherein an orthographic projection of the first gate metal layer on the substrate and an orthographic projection of the second gate metal layer on the substrate are both positioned in an orthographic projection of the active layer on the substrate, and an orthographic projection of the second gate metal layer on the substrate is also positioned in an orthographic projection of the first gate metal layer on the substrate and is positioned in an orthographic projection of the gate insulating layer on the substrate;

conducting a target portion of the active layer, an orthographic projection of the target portion on the substrate not overlapping an orthographic projection of the first gate metal layer on the substrate;

forming an interlayer dielectric layer on one side, far away from the substrate, of the second gate metal layer, wherein the interlayer dielectric layer comprises at least two insulation material layers which are sequentially stacked;

forming a via hole penetrating through the interlayer dielectric layer and the gate insulating layer;

and forming a source drain metal layer on one side of the interlayer dielectric layer, which is far away from the substrate, and overlapping the source drain metal layer with the active layer through the through hole to obtain the transistor.

Optionally, forming a second gate metal layer on one side of the substrate includes:

forming a gate metal film on one side of the gate insulating layer away from the substrate;

forming a photoresist pattern on one side of the gate metal film, which is far away from the substrate, wherein the orthographic projection of the photoresist pattern on the substrate is overlapped with the orthographic projection of the first gate metal layer on the substrate;

taking the photoresist pattern as a protective layer, and carrying out first etching treatment on the gate metal film to obtain a gate metal pattern;

performing ashing treatment on a first portion of the photoresist pattern to remove the first portion, and leaving a second portion except the first portion;

and taking the second part of the photoresist pattern as a protective layer, and carrying out second etching treatment on the gate metal pattern to obtain a second gate metal layer.

Optionally, the channelizing the target portion of the active layer includes:

after the first etching treatment is performed on the gate metal film, a target portion of the active layer is conducted.

Optionally, an orthographic projection of the gate insulating layer on the substrate overlaps with an orthographic projection of the first gate metal layer on the substrate, and the gate insulating layer is formed on one side of the substrate, including:

before forming a gate metal film on one side of the gate insulating layer, which is far away from the substrate, forming a gate insulating film on one side of the active layer, which is far away from the substrate;

and when the photoresist pattern is used as a protective layer and first etching treatment is carried out on the gate metal film, the first etching treatment is carried out on the gate insulating film, so that a gate insulating layer is obtained.

Optionally, the channelizing the target portion of the active layer includes: doping ions to a target portion of the active layer using a doping process to make the target portion of the active layer conductive.

Optionally, an orthographic projection of the gate insulating layer on the substrate covers an orthographic projection of the active layer on the substrate;

the conductimerizing the target portion of the active layer includes: dry etching the target portion of the active layer with a plasma formed from a dry etching gas to render the target portion of the active layer conductive.

Optionally, the interlayer dielectric layer includes: two insulating material layers stacked in sequence in a direction away from the substrate;

among the two insulating layers, the material of the insulating material layer close to one side of the substrate comprises: silicon oxide, the material of the insulating material layer on the side far away from the substrate comprises: and (3) silicon nitride.

Optionally, the material of the active layer includes: an oxide material.

In another aspect, there is provided a display panel including: a plurality of pixels each comprising a transistor fabricated using the method of the above aspect.

In still another aspect, there is provided a display device including: a power supply assembly, and a display panel as described in the above aspect;

the power supply assembly is connected with the display panel and used for supplying power to the display panel.

To sum up, the beneficial effects brought by the technical scheme provided by the embodiment of the application at least can include:

provided are a display panel, a manufacturing method of a transistor of the display panel and a display device. In the method, after a first gate metal layer, an active layer, a gate insulating layer and a second gate metal layer are formed on one side of a substrate, a target part of the active layer can be subjected to conductor processing, then an interlayer dielectric layer and a source drain metal layer are formed, and the source drain metal layer is overlapped with the active layer subjected to conductor processing through a via hole penetrating through the interlayer dielectric layer and the gate insulating layer, so that the transistor is obtained. Wherein, because the interlayer fixing layer comprises at least two insulating material layers, the compactness and the etching resistance are better. Therefore, when the via hole is formed, the contact part of the interlayer dielectric layer and the second gate metal layer is prevented from being broken, and the problem of abnormal display of the display panel is avoided.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a flowchart of a method for manufacturing a transistor in a display panel according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a transistor in a display panel according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a transistor in another display panel provided in this embodiment of the present application;

fig. 4 is a schematic structural diagram of a transistor in another display panel provided in the embodiment of the present application;

fig. 5 is a flowchart of a method for forming a gate metal layer according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a gate metal film and a photoresist pattern formed according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a gate metal pattern formed according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a structure for removing a first portion of a photoresist pattern according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a structure formed with a second gate metal layer according to an embodiment of the present disclosure;

fig. 10 is a flowchart of a method of forming a gate metal layer and a gate insulating layer according to an embodiment of the present disclosure;

fig. 11 is a schematic structural view of a gate metal film, a gate insulating film and a photoresist pattern formed according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of a gate insulating layer formed in accordance with an embodiment of the present disclosure;

FIG. 13 is a schematic diagram of another alternative structure for removing a first portion of a photoresist pattern according to an embodiment of the present application;

fig. 14 is a schematic structural diagram of another structure formed with a second gate metal layer according to an embodiment of the present disclosure;

fig. 15 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Fig. 1 is a flowchart of a method for manufacturing a transistor in a display panel according to an embodiment of the present disclosure. As shown in fig. 1, the method includes:

step 101, forming a first gate metal layer, an active layer, a gate insulating layer and a second gate metal layer on one side of a substrate.

Alternatively, the first gate metal layer, the active layer, the gate insulating layer, and the second gate metal layer may be formed on one side of the substrate through a one-time patterning process. The primary patterning process may include: gluing, exposing, developing and etching.

For example, fig. 2 shows a first Gate metal layer Gate1, an active (poly) layer P1, a Gate Insulation (GI) layer, and a second Gate metal layer Gate2 formed on one side of a substrate 01. The first Gate metal layer Gate1, the active layer P1, the Gate insulating layer GI1, and the second Gate metal layer Gate2 shown in fig. 2 are sequentially stacked in a direction away from the substrate 01. That is, the finally manufactured transistor may be a double-Gate transistor of a top-Gate (top-Gate) structure, wherein the first Gate metal layer Gate1 may be referred to as a bottom Gate (bottom Gate) in the double-Gate, and the second Gate metal layer Gate2 may be referred to as a top Gate in the double-Gate. Of course, in some other embodiments, the finally manufactured transistor can also be a double-gate transistor with a bottom gate structure.

Also, as can be seen from fig. 2, an orthogonal projection of the first Gate metal layer Gate1 formed on the substrate 01 and an orthogonal projection of the second Gate metal layer Gate2 formed on the substrate 01 are both located within an orthogonal projection of the active layer P1 on the substrate 01. The orthographic projection of the formed second Gate metal layer Gate2 on the substrate 01 is also located within the orthographic projection of the first Gate metal layer Gate1 on the substrate 01, and within the orthographic projection of the Gate insulating layer GI1 on the substrate 01. That is, the areas of the active layer P1, the first Gate metal layer Gate1, and the second Gate metal layer Gate2 may be sequentially reduced. For example, fig. 2 also shows a partially enlarged view in which the length of the first Gate metal layer Gate1 is denoted by (bottom length, Lb) and the length of the second Gate metal layer Gate2 is denoted by (top length, Lt), and it can be seen that Lb is greater than Lt. The length here may refer to a channel length of the gate metal layer.

Step 102, the target portion of the active layer is rendered conductive.

Alternatively, the target portion of the active layer P1 may be conducted through a doping process or a dry etching process. And, referring to fig. 2, an orthographic projection of a target portion of the active layer P1 on the substrate 01 does not overlap with an orthographic projection of the first Gate metal layer Gate1 on the substrate 01. That is, in the embodiment of the present application, the conductor formation process may be performed only on the portion of the active layer P1 other than the region directly above the first Gate metal layer Gate 1. Thus, the effective channel length of the active layer P1 can be ensured to be longer, thereby ensuring that the characteristics of the manufactured transistor are more stable.

For example, referring to a partial enlarged view shown in fig. 2, a portion of the active layer P1 not overlapping with the second Gate metal layer Gate2 is identified as an X region, a portion of the active layer P1 not overlapping with the first Gate metal layer Gate1 is identified as a Y region, and a portion of the active layer P1 overlapping with the first Gate metal layer Gate1 but not overlapping with the second Gate metal layer Gate2 is identified as a Z region (i.e., an X region-Y region). In the embodiment of the present application, the conductor forming process may be performed only on the target portion in the Y region in the active layer P1. The purpose of the conductor formation process is to: the Source and Drain (SD) metal layer formed later and the active layer P1 can be electrically connected reliably, the on-resistance of the active layer P1 is reduced, and the on-state current Ion of the transistor is increased.

And 103, forming an interlayer dielectric layer on one side of the second gate metal layer far away from the substrate.

Alternatively, an inter-level dielectric (ILD) layer may be formed on a side of the second gate metal layer away from the substrate by a deposition process. And in the embodiment of the present application, the interlayer dielectric ILD1 is formed to include at least two layers of insulating material stacked in sequence.

For example, referring to fig. 2, the interlayer dielectric ILD1 shown comprises two layers of insulating material ILD11 and ILD12 stacked in sequence, the materials of the two layers of insulating material ILD11 and ILD12 may be different, i.e., the two layers of insulating material ILD11 and ILD12 may be made of different insulating materials. For example, in the two insulating material layers ILD11 and ILD12, the material of one insulating material layer may be silicon oxide (SiO), and the material of the other insulating material layer may be silicon nitride (SiN). Therefore, by means of the difference of compactness and etching resistance among materials, the compactness and the etching resistance of the whole interlayer dielectric ILD1 are improved, and the phenomenon that when a via hole is formed subsequently, the contact part of the interlayer dielectric ILD1 and the second Gate metal layer Gate2 generates Crack is avoided, so that the probability of display abnormity of bright spot defects of the display panel is reduced, and the delivery yield of the display panel is improved.

And 104, forming a through hole penetrating through the interlayer dielectric layer and the gate insulating layer.

Optionally, the interlayer dielectric ILD1 and the gate insulating layer GI1 may be etched together by an etching process, so as to form a via hole penetrating through the interlayer dielectric ILD1 and the gate insulating layer GI 1.

For example, fig. 2 also shows a via hole K1 formed, where the via hole K1 may expose the active layer P1, so that the subsequently formed source and drain metal layers SD1 and P1 can effectively overlap.

And 105, forming a source drain metal layer on one side of the interlayer dielectric layer, which is far away from the substrate, and overlapping the source drain metal layer with the active layer through the through hole to obtain the transistor.

Alternatively, the source/drain metal layer SD1 may be formed on the side of the interlayer dielectric ILD1 away from the substrate 01 by a single patterning process.

For example, fig. 2 further illustrates a formed source drain metal layer SD1, the source drain metal layer SD1 may include a source portion S1 and a drain portion D1 which are arranged at intervals, the source portion S1 may overlap with the active layer P1 through one via K1 penetrating through the interlayer ILD1, and the drain portion D1 may overlap with the active layer P1 through another via K1 penetrating through the interlayer ILD1, so as to obtain the transistor T1.

It should be noted that, referring to fig. 2, it can also be seen that an orthographic projection of the overlap of the source-drain metal layer SD1 and the active layer P1 on the substrate 01 does not overlap with an orthographic projection of the first Gate metal layer Gate1 on the substrate 01, and the Gate insulating layer GI1 and the second Gate metal layer Gate2 may be located between the source portion S1 and the drain portion D1.

Alternatively, as can also be seen with reference to fig. 2, in an embodiment of the present application, a substrate 01 may be provided that includes a glass (glass) base 011 and a flexible substrate 012 disposed in a stacked manner. The material of the flexible substrate 012 may be a Polyimide (PI) material, and accordingly, the flexible substrate 012 may also be referred to as a PI substrate. And, the transistor T1 may further include: an insulating material layer (not shown) between the substrate 01 and the first Gate metal layer Gate1, and another interlayer dielectric layer ILD2 and a protective (barrier) layer B1 between the first Gate metal layer Gate1 and the active layer P1, which are sequentially stacked in a direction away from the substrate 01, so as to achieve insulation between two adjacent conductive layers and protection of film layers on both sides of the protective layer B1.

In summary, the embodiments of the present application provide a method for manufacturing a transistor in a display panel. In the method, after a first gate metal layer, an active layer, a gate insulating layer and a second gate metal layer are formed on one side of a substrate, a target part of the active layer can be subjected to conductor processing, then an interlayer dielectric layer and a source drain metal layer are formed, and the source drain metal layer is overlapped with the active layer subjected to conductor processing through a via hole penetrating through the interlayer dielectric layer and the gate insulating layer, so that the transistor is obtained. Wherein, because the interlayer dielectric layer comprises at least two insulating material layers, the compactness and the etching resistance are better. Therefore, when the via hole is formed, the contact part of the interlayer dielectric layer and the second gate metal layer is prevented from being broken, and the problem of abnormal display of the display panel is avoided.

In addition, in the embodiment of the present invention, only the portion of the active layer located outside the region directly opposite to the first gate metal layer is made into a conductor, so that the effective channel length of the active layer (i.e., the length of the portion which is not made into a conductor) can be ensured to be sufficiently long, and the characteristics of the manufactured transistor can be ensured to be stable.

Alternatively, referring to fig. 2, the interlayer ILD1 on the side of the second Gate metal layer Gate2 away from the substrate 01 may include: two layers of insulating material, ILD11 and ILD12, stacked in sequence in a direction away from substrate 01. The material of the insulating material layer ILD11 near the side of substrate 01 may include: the material of the insulating-material layer ILD12 on the side of the silicon oxide SiO, facing away from the substrate 01, may include: silicon nitride SiN. That is, in the interlayer dielectric ILD1, the material of the Top layer (Top layer) far from the substrate 01 may be silicon nitride SiN.

Because the silicon nitride SiN has better compactness and etching resistance compared with silicon oxide SiO, the problem of Crack at the contact part of the interlayer dielectric layer ILD1 and the second Gate metal layer Gate2 when the interlayer dielectric layer ILD1 is etched to form the via hole K1 can be further effectively avoided by setting the top layer part of the silicon nitride SiN as the material.

Of course, in some other embodiments, the silicon nitride SiN may be replaced by other materials with better compactness and etching resistance, such as aluminum oxide (AlO). In the related art, the transistor includes an ILD1 which is typically only SiO.

Alternatively, in the embodiment of the present application, the material of the active layer P1 may include: an oxide (oxide) material. That is, the transistor T1 manufactured by the method shown in fig. 1 may be referred to as an oxide transistor.

Illustratively, the oxide material may include: indium Gallium Zinc Oxide (IGZO) material, zinc oxide ZnO material, or tin oxide SnO material. In the embodiments of the present application, the IGZO material is used as the material of the active layer P1, that is, the IGZO transistor T1 is used as an example.

Alternatively, referring to another display panel shown in fig. 3, in the embodiment of the present application, the display panel may further include a transistor T2 in which the material of the active layer P2 is a P-silicon (Si) material, in addition to the oxide transistor T1 manufactured by the above method. The P-Si material may be a Low Temperature Polysilicon (LTPS) material, and accordingly, the transistor T2 may also be referred to as an LTPS transistor. On the basis, the display panel provided by the embodiment of the present application can be referred to as an LTPO display panel.

The LTPS transistor has the advantages of high mobility, quick charging and the like, and the advantages of the oxide transistor are combined, so that the display effect and the service life of the display panel can be effectively improved, and the use experience of a user is improved. Alternatively, the transistors described in the embodiments of the present application may be all Thin Film Transistors (TFTs). For example, the oxide transistor T1 may also be referred to as an oxide TFT.

Alternatively, as can be seen in connection with fig. 3, LTPS transistor T2 may include: the active layer P2, the third Gate metal layer Gate3 and the source-drain metal layer SD2 are sequentially stacked between the substrate 01 and the first Gate metal layer Gate1 along a direction away from the substrate 01, and the interlayer dielectric ILD1 is on a side away from the substrate 01. The source and drain metal layer SD2 may overlap the active layer P2 through a via hole K2 penetrating the active layer P2 and the layers therebetween. Also, the source-drain metal layer SD2 included in the LTPS transistor T2 may include a source portion S2 and a drain portion D2 which are spaced apart from each other, as in the oxide transistor T1.

Furthermore, as can also be seen with reference to fig. 3, in addition to including the above-described membrane layer, there may be included: the Gate insulating layer GI2 is located between the active layer P2 and the third Gate metal layer Gate3, and the Gate insulating layer GI3 is located between the third Gate metal layer Gate3 and the first Gate metal layer Gate1, so as to insulate the two adjacent conductive layers, and avoid signal crosstalk between the two adjacent conductive layers. And, may further include: and a protective layer B2 and a buffer (buffer) layer B3 which are located between the substrate 01 and the active layer P2 and are sequentially stacked in a direction away from the substrate 01. The protective layer B2 and the buffer layer B3 may be used to protect the upper and lower film layers.

However, in order to improve the characteristics of LTPS transistor T2 by including LTPS transistor T2, LTPS transistor T2 is often annealed (Anneal) after a via hole is opened in interlayer dielectric ILD 1. After annex, an oxide layer inevitably forms on the active layer P2 of LTPS transistor T2, and the oxide layer may cause a large contact resistance between the active layer P2 of LTPS transistor T2 and the source-drain metal layer SD 2. Therefore, after the Anneal, the oxide layer is usually etched by using a Buffered Oxide Etch (BOE) to remove the oxide layer, thereby improving the contact resistance between the active layer P2 and the source/drain metal layer SD 2. However, the etching process for removing the oxide layer may further cause Crack at the contact portion (i.e., at the slope angle) between the interlayer dielectric ILD1 and the second Gate metal layer Gate2, thereby causing an abnormal bright spot defect of the display panel. The abnormal phenomenon is particularly obvious on an interlayer dielectric ILD1 formed only by using a silicon oxide SiO material with poor compactness at present.

In the embodiment of the application, by adopting a lamination process, the interlayer dielectric ILD1 is set to include a double-layer insulating material layer (i.e., including ILD11 and ILD12) of a silicon oxide SiO material and a silicon nitride SiN material, thereby effectively and reliably preventing the contact portion between the interlayer dielectric ILD1 and the second Gate metal layer Gate2 from Crack, and ensuring that the factory yield of the display panel is good.

As an alternative implementation, referring to fig. 2 and 3, it can be seen that an orthographic projection of the gate insulating layer GI1 formed in the embodiment of the present application on the substrate 01 may cover an orthographic projection of the active layer P1 on the substrate 01.

As another alternative implementation manner, referring to the structure shown in fig. 4, an orthogonal projection of the Gate insulating layer GI1 formed in the embodiment of the present application on the substrate 01 may overlap an orthogonal projection of the first Gate metal layer Gate1 on the substrate 01. That is, the length of the Gate insulating layer GI1 may be the same as the length Lb of the first Gate metal layer Gate 1.

Currently, limited to the conductor process, in order to reliably make the active layer P1 conductive, the orthographic projection of the Gate insulating layer GI1 on the substrate 01 is usually overlapped with the orthographic projection of the second Gate metal layer Gate2 on the substrate 01, i.e. the Gate insulating layer GI1 is not disposed in the region except the region right below the second Gate metal layer Gate 2. However, since the material included in the interlayer dielectric ILD1 (particularly, the silicon nitride SiN material used in the embodiment of the present application) contains a large amount of hydrogen (H) ions, the H ions are easily diffused to the channel of the active layer P1 in addition to the position where the gate insulating layer GI1 is provided, and thus the stability of the characteristics of the oxide transistor T1 to be formed is deteriorated. In the embodiment of the application, the Gate insulating layer GI1 is arranged to cover the active layer P1 or overlap with the first Gate metal layer Gate1, that is, the Gate insulating layer GI1 in all regions right above the first Gate metal layer Gate1 is retained, so that H ions in the interlayer dielectric layer ILD1 can be effectively blocked, the H ions are prevented from diffusing to the channel region of the active layer P1 to affect the characteristics of the oxide transistor T1, and the manufactured oxide transistor T1 is further ensured to obtain more stable characteristics, that is, the characteristics of the oxide transistor T1 can be further improved.

In addition, on the basis that the Gate insulating layer GI1 is provided to cover the active layer P1, the step of the inclination angle between the interlayer dielectric ILD1 and the second Gate metal layer Gate2 can be improved, that is, the step is made smaller, thereby further improving the problem of Crack occurring at the contact portion between the interlayer dielectric ILD1 and the second Gate metal layer Gate 2. Furthermore, on the basis that the Gate insulating layer GI1 is provided to cover the active layer P1, as can be seen from comparing fig. 3 and fig. 4, when the second Gate metal layer Gate2 is formed by etching, the Gate insulating layer GI1 formed on the side of the active layer P1 away from the substrate 01 does not need to be etched again. Thus, the etching time can be reduced, and the etching uniformity can be ensured to be good. For example, on the basis of using a FICD (FICD) wet etching, the uniformity of the FICD can be ensured to be better.

Referring to fig. 4, a target portion of the active layer P1 may be dry-etched by plasma (plasma) formed of a dry etching gas on the basis of overlapping the Gate insulating layer GI1 with the first Gate metal layer Gate1 to make the target portion of the active layer P1 conductive. That is, the active layer P1 may be made conductive using a dry etching process.

For example, the dry etching gas may include: sulfur hexafluoride (SF6) gas or carbon tetrafluoride (CF4) gas. That is, in the embodiment of the present application, the target portion of the active layer P1 can be made conductive by dry etching plasma formed by dry etching gas such as SF6 or CF 4. Of course, the embodiment of the present application does not limit the dry etching gas.

However, since the dry etching gas generally has difficulty in penetrating the gate insulating layer GI1, in conjunction with fig. 2 and 3, on the basis that the gate insulating layer GI1 covers the active layer P1, a Doping (Doping) process may be used to dope ions into a target portion of the active layer P1 so as to make the target portion of the active layer P1 conductive.

Illustratively, the dopant ions may include boron ions B + or phosphorus ions P-. That is, in the embodiment of the present application, dopant ions such as B + or P-may be implanted into the target portion of the active layer P1 through the Doping process to make the target portion of the active layer P1 conductive. Of course, the embodiment of the present application does not limit the dopant ions.

Compared with the Doping process, the dry etching process has the advantages that the processing mode is simpler, the cost is lower, the Gate insulating layer GI1 is overlapped with the first Gate metal layer Gate1, and on the basis, the active layer P1 is made conductive by the dry etching process, so that H ions in the interlayer dielectric layer ILD1 can be effectively prevented from diffusing to the active layer P1, the process can be simplified, and the cost is reduced. In addition, during the Doping process, the Doping ions can be more or less diffused to the channel of the active layer P1, which leads to the shortening of the effective channel of the active layer P1, so that the effective channel of the active layer P1 can be prevented from being shortened by adopting the dry etching process, the manufactured oxide transistor T1 can obtain more stable characteristics, and the improvement of the resolution of the display panel can be facilitated. The resolution can be measured by the number of Pixels Per Inch (PPI), i.e., the PPI of the display panel can be improved.

It has been tested that when the active layer P1 is conducted by the Doping process, most of the Doping ions (e.g., B +) are implanted into the active layer P1 along the electric field direction and perpendicular to the surface of the active layer P1, but a small amount of the Doping ions laterally diffuse into the channel of the active layer P1, which results in a short effective channel length Leff of the active layer P1. In addition, when the LTPS transistor T2 is subjected to a high temperature annex, the doped ions will diffuse into the channel of the active layer P1 under the action of the high temperature, and further shorten the effective channel length Leff of the active layer P1, so that the characteristics of the manufactured oxide transistor T1 become unstable, and the improvement of the PPI of the display panel is not facilitated.

For example, still referring to fig. 2, the active layer P1 in the X region is generally conducted by the related art, and on the basis of the conduction process by the doting process, the effective channel length Leff of the second Gate metal layer Gate2 is reduced to: lt-2. delta.L. Here, Δ L is the length of the active layer P1 located in the X region minus the length of the active layer P1 located in the Y region, that is, the length of the active layer P1 located in the Z region. Since the active layer P1 located on the left and right sides of the first Gate metal layer Gate1 need to be made conductive so as to overlap the source portion S1 and the drain portion D1 included in the source-drain metal layer SD1, respectively, it is 2 Δ L. On this basis, it can also be determined that the target portions of the active layer P1 located on the left side and the right side of the first Gate metal layer Gate1 are both made conductive in the embodiments of the present application, and the following embodiments are not repeated.

In the embodiment of the present application, with reference to fig. 2, ions are doped into the active layer P1 located in the Y region only by using a Doping process, and ions are not doped into the active layer P1 located in the X region, that is, only the active layer P1 in the region other than the region right above the first Gate metal layer Gate1 is Doping-treated, so that the X region can be fully utilized as a buffer region, and the doped ions only slightly diffuse into the X region or do not diffuse into the X region. That is, the diffusion of the doped ions to the right under the second Gate metal layer Gate2, i.e., to the effective channel region, can be reliably prevented. Further, it is possible to secure that the effective channel length Leff of the oxide transistor T1 is equal to the length Lt of the second Gate metal layer Gate2, i.e., the effective channel length Leff of the oxide transistor T1 is Lt. Since Lt is greater than Lt-2 Δ L, it can be seen that on the basis of doting the active layer P1 in the region other than the region right above the first Gate metal layer Gate1, the effective channel length Leff can be ensured to be longer, so that the characteristics of the oxide transistor T1 can be more stable, and the PPI of the display panel can be improved.

Note that, in the case where the oxide transistor T1 is a double-Gate transistor, the first Gate metal layer Gate1 is a bottom Gate, and the second Gate metal layer Gate2 is a top Gate, the conductivity is made only to the active layer P1 located in the Y region, and the characteristics of the oxide transistor T1 are not affected.

Fig. 5 shows a flow chart of a method of forming a second gate metal layer on one side of a substrate. As shown in fig. 5, the method may include:

and 1011, forming a gate metal film on one side of the gate insulating layer far away from the substrate.

Alternatively, a deposition process may be used to form the gate metal film on the side of the gate insulating layer away from the substrate. For example, the deposition process may be: chemical Vapor Deposition (CVD) processes. For example, fig. 6 shows a gate metal film 02 formed on a side of the gate insulating layer GI1 away from the substrate 01.

Step 1012, forming a photoresist pattern on the side of the gate metal film away from the substrate.

Then, a photoresist pattern may be formed on the side of the gate metal thin film away from the substrate using a one-time patterning process. Illustratively, fig. 6 also shows a photoresist pattern 03 formed on the side of the gate metal film 02 away from the substrate 01. Also, as can be seen from fig. 6, an orthogonal projection of the formed photoresist pattern 03 on the substrate 01 overlaps an orthogonal projection of the first Gate metal layer Gate1 on the substrate 01.

As described in the above embodiments, the one-step patterning process may include: and sequentially performing gluing, exposure and development treatment. Optionally, the photoresist used in the embodiment of the present application may be a Photoresist (PR) photoresist, and the PR photoresist may be a positive photoresist or a negative photoresist. The mask used in the exposure process may be a half-tone (H/T) mask. That is, after the gate metal thin film 02 is formed, the H/T process may be continued. H/T reticles generally comprise: the light-transmitting device comprises a completely-transmitting area, a semi-transmitting area and a completely-transmitting area, wherein the part of the completely-transmitting area is completely exposed and removed, the part of the semi-transmitting area is partially exposed, and the part of the opaque area is not exposed. As can be seen from fig. 2 and 6, in the embodiment of the present invention, the Z region may correspond to the semi-transmissive region, the region where the second Gate metal layer Gate2 is located may correspond to the opaque region, and the remaining regions may correspond to the completely transmissive regions, so that the photoresist pattern 03 having the shape shown in fig. 6 can be reliably obtained.

Of course, in some other embodiments, a common metal mask may be used to process the applied photoresist to obtain the photoresist pattern 03 shown in fig. 6.

And 1013, taking the photoresist pattern as a protective layer, and performing first etching treatment on the gate metal film to obtain a gate metal pattern.

Then, the photoresist pattern may be used as a protective layer, and the gate metal film 03 may be subjected to a first etching process by using a dry etching method or a wet etching method, so as to obtain a gate metal pattern.

By way of example, fig. 7 shows the formed gate metal pattern 04. As can be seen from this figure, since the orthographic projection of the photoresist pattern 03 on the substrate 01 overlaps the orthographic projection of the first Gate metal layer Gate1 on the substrate 01, the orthographic projection of the formed Gate metal pattern 04 on the substrate 01 also overlaps the orthographic projection of the first Gate metal layer Gate1 on the substrate 01. That is, in the gate metal film 02, a portion protected by the photoresist pattern 03 is not etched, and a portion not protected by the photoresist pattern 03 (i.e., the gate metal film 02 without PR resist protection) is etched. Fig. 7 also refers to the schematically divided regions Z, Y and Z of fig. 2.

Step 1014, ashing the first portion of the photoresist pattern to remove the first portion and leave a second portion other than the first portion.

Then, the first portion of the photoresist pattern may be removed by Ashing using Ashing (Ashing) process, only the second portion remains, and the thickness of the ashed second portion is equal to the thickness of the original first portion.

Illustratively, fig. 8 shows the ashing process, and a second partial schematic view after the ashing process. As can be seen from fig. 7 and 8, the first portion of the photoresist pattern 03 is actually a portion located in the Z region, and correspondingly, the second portion is other than the first portion. After this step, the side of the second Gate metal layer Gate2 in the Z region may be left without PR paste protection.

And step 1015, taking the second part of the photoresist pattern as a protective layer, and performing second etching treatment on the gate metal pattern to obtain a second gate metal layer.

After the first portion of the photoresist pattern 03 is removed by ashing, the gate metal pattern 04 may be etched by using the remaining second portion of the photoresist pattern 03 as a protection layer and using dry etching or wet etching, so as to obtain a second gate metal layer. Note that the second portion of the photoresist pattern 03 needs to be stripped after the etching process.

For example, fig. 9 shows a schematic structural diagram of the formed second Gate metal layer Gate 2. Referring to fig. 9, after step 1014, the portion of the Gate metal pattern 04 without the protection of the PR paste may be etched, so as to obtain the desired second Gate metal layer Gate 2.

Note that the gate insulating layer GI1 shown in fig. 6 to 9 covers the active layer P1. For the structure that the Gate insulating layer GI1 only overlaps the first Gate metal layer Gate1, referring to another method flowchart shown in fig. 10, in an embodiment of the present invention, forming the Gate insulating layer may include:

and step 1016, before forming the gate metal film on the side of the gate insulating layer far away from the substrate, forming a gate insulating film on the side of the active layer far away from the substrate.

Alternatively, as in step 1011 above, a gate insulating film may be formed on the side of the active layer away from the substrate by a deposition process such as CVD. For example, fig. 11 shows a schematic structural view of the formed gate insulating film 05. As can be seen from a comparison between fig. 6 and fig. 11, the gate insulating film 05 formed here is the final gate insulating layer GI1, on the basis that the gate insulating layer GI1 covers the active layer P1.

And 1013, taking the photoresist pattern as a protective layer, and performing first etching treatment on the gate metal film and simultaneously performing first etching treatment on the gate insulating film to obtain the gate insulating layer.

Then, the first etching process may be performed on the gate insulating film by using the same etching process (e.g., wet etching or dry etching) while performing the first etching process on the gate metal film, so as to obtain the required gate insulating layer. For example, fig. 12 shows the gate insulating layer GI1 formed. Similarly, since the orthographic projection of the photoresist pattern 03 on the substrate 01 overlaps the orthographic projection of the first Gate metal layer Gate1 on the substrate 01, the orthographic projection of the formed Gate insulating layer GI1 on the substrate 01 also overlaps the orthographic projection of the first Gate metal layer Gate1 on the substrate 01, thereby effectively protecting the active layer P1 except for the target portion.

As can be seen from comparison between fig. 6 and 12, if the gate insulating layer GI1 covers the active layer P1, the gate insulating layer GI1 may be directly formed without performing the first etching process. If the Gate insulating layer GI1 only overlaps the first Gate metal layer Gate1, the Gate insulating film needs to be subjected to a first etching process. It can be further seen that, as described in the above embodiments, the etching time can be reduced and the etching uniformity (e.g., FICD uniformity) of the gate metal film 02 can be ensured to be better on the basis that the gate insulating layer GI1 covers the active layer P1.

For the structure in which the Gate insulating layer GI1 overlaps only the first Gate metal layer Gate1, steps 1014 and 1015 may be performed again after the Gate insulating layer GI1 is formed. Fig. 13 and fig. 14 also show structural diagrams corresponding to the subsequent execution of step 1014 and step 1015, respectively, on the basis of the structure.

It should be noted that, although the gate insulating layer GI1 is not formed by etching in the structure in which the gate insulating layer GI1 covers the active layer P1, since the gate insulating layer GI1 formed below the gate insulating layer GI1 is etched more or less in the process of etching the gate metal film 02, it is determined that, based on this structure, the gate insulating layer GI1 in the Y region and the gate metal film 02 are etched twice, and the gate insulating layer GI1 in the Z region is etched only once. Further, referring to fig. 9, the thickness of the Gate insulating layer GI1 located directly under the second Gate metal layer Gate2 is greater than the thickness of the Gate insulating layer GI1 located in the Z region and greater than the thickness of the Gate insulating layer GI1 located in the Y region.

In the embodiment of the present application, the target portion of the active layer P1 may be directly conducted after the first etching process is performed on the gate metal film 02. Since the gate insulating layer GI1 protects the active layer P1 except for the target portion on the side away from the substrate 01, it is possible to effectively ensure that only the target portion of the active layer P1 is subjected to the conductor forming process.

Also, in conjunction with the above-described embodiment, fig. 5 and 7, if the gate insulating layer GI1 covers the active layer P1, after the first etching process is performed on the gate metal film 02, ions may be doped into a target portion of the active layer using a doping process to make the target portion conductive. In other words, the active layer P1 located in the Y region may be doped with ions using a Doping process to conduct a target portion of the active layer P1. And, in conjunction with the above-described embodiment, fig. 10 and 12, if the Gate insulating layer GI1 overlaps the first Gate metal layer Gate1, after the first etching process is performed on the Gate metal thin film 02, a target portion of the active layer may be dry-etched by plasma formed of a dry etching gas to make the target portion of the active layer conductive. In other words, a dry etching process may be used to introduce a dry etching gas into the active layer P1 located in the Y region to conduct a target portion of the active layer P1. The step of conductimerizing is identified in fig. 5 and 12 as step 1017.

After the above step 1015, a deposition process may be further used to sequentially form a silicon oxide SiO material and a silicon nitride SiN material on one side of the substrate 01, so as to obtain an interlayer dielectric ILD1 comprising two insulating material layers. For example, the deposition process may be a Plasma Enhanced Chemical Vapor Deposition (PECVD) method. Then, a via penetrating through the interlayer dielectric ILD1 and the gate insulating layer GI1 may be formed by an etching process, and a source/drain metal may be formed on the interlayer dielectric ILD1 by a single patterning process. And finally, overlapping the source drain metal layer with the active layer through the via hole.

It should be noted that fig. 3 and 4 only schematically illustrate the interlayer dielectric ILD1, and do not represent that the interlayer dielectric ILD1 only includes one insulating material layer. That is, the interlayer dielectric ILD1 in the display panel shown in fig. 3 and 4 should also include two layers of insulating material as shown in fig. 2.

In summary, the embodiments of the present application provide a method for manufacturing a transistor in a display panel. In the method, after a first gate metal layer, an active layer, a gate insulating layer and a second gate metal layer are formed on one side of a substrate, a target part of the active layer can be subjected to conductor processing, then an interlayer dielectric layer and a source drain metal layer are formed, and the source drain metal layer is overlapped with the active layer subjected to conductor processing through a via hole penetrating through the interlayer dielectric layer and the gate insulating layer, so that the transistor is obtained. Wherein, because the interlayer fixing layer comprises at least two insulating material layers, the compactness and the etching resistance are better. Therefore, when the via hole is formed, the contact part of the interlayer dielectric layer and the second gate metal layer is prevented from being broken, and the problem of abnormal display of the display panel is avoided.

Fig. 15 is a schematic structural diagram of a display panel according to an embodiment of the present application. As shown in fig. 15, the display panel includes: a plurality of pixels P0, each pixel P0 including a transistor T1 fabricated using the method as shown in the previous figures.

Alternatively, the transistor T1 may be an oxide transistor. Of course, in some other embodiments, as shown in FIG. 3, each pixel P0 may also include a LTPS transistor T2. That is, the display panel provided in the embodiment of the present application may be an LTPO display panel.

Fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present application. As shown in fig. 16, the display device includes: a power supply assembly J1, and a display panel 00 as shown in fig. 15.

The power supply assembly J1 is connected to the display panel 00 and is used for supplying power to the display panel 00.

Optionally, the display device may be: any product or component with a display function, such as an LTPO display device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.

It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or there can be more than one intermediate layer or element. Like reference numerals refer to like elements throughout.

Also, the terminology used in the description of the embodiments section of the present application is for the purpose of explanation only for the embodiments of the present application and is not intended to be limiting of the present application. Unless otherwise defined, technical or scientific terms used in the embodiments of the present application should have the ordinary meaning as understood by those having ordinary skill in the art to which the present application belongs.

For example, the use of "first," "second," or "third" and similar terms in the description and claims of embodiments of the present application does not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another.

Likewise, "a plurality" means two or more unless expressly limited otherwise. The terms "a" or "an," and the like, also do not denote a limitation of quantity, but rather denote the presence of at least one.

The word "comprise" or "comprises", and the like, means that the element or item listed before "comprises" or "comprising" covers the element or item listed after "comprising" or "comprises" and its equivalents, and does not exclude other elements or items.

"upper", "lower", "left", or "right", etc. are used merely to indicate relative positional relationships, which may also change accordingly when the absolute position of the object being described changes. "connect" or "couple" refers to an electrical connection.

"and/or" means that three relationships may exist, e.g., A and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

The above description is intended to be exemplary only, and not to limit the present application, and any modifications, equivalents, improvements, etc. made within the spirit and scope of the present application are intended to be included therein.

Claims

1. A method of fabricating a transistor in a display panel, the method comprising:

forming a first gate metal layer, an active layer, a gate insulating layer and a second gate metal layer on one side of a substrate, wherein the orthographic projection of the first gate metal layer on the substrate and the orthographic projection of the second gate metal layer on the substrate are both positioned in the orthographic projection of the active layer on the substrate, and the orthographic projection of the second gate metal layer on the substrate is also positioned in the orthographic projection of the first gate metal layer on the substrate and in the orthographic projection of the gate insulating layer on the substrate;

conducting a target portion of the active layer, an orthographic projection of the target portion on the substrate not overlapping with an orthographic projection of the first gate metal layer on the substrate;

2. The method of claim 1, wherein forming a second gate metal layer on one side of the substrate comprises:

3. The method of claim 2, wherein the conductimerizing the target portion of the active layer comprises:

4. The method of claim 2 or 3, wherein an orthographic projection of the gate insulating layer on the substrate overlaps with an orthographic projection of the first gate metal layer on the substrate, and the gate insulating layer is formed on one side of the substrate, comprising:

5. The method of claim 4, wherein the conductimerizing the target portion of the active layer comprises: doping ions to a target portion of the active layer using a doping process to conduct the target portion of the active layer.

6. A method according to any one of claims 1 to 3, wherein an orthographic projection of the gate insulating layer on the substrate covers an orthographic projection of the active layer on the substrate;

7. The method of any of claims 1 to 3, wherein the interlayer dielectric layer comprises: two insulating material layers stacked in sequence in a direction away from the substrate;

among the two insulating layers, the material of the insulating material layer close to one side of the substrate comprises: silicon oxide, the material of the insulating material layer at the side far away from the substrate comprises: silicon nitride.

8. A method according to any of claims 1 to 3, wherein the material of the active layer comprises: an oxide material.

9. A display panel, comprising: a plurality of pixels, each comprising a transistor fabricated using the method of any one of claims 1 to 8.

10. A display device, characterized in that the display device comprises: a power supply component, and the display panel of claim 9;