CN114628347B - Semiconductor packaging structure and preparation method thereof - Google Patents

Semiconductor packaging structure and preparation method thereof Download PDF

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Publication number
CN114628347B
CN114628347B CN202210525536.XA CN202210525536A CN114628347B CN 114628347 B CN114628347 B CN 114628347B CN 202210525536 A CN202210525536 A CN 202210525536A CN 114628347 B CN114628347 B CN 114628347B
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recess
solder
electrode
groove
conductive base
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CN114628347A (en
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陈国栋
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Shandong Zhongqing Intelligent Technology Co ltd
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Shandong Zhongqing Intelligent Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/89—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/89—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L2224/81 - H01L2224/86
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention provides a semiconductor packaging structure and a preparation method thereof, and relates to the technical field of semiconductor packaging. The semiconductor packaging structure comprises an electric connector, the electric connector comprises a terminal part, a connecting part and a welding part which are sequentially connected, the welding part is of a rectangular structure and comprises a recess, the recess is of a square structure, one side of the welding part, which is far away from the connecting part, is provided with a bent skirt edge, the skirt edge and a first side wall of the recess form a groove, the first side wall is a through structure, and the through structure is communicated with the recess and the groove; the groove is internally provided with a first welding flux, and the electric connecting piece is electrically connected with the semiconductor chip through the first welding flux. The skirt edge of the groove can prevent the solder from overflowing outwards, so that the solder is separated, and the reliability of electric connection is ensured.

Description

Semiconductor packaging structure and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure and a preparation method thereof.
Background
Lead frame packages have been common package structures for semiconductor packages that require electrical leadout and chip carrying using the base island and electrode termination structures of the lead frame, while structural electrical connections are necessary that connect the electrodes of the chip and the electrode termination structures to achieve chip packaging. However, this structure requires two times of soldering for each electrical connector, i.e., electrode soldering of the electrical connector to the chip and electrical connection of the electrical connector to the electrode terminal structure, which is complicated, and, for solder-bonded electrical connectors, the bonding position is liable to cause a risk of cold solder, solder disconnection, or the like due to lack of bonding solder, or uneven bonding of the electrical connectors.
Disclosure of Invention
It is an object of the present invention to overcome the drawbacks of the prior art, and to provide a semiconductor package structure, which includes: a conductive base island comprising opposing first and second surfaces; a semiconductor chip including a first electrode on a lower surface thereof and a second electrode on an upper surface thereof, the first electrode being bonded to the first surface of the conductive base island; an electrical connector electrically coupled to the second electrode; and the sealing layer seals the conductive base island, the semiconductor chip and the electric connector, and the second surface of the conductive base island is flush with the lower surface of the sealing layer.
The electric connector comprises a terminal part, a connecting part and a welding part which are connected in sequence, the welding part is of a rectangular structure and comprises a recess, the recess is of a square structure, and one side, away from the connecting part, of the welding part is provided with a bent skirt edge. The skirt edge and the first side wall of the recess form a groove, the first side wall is a through structure, and the through structure is communicated with the recess and the groove; the groove is internally provided with first welding materials, and the electric connecting piece is electrically connected to the second electrode through the first welding materials.
According to an embodiment of the present invention, the recess includes a residual solder therein, the residual solder being of unitary construction with the first solder.
According to an embodiment of the present invention, a majority of the recess is located outside the semiconductor chip in a plan view.
According to the embodiment of the present invention, the lower surface of the terminal portion is flush with the lower surface of the sealing layer.
The invention also provides a preparation method of the semiconductor packaging structure according to the semiconductor packaging structure, which comprises the following steps:
s1, providing a conductive base island which comprises a first surface and a second surface which are opposite;
s2, providing a semiconductor chip, wherein the semiconductor chip comprises a first electrode on its lower surface and a second electrode on its upper surface, and the first electrode is bonded on the first surface of the conductive base island;
s3, providing an electric connector, wherein the electric connector comprises a terminal part, a connecting part and a welding part which are sequentially connected, the welding part is of a rectangular structure and comprises a recess, the recess is of a square structure, one side of the welding part, which is far away from the connecting part, is provided with a bent skirt edge, the skirt edge and a first side wall of the recess form a groove, the first side wall is a through structure, and the through structure is communicated with the recess and the groove; and pressing the welding part on the second electrode, wherein the groove is aligned with the second electrode;
s4, arranging a solder sheet in the recess, and carrying out hot pressing to enable the solder sheet to be melted to form first solder into the groove so as to realize the joint of the electric connector and the second electrode;
and S5, forming a sealing layer, wherein the sealing layer seals the conductive base island, the semiconductor chip and the electric connector, and the second surface of the conductive base island is flush with the lower surface of the sealing layer.
According to the embodiment of the invention, in S4, the hot pressing includes pressing the solder sheet with a pressing block, and heating to melt the solder sheet, and further to fill the melted solder into the groove through the through structure, so as to realize the soldering joint of the electrical connector and the second electrode.
According to the embodiment of the invention, the electric connecting piece is formed by one-time stamping through the stamping die, and the obtained electric connecting piece is of an integrally-molded structure.
According to the embodiment of the present invention, the electrical connection formed after step S3 has a majority of the recess located outside the semiconductor chip as viewed in plan.
According to the embodiment of the present invention, step S4 specifically includes: and locally heating and melting the solder sheet by using a hot-pressing head to realize liquidization of the solder sheet, and enabling the melted solder sheet to enter the groove through the through structure 16.
Compared with the prior art, the invention has the following beneficial effects:
the welding part of the electric connecting piece comprises a recess and a groove which are communicated with each other, wherein the recess faces upwards, the groove faces downwards, when the electric connecting piece is used, a solder piece is placed in the recess, the solder piece is melted into solder to enter the groove under the hot pressing state, and the direct electric connecting piece of the electric connecting piece and the upper electrode of the chip is realized. The solder part remains in the recess, the solder in the recess is used for later electric connection, and the recess can be used for a part for later electric connection with another terminal part.
The electric connecting piece is formed by one-time stamping through the stamping die, is of an integral structure, is simple in forming method, the welding part of the electric connecting piece can be easily aligned to the welding position, and more welding materials can be contained in the groove for electric connection. And the skirt edge of the groove can prevent the solder from overflowing outwards, so that the solder is separated, and the reliability of electric connection is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic view of an electrical connector of the present invention, wherein (a) is a cross-sectional view and (b) is a top view;
FIG. 2 is a schematic view of an electrical connector formed by a stamping die according to the present invention, (c) is a schematic view before stamping, and (d) is a schematic view after stamping;
FIG. 3 is a cross-sectional view of a semiconductor package structure according to the present invention;
FIG. 4 is a schematic illustration of a semiconductor chip bonded to a conductive base island;
FIG. 5 is a schematic view of the electrical connector engaging the semiconductor chip;
fig. 6 is a schematic view after the solder sheet is disposed;
FIG. 7 is a schematic view of a hot-pressed solder sheet;
fig. 8 is a schematic view after forming the sealing layer.
Description of reference numerals:
10. an electrical connection; 11. a terminal portion; 12. a connecting portion; 13. welding the part; 14. recessing; 15. a groove; 16. a through structure; 17. a skirt edge; 20. a semiconductor package structure; 21. a base island; 22. a semiconductor chip; 23. a first solder; 24. a first electrode; 25. a second solder; 26. residual solder; 27. a sealing layer; 28. a bottom surface; 29. a solder sheet; 30. stamping a die; 40. stamping parts; 50. and (4) a hot-pressing head.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention. In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The present embodiment provides a semiconductor package structure, which includes: a conductive base island comprising opposing first and second surfaces; a semiconductor chip including a first electrode on a lower surface thereof and a second electrode on an upper surface thereof, the first electrode being bonded to the first surface of the conductive base island; an electrical connector electrically coupled to the second electrode; the sealing layer seals the conductive base island, the semiconductor chip and the electric connecting piece, and the second surface of the conductive base island is flush with the lower surface of the sealing layer; the electric connector comprises a terminal part, a connecting part and a welding part which are sequentially connected, the welding part is of a rectangular structure and comprises a recess, the recess is of a square structure, one side, far away from the connecting part, of the welding part is provided with a bent skirt edge, the skirt edge and a first side wall of the recess form a groove, the first side wall is a through structure, and the through structure is communicated with the recess and the groove; the groove is internally provided with a first welding flux, and the electric connector is electrically connected to the second electrode through the first welding flux.
Referring first to fig. 1, the electric connector 10 for use according to the present invention includes a terminal portion 11, a connecting portion 12, and a soldering portion 13 which are integrally formed. The electrical connector 10 is a folded copper structure that is stamped and formed with a die. Wherein the terminal portion 11 is located at the bottom and the soldering portion 13 is located at the top, and the connecting portion 12 connects the terminal portion 11 and the soldering portion 13. The terminal portion 11 has a square structure and is used for electrical connection to the outside. The connecting portion 12 has an inclined structure, one end of which is joined to the terminal portion 11 and the other end of which is joined to one side of the soldering portion 13.
The welded portion 13 has a rectangular configuration in plan view, and the welded portion 13 has a recess 14, and the recess 14 is formed by pressing, and a through structure 16 is formed by pressing on one side wall of the recess 14. On one side of the welded portion 13, there is a skirt 17, the skirt 17 being formed by bending, and forming a groove 15 with the side wall of the recess 14. The recess 15 is open on both sides and the skirt 17 serves as a solder stop. The bottom of the skirt 17 is flush with the bottom of the recess 14.
In particular, as shown in fig. 1 (a), the recess 14 communicates with the groove 15 through a through structure 16 on the sidewall thereof, and in actual use of the electrical connector 10, the recess 14 is used for carrying solder sheets, and the groove 15 is used for accommodating solder to form an electrical connection. In addition, the recesses 14 of the present invention also serve as additional connection points to achieve electrical connection alignment with other connectors and to accommodate solder.
The electrical connector 10 is formed by mechanical stamping, as can be seen in particular in fig. 2. The stamping die 30 may include cutting blades on its stamping surface, one of which is used to cut off the stamping part 40, and the other of which is used to form the through structure 16. In addition, the stamping surface includes a protrusion, which correspondingly forms the recess 14.
Referring to fig. 2 (d), the electrical connector 10 may be directly formed by one-time stamping, and, in order to ensure the flushness of the bottom of the recess 14 and the bottom of the skirt 17, the recess bottom may be ground and roughened, and the roughened recess bottom (bottom surface) may improve the reliability of the soldering, ensuring solder spreading at the joint and contact with the subsequent sealing layer.
A semiconductor package structure 20 as an embodiment of the present invention may be seen in fig. 3, which includes at least an electrical connector 10, a base island 21, a semiconductor chip 22, and a sealing layer 27. The bottom surfaces of the base islands 21 and the bottom surface 28 of the sealing layer 27 are coplanar with the bottom surface of the terminal portion 11 of the electrical connector 10, i.e., the sealing layer 27 exposes the base islands 21 and the terminal portion 11 on the bottom surface 28. The material of the base island 21 may be copper, which is used as one of the terminals and functions as a function portion of the heat sink. The base island 21 has a stepped shape on its side to ensure bonding and sealability with the sealing layer 27.
Specifically, the method for forming the semiconductor packaging structure implemented by the invention comprises the following steps:
s1, providing a conductive base island which comprises a first surface and a second surface which are opposite;
s2, providing a semiconductor chip, wherein the semiconductor chip comprises a first electrode on the lower surface of the semiconductor chip and a second electrode on the upper surface of the semiconductor chip, and the first electrode is jointed on the first surface of the conductive base island;
s3, providing an electric connector, wherein the electric connector comprises a terminal part, a connecting part and a welding part which are sequentially connected, the welding part is of a rectangular structure and comprises a recess, the recess is of a square structure, one side of the welding part, which is far away from the connecting part, is provided with a bent skirt edge, the skirt edge and a first side wall of the recess form a groove, the first side wall is of a through structure, and the through structure is communicated with the recess and the groove; and pressing the welding part on the second electrode, wherein the groove is aligned with the second electrode;
s4, arranging a solder sheet in the recess, and carrying out hot pressing to enable the solder sheet to be melted to form first solder into the groove so as to realize the joint of the electric connector and the second electrode;
and S5, forming a sealing layer, wherein the sealing layer seals the conductive base island, the semiconductor chip and the electric connector, and the second surface of the conductive base island is flush with the lower surface of the sealing layer.
The semiconductor chip 22 may be a power chip, such as an IGBT, HBT, HEMT, and has electrodes on its top and bottom, including a bottom electrode 24 and a top electrode 23, wherein the number of the top electrodes 23 may be two. The lower electrode 24 is bonded to the upper surface of the base island 21 by a first solder 25, and the first solder 25 may be selected from a tin-lead solder, a gold-tin solder, and the like. Specific formation steps reference may be made to fig. 4, to which a reflow process may be applied.
Next, referring to fig. 5, the soldering portion 13 of the electrical connector 10 is pressed onto the upper electrode 23, wherein the bottom of the recess 14 and the bottom of the skirt 17 can simultaneously contact the upper surface of the semiconductor chip 22, and the groove 15 is aligned with the upper electrode 23. In this case, since most of the recess 14 is located outside the semiconductor chip 22 in plan view, the position of the recess 14 for connecting another terminal can be made to be a position which does not affect the solder electrical connection in the groove 15 when soldering is performed.
Next, referring to fig. 6, a solder sheet 29 is placed in the recess 14, and the solder sheet 29 may be formed of a low melting point solder, which has a sheet-like structure and is sized to fit into the recess 14.
Next, referring to fig. 7, the solder sheet 29 is liquefied by locally heating and melting the solder sheet 29 by the hot-pressing head 50 in the form of low-temperature hot pressing, wherein the temperature is approximately between 150 ℃ and 220 ℃. Due to the action of the pressure, the molten solder piece 29 becomes the second solder 26 entering the groove 15 through the through structure 16 while contacting the upper electrode 23 and the soldering portion 13, achieving electrical connection of the semiconductor chip 22 and the electrical connection member 10. In this step, the thermal head 50 may be a heating press block, and the local heating thereof may prevent the semiconductor chip 22 from being damaged due to over-high temperature, so as to ensure the reliability of the electrical connection and the packaging.
In this step, a part of solder remains in the recess 14, the remaining solder can be used as a soldering material for further terminals, and the recess 14 can ensure the holding amount of solder when connecting other terminals and can be used as an alignment member.
Finally, the sealing layer 27 is injection molded, and the sealing layer 27 may be formed by a conventional cured resin material, with the bottom surface of the sealing layer 27 being flush with the bottoms of the islands 21 and the terminal portions 11. Thus, the semiconductor package structure shown in fig. 8 is obtained.
The welding part of the electric connecting piece comprises a recess and a groove which are communicated with each other, wherein the recess faces upwards, the groove faces downwards, when the electric connecting piece is used, a solder piece is placed in the recess, the solder piece is melted into solder to enter the groove under the hot pressing state, and the direct electric connecting piece of the electric connecting piece and the upper electrode of the chip is realized. The solder part is left in the recess, the solder in the recess is used for later electric connection, and the recess can be used for a part for later electric connection with other terminal parts.
The electric connecting piece is formed by one-time stamping through the stamping die, is of an integral structure, is simple in forming method, the welding part of the electric connecting piece can be easily aligned to the welding position, and more welding materials can be contained in the groove for electric connection. And the skirt edge of the groove can prevent the solder from overflowing outwards, so that the solder is separated, and the reliability of electric connection is ensured.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (9)

1. A semiconductor package structure, comprising:
a conductive base island comprising opposing first and second surfaces;
a semiconductor chip including a first electrode on a lower surface thereof and a second electrode on an upper surface thereof, the first electrode being bonded to the first surface of the conductive base island;
an electrical connector electrically coupled to the second electrode;
the sealing layer seals the conductive base island, the semiconductor chip and the electric connecting piece, and the second surface of the conductive base island is flush with the lower surface of the sealing layer;
the electric connector is characterized by comprising a terminal part, a connecting part and a welding part which are sequentially connected, wherein the welding part is of a rectangular structure and comprises a recess, the recess is of a square structure, one side of the welding part, which is far away from the connecting part, is provided with a bent skirt edge, the skirt edge and a first side wall of the recess form a groove, the first side wall is a through structure, and the through structure is communicated with the recess and the groove; the groove is internally provided with first welding materials, and the electric connecting piece is electrically connected to the second electrode through the first welding materials.
2. The semiconductor package structure of claim 1,
the recess comprises residual solder, and the residual solder and the first solder are of an integral structure.
3. The semiconductor package structure of claim 1,
the most part of the recess is located outside the semiconductor chip in a plan view.
4. The semiconductor package structure of claim 1,
the lower surface of the terminal portion is flush with the lower surface of the sealing layer.
5. A preparation method of a semiconductor packaging structure is characterized by comprising the following steps:
s1, providing a conductive base island which comprises a first surface and a second surface which are opposite;
s2, providing a semiconductor chip, wherein the semiconductor chip comprises a first electrode on its lower surface and a second electrode on its upper surface, and the first electrode is bonded on the first surface of the conductive base island;
s3, providing an electric connector, wherein the electric connector comprises a terminal part, a connecting part and a welding part which are sequentially connected, the welding part is of a rectangular structure and comprises a recess, the recess is of a square structure, one side of the welding part, which is far away from the connecting part, is provided with a bent skirt edge, the skirt edge and a first side wall of the recess form a groove, the first side wall is a through structure, and the through structure is communicated with the recess and the groove; and pressing the welding part on the second electrode, wherein the groove is aligned with the second electrode;
s4, arranging a solder sheet in the recess, and carrying out hot pressing, so that the solder sheet is melted to form a first solder into the groove, and the electric connector is jointed with the second electrode;
and S5, forming a sealing layer, wherein the sealing layer seals the conductive base island, the semiconductor chip and the electric connector, and the second surface of the conductive base island is flush with the lower surface of the sealing layer.
6. The method of manufacturing a semiconductor package according to claim 5,
in S4, the hot pressing includes pressing the solder sheet with a pressing block and heating to melt the solder sheet, and further filling the melted solder into the groove through the through structure to achieve solder bonding of the electrical connector and the second electrode.
7. The method of manufacturing a semiconductor package according to claim 6,
the electric connecting piece is formed by one-time stamping through a stamping die, and the obtained electric connecting piece is of an integrally formed structure.
8. The method of manufacturing a semiconductor package according to claim 7,
the electrical connection formed after step S3 has a majority of the recesses located outside the semiconductor chip when viewed in plan.
9. The method of manufacturing a semiconductor package structure according to claim 7,
step S4 specifically includes: and locally heating and melting the solder sheet by using a hot-pressing head to realize liquidization of the solder sheet, and enabling the melted solder sheet to enter the groove through the through structure.
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