CN114628248A - Silicon carbide device and preparation method thereof - Google Patents
Silicon carbide device and preparation method thereof Download PDFInfo
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- CN114628248A CN114628248A CN202210526000.XA CN202210526000A CN114628248A CN 114628248 A CN114628248 A CN 114628248A CN 202210526000 A CN202210526000 A CN 202210526000A CN 114628248 A CN114628248 A CN 114628248A
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 120
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 120
- 238000002360 preparation method Methods 0.000 title abstract description 17
- 238000005468 ion implantation Methods 0.000 claims abstract description 253
- 238000000034 method Methods 0.000 claims abstract description 117
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000001259 photo etching Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims description 31
- 230000003647 oxidation Effects 0.000 claims description 24
- 238000007254 oxidation reaction Methods 0.000 claims description 24
- 238000004519 manufacturing process Methods 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 238000005224 laser annealing Methods 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 10
- 238000000206 photolithography Methods 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 7
- 230000004913 activation Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229920005668 polycarbonate resin Polymers 0.000 description 2
- 239000004431 polycarbonate resin Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention provides a silicon carbide device and a preparation method thereof, wherein the preparation method comprises the following steps: providing a base structure, the base structure comprising in sequence: the epitaxial structure comprises a silicon carbide substrate, a silicon carbide epitaxial layer, a first ion implantation layer of a first conduction type and a second ion implantation layer of a second conduction type; forming a first patterned mask structure on the second ion implantation layer by utilizing a photoetching process; forming a trench in the base structure using the first patterned mask structure; forming a gate structure in the trench; forming a second patterned mask structure on the second ion implantation layer by using the grid structure; forming an opening in the second ion implantation layer by using the second patterned mask structure, wherein the opening exposes a part of the first ion implantation layer; forming a contact structure in the exposed first ion implantation layer by using the opening; and forming a conductive layer connected to the contact structure; the first conductivity type and the second conductivity type are opposite conductivity types. Therefore, the problem of alignment precision difference between two photoetching processes can be avoided.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a silicon carbide device and a preparation method thereof.
Background
A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a Field-Effect Transistor that can be widely used in analog circuits and digital circuits. The silicon carbide material metal-oxide semiconductor field effect transistor (SiC MOSFET for short) has the characteristics of low on resistance, high switching speed, high temperature resistance and the like, and has great application advantages in the fields of high-voltage frequency conversion, new energy automobiles, rail transit and the like. In order to increase the current density of silicon carbide devices, effective control and shortening of the cell width of the devices has become one of the major research directions. When the cell width of the device is shortened, the photolithography alignment process has extremely high precision requirements, which brings great challenges to the process manufacturing. In particular, in the preparation of the existing silicon carbide device, the distance between the gate structure and the contact structure is controlled by two layers of masks (masks), and the alignment precision difference exists between the two photoetching processes, so that the problem of poor distance control is often caused.
Disclosure of Invention
The invention aims to provide a silicon carbide device and a preparation method thereof, and aims to solve the problem that in the prior art, the distance between a gate structure and a contact hole is controlled by two layers of light masks, and the alignment precision is different.
In order to solve the technical problem, the invention provides a preparation method of a silicon carbide device, which comprises the following steps: providing a base structure comprising: the silicon carbide epitaxial layer is positioned on the silicon carbide substrate, the first ion implantation layer of the first conductivity type is positioned on the silicon carbide epitaxial layer, and the second ion implantation layer of the second conductivity type is positioned on the first ion implantation layer; forming a first patterned mask structure on the second ion implantation layer by utilizing a photoetching process; forming a trench in the base structure using the first patterned mask structure; forming a gate structure in the trench; forming a second patterned mask structure on the second ion implantation layer by using the gate structure; forming an opening in the second ion implantation layer by using the second patterned mask structure, wherein part of the first ion implantation layer is exposed by the opening; forming a contact structure in the exposed first ion implantation layer by using the opening; and forming a conductive layer, the conductive layer being connected to the contact structure; wherein the first conductivity type and the second conductivity type are opposite conductivity types.
Optionally, in the preparation method of the silicon carbide device, forming a second patterned mask structure on the second ion implantation layer by using the gate structure includes: etching the first graphical mask structure, forming first side wall structures on two sides of the grid structure and exposing part of the second ion implantation layer; performing an oxidation process to form a first oxide layer on the surface of the second ion implantation layer and the surface of the grid structure; and etching the first oxide layer to form the second patterned mask structure, wherein the second patterned mask structure comprises the first side wall structure and the rest first oxide layer.
Optionally, in the preparation method of the silicon carbide device, forming a second patterned mask structure on the second ion implantation layer by using the gate structure includes: removing the first graphical mask structure; forming a second oxide layer covering the gate structure and the second ion implantation layer; and etching the second oxide layer to form second side wall structures on two sides of the gate structure, wherein the second side wall structures are used as the second patterning mask structures.
Optionally, in the preparation method of the silicon carbide device, after forming an opening in the second ion implantation layer by using the second patterned mask structure, the opening exposing a portion of the first ion implantation layer, and before forming a contact structure in the exposed first ion implantation layer by using the opening, the preparation method of the silicon carbide device further includes: performing an oxidation process to form a third oxide layer on the inner wall of the opening, the upper surface of the second ion injection layer and the surface of the gate structure; and etching to remove the third oxide layer on the surface of the first ion implantation layer.
Optionally, in the preparation method of the silicon carbide device, forming a second patterned mask structure on the second ion implantation layer by using the gate structure includes: removing the first graphical mask structure; forming a fourth oxide layer, wherein the fourth oxide layer covers the grid structure and the second ion implantation layer; etching the fourth oxide layer to form third side wall structures on two sides of the grid structure; performing an oxidation process to form a fifth oxide layer on the surface of the second ion implantation layer and the surface of the grid structure; and etching the fifth oxide layer to form the second patterned mask structure, wherein the second patterned mask structure comprises the third sidewall structure and the remaining fifth oxide layer.
Optionally, in the preparation method of the silicon carbide device, the first patterned mask structure is made of silicon oxide.
Optionally, in the method for manufacturing a silicon carbide device, forming a trench in the base structure using the first patterned mask structure includes: and performing an etching process on the substrate structure by taking the first patterned mask structure as a mask to form the groove, wherein the groove extends from the surface of the first patterned mask structure to the silicon carbide epitaxial layer.
Optionally, in the method for manufacturing a silicon carbide device, forming a gate structure in the trench includes: performing an ion implantation process on the bottom of the trench to form a third ion implantation layer of the first conductivity type at the bottom of the trench; forming a dielectric layer, wherein the dielectric layer covers the inner wall of the groove; and filling a polycrystalline silicon layer in the groove to form the grid structure.
Optionally, in the preparation method of the silicon carbide device, a ratio of an oxidation rate of the gate structure to an oxidation rate of the second ion implantation layer is between (3: 1) and (15: 1).
Optionally, in the method for manufacturing a silicon carbide device, forming a contact structure in the exposed first ion implantation layer by using the opening includes: performing an ion implantation process on the first ion implantation layer to form a fourth ion implantation layer; and performing a laser annealing process on the fourth ion implantation layer to form the contact structure.
Optionally, in the preparation method of the silicon carbide device, the process temperature for performing the laser annealing process is between 800 ℃ and 1200 ℃.
The present invention also provides a silicon carbide device comprising: a base structure, the base structure comprising: the silicon carbide epitaxial layer is positioned on the silicon carbide substrate, the first ion implantation layer of the first conductivity type is positioned on the silicon carbide epitaxial layer, and the second ion implantation layer of the second conductivity type is positioned on the first ion implantation layer; a gate structure formed in the base structure; a second patterned mask structure formed on the second ion implantation layer; a contact structure formed in the first ion implantation layer on the side of the second patterned mask structure; and a conductive layer connected to the contact structure; wherein the first conductivity type and the second conductivity type are opposite conductivity types.
In the silicon carbide device and the preparation method thereof provided by the invention, only one photoetching process is needed in the process of forming the gate structure and the contact structure, specifically, the groove is formed through one photoetching process to form the gate structure in the groove, and then the contact structure is formed through a self-alignment process. Therefore, the problem of alignment precision difference between two photoetching processes can be avoided. Further, the distance between the gate structure and the contact structure is also better controlled by forming the contact structure through a self-aligned process.
Drawings
Fig. 1 is a schematic flow chart of a method for producing a silicon carbide device according to an embodiment of the present invention.
Fig. 2 to 12 are schematic cross-sectional views of structures formed by performing the method of manufacturing a silicon carbide device according to the first embodiment of the present invention.
Fig. 13 to 25 are schematic cross-sectional views of structures formed by performing the method of manufacturing a silicon carbide device according to the second embodiment of the present invention.
Fig. 26 to 38 are schematic cross-sectional views of structures formed by performing the method of manufacturing a silicon carbide device according to the third embodiment of the present invention.
Wherein the reference numerals are as follows: 100-a base structure; 102-a silicon carbide epitaxial layer; 104-a first ion-implanted layer; 106-a second ion-implanted layer; 108-a first patterned mask structure; 110-a trench; 112-a third ion-implanted layer; 114-a dielectric layer; 116-a polysilicon layer; 118-a gate structure; 120-a second patterned mask structure; 122 — a first sidewall structure; 124-first oxide layer; 126-an opening; a 128-contact structure; 130-a conductive layer; 200-a base structure; 202-a silicon carbide epitaxial layer; 204-a first ion-implanted layer; 206-a second ion-implanted layer; 208-a first patterned mask structure; 210-a trench; 212-a third ion-implanted layer; 214-a dielectric layer; 216-a polysilicon layer; 218-a gate structure; 220-a second patterned mask structure; 222-a second oxide layer; 224-an opening; 225-a third oxide layer; a 226-contact structure; 228-a conductive layer; 300-a base structure; 302-a silicon carbide epitaxial layer; 304-a first ion implanted layer; 306-a second ion-implanted layer; 308-a first patterned mask structure; 310-a trench; 312-a third ion-implanted layer; 314-a dielectric layer; 316-a polysilicon layer; 318-gate structure; 320-a second patterned mask structure; 322-fourth oxide layer; 324-a third sidewall structure; 326-fifth oxide layer; 328-opening; 330-a contact structure; 332-conductive layer.
Detailed Description
The silicon carbide device and the method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific examples. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Unless otherwise defined in the specification, technical or scientific terms used herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which the invention belongs. The use of "first," "second," and similar terms in the description and in the claims does not indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "a number" means two or more. Unless otherwise indicated, "front", "rear", "lower" and/or "upper" and the like are for convenience of description and are not limited to one position or one spatial orientation. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
Fig. 1 is a schematic flow chart illustrating a method for fabricating a silicon carbide device according to an embodiment of the invention. As shown in fig. 1, the method for manufacturing the silicon carbide device includes: step S10: providing a base structure comprising: the silicon carbide epitaxial layer is positioned on the silicon carbide substrate, the first ion implantation layer of the first conductivity type is positioned on the silicon carbide epitaxial layer, and the second ion implantation layer of the second conductivity type is positioned on the first ion implantation layer; step S11: forming a first patterned mask structure on the second ion implantation layer by utilizing a photoetching process; step S12: forming a trench in the base structure using the first patterned mask structure; step S13: forming a gate structure in the trench; step S14: forming a second patterned mask structure on the second ion implantation layer by using the gate structure; step S15: forming an opening in the second ion implantation layer by using the second patterned mask structure, wherein the opening exposes part of the first ion implantation layer; step S16: forming a contact structure in the exposed first ion implantation layer by using the opening; and step S17: forming a conductive layer, wherein the conductive layer is connected with the contact structure; wherein the first conductivity type and the second conductivity type are opposite conductivity types.
In the embodiment of the invention, only one photolithography process is needed in the process of forming the gate structure and the contact structure, specifically, a trench is formed through one photolithography process to form the gate structure in the trench, and then the contact structure is formed through a self-aligned process. Therefore, the problem of alignment precision difference between two photoetching processes can be avoided. Further, the distance between the gate structure and the contact structure is also better controlled by forming the contact structure through a self-aligned process.
[ EXAMPLE I ].
Fig. 2 to 12 are schematic cross-sectional views illustrating structures formed by performing a method of fabricating a silicon carbide device according to a first embodiment of the invention.
As shown in fig. 2, in the embodiment of the present application, a substrate structure 100 is provided, where the substrate structure 100 includes: a silicon carbide substrate (not shown in the figure), a silicon carbide epitaxial layer 102 on the silicon carbide substrate, a first ion implantation layer 104 of a first conductivity type on the silicon carbide epitaxial layer 102, and a second ion implantation layer 106 of a second conductivity type on the first ion implantation layer 104. Referring to fig. 2, in the embodiment of the present application, a silicon carbide substrate (not shown) may be provided; then, an epitaxial process is performed on the silicon carbide substrate, thereby forming the silicon carbide epitaxial layer 102. Then, an ion implantation process is performed on the silicon carbide epitaxial layer 102 to obtain the first ion implantation layer 104, where P-type ion implantation is performed on the silicon carbide epitaxial layer 102 to obtain the P-type first ion implantation layer 104. Next, an ion implantation process is performed on the first ion implantation layer 104 to obtain the second ion implantation layer 106, where N-type heavy doping is performed on the first ion implantation layer 104 to obtain an N + -type second ion implantation layer 106. In other embodiments of the present application, the doping types of the first ion implantation layer 104 and the second ion implantation layer 106 may be opposite.
Next, as shown in fig. 3, a first patterned mask structure 108 is formed on the second ion implantation layer 106 by using a photolithography process. Here, the first patterned mask structure 108 is a hard mask layer, and may be a silicon oxide material. Specifically, a silicon oxide layer may be formed on the second ion implantation layer 106; next, an exposure process is performed on the silicon oxide layer by using a mask plate, and in this embodiment, an etching process is performed on the exposed silicon oxide layer to obtain the first patterned mask structure 108. The first patterned mask structure 108 exposes a portion of the second ion implantation layer 106.
Referring to fig. 4, a trench 110 is formed in the substrate structure 100 by using the first patterned mask structure 108. Specifically, the trench 110 is formed by etching the second ion implantation layer 106, the first ion implantation layer 104, and a part of the thickness of the silicon carbide epitaxial layer 102. Here, the trench 110 is in communication with an opening in the first patterned mask structure 108, whereby the trench 110 extends from the surface of the first patterned mask structure 108 into the silicon carbide epitaxial layer 102.
In the present embodiment, a gate structure is then formed in the trench 110. Specifically, as shown in fig. 5 and 6, first, an ion implantation process is performed on the bottom of the trench 110 to form a third ion implantation layer 112 of the first conductivity type at the bottom of the trench 110. Here, P-type ion implantation is performed on the bottom of the trench 110 to form a P-type third ion implantation layer 112 at the bottom of the trench 110. Next, a dielectric layer 114 is formed, wherein the dielectric layer 114 covers the inner wall of the trench 110 and extends to cover the surface of the first patterned mask structure 108. The material of the dielectric layer 114 may be the same as the material of the first patterned mask structure 108, such as silicon oxide. A polysilicon layer 116 is formed on the dielectric layer 114, and the polysilicon layer 116 fills the trench 110. With continued reference to fig. 6, the polysilicon layer 116 and the dielectric layer 114 on the first patterned mask structure 108 are then removed to form the gate structure 118 in the trench 110. Specifically, the polysilicon layer 116 and the dielectric layer 114 on the first patterned mask structure 108 may be removed by an etching process or a chemical mechanical polishing process.
Here, the silicon carbide epitaxial layer 102 between the first ion implantation layer 104 and the third ion implantation layer 112 may form a depletion region, so that the performance of the formed silicon carbide device may be improved.
As shown in fig. 7 to 9, in the embodiment of the present application, a second patterned mask structure 120 is formed on the second ion implantation layer 106 by using the gate structure 118.
First, referring to fig. 7, the first patterned mask structure 108 is etched, and first sidewall structures 122 are formed on two sides of the gate structure 118 and expose a portion of the second ion implantation layer 106. Here, the first patterned mask structure 108 may be etched by a dry etching process with an inclined angle, so as to form a first sidewall structure 122 with an inclined surface on two sides of the gate structure 118 and expose a portion of the second ion implantation layer 106.
Next, as shown in fig. 8, an oxidation process is performed to form a first oxide layer 124 on the exposed surface of the second ion implantation layer 106 and the surface of the gate structure 118. In the present embodiment, the portion of the gate structure 118 above the surface of the two ion implantation layers 106 is oxidized to be a portion of the first oxide layer 124. Wherein a ratio of an oxidation rate of the gate structure 118 to an oxidation rate of the second ion implantation layer 106 is between (3: 1) and (15: 1), for example, the ratio of the oxidation rate of the gate structure 118 to the oxidation rate of the second ion implantation layer 106 is 7: 1; 12:1, etc. Thus, the oxidation rate of the gate structure 118 will be much faster than the oxidation rate of the second ion implantation layer 106, so that the thickness of the first oxide layer 124 on the gate structure 118 will be much larger than the thickness of the first oxide layer 124 on the second ion implantation layer 106. In an embodiment of the application, the thickness of the first oxide layer 124 on the gate structure 118 is between 3000A-10000A, and the thickness of the first oxide layer 124 on the second ion implanted layer 106 is 200A-2000A.
As shown in fig. 9, the first oxide layer 124 is then etched to form the second patterned mask structure 120. Specifically, the first oxide layer 124 may be etched by a vertical dry etching process. Here, the etching is stopped to expose the second ion implantation layer 106. Since the thickness of the first oxide layer 124 on the second ion implantation layer 106 is relatively thin, a partial thickness of the first oxide layer 124 still remains on the gate structure 118 when the second ion implantation layer 106 is etched to expose the first oxide layer 124. The remaining first oxide layer 124 and the first sidewall structure 122 serve as the second patterned mask structure 120. The gate structure 118 is utilized to form the first sidewall structure 122 and the first oxide layer 124 with a height difference, thereby forming the second patterned mask structure 120.
As shown in fig. 10, an opening 126 is formed in the second ion implantation layer 106 by using the second patterned mask structure 120, and the opening 126 exposes a portion of the first ion implantation layer 104. Specifically, with the second patterned mask structure 120 as a mask, an etching process is performed on the second ion implantation layer 106 to form the opening 126 in the second ion implantation layer 106, where the opening 126 extends from the surface of the second ion implantation layer 106 to the surface of the first ion implantation layer 104, so as to expose the first ion implantation layer 104.
In the present embodiment, next, as shown in fig. 11, a contact structure 128 is formed in the exposed first ion implantation layer 104 by using the opening 126. Specifically, an ion implantation process is performed on the first ion implantation layer 104 to form a fourth ion implantation layer (not shown) of the first conductivity type, where the first conductivity type is P-type. The fourth ion implantation layer has a higher ion implantation concentration with respect to the first ion implantation layer 104 of the first conductivity type, where a fourth ion implantation layer of a P + -type is formed. Then, a laser annealing process is performed on the fourth ion implantation layer to form the contact structure 128. Preferably, the process temperature for performing the laser annealing process is between 800 ℃ and 1200 ℃. The laser annealing process is adopted instead of the conventional high-temperature furnace tube annealing process, so that the impurity activation can be realized at a lower temperature, and the quality and the reliability of the formed silicon carbide device are improved.
Referring to fig. 12, in the embodiment of the present application, a conductive layer 130 is formed, and the conductive layer 130 is connected to the contact structure 128. Specifically, the conductive layer 130 may be formed by depositing a metal layer.
Accordingly, embodiments of the present application also provide a silicon carbide device, including: a base structure 100, said base structure 100 comprising: a silicon carbide substrate (not shown in the figure), a silicon carbide epitaxial layer 102 on the silicon carbide substrate, a first ion implantation layer 104 of a first conductivity type on the silicon carbide epitaxial layer 102, and a second ion implantation layer 106 of a second conductivity type on the first ion implantation layer 104; a gate structure 118 formed in the base structure 100; a second patterned mask structure 120 formed on the second ion implantation layer 106; a contact structure 128 formed in the first ion implantation layer 104 on the second patterned mask structure 120 side; and a conductive layer 130 connected to the contact structure 128; wherein the first conductivity type and the second conductivity type have opposite conductivity types, i.e., one of the two is a P-type conductivity type and the other is an N-type conductivity type.
[ EXAMPLE II ] A method for producing a polycarbonate resin composition.
Please refer to fig. 13-25, which are schematic cross-sectional views illustrating structures formed by performing a method of fabricating a silicon carbide device according to a second embodiment of the present invention.
As shown in fig. 13, in the embodiment of the present application, a base structure 200 is provided, where the base structure 200 includes: a silicon carbide substrate (not shown), a silicon carbide epitaxial layer 202 on the silicon carbide substrate, a first ion implantation layer 204 of a first conductivity type on the silicon carbide epitaxial layer 202, and a second ion implantation layer 206 of a second conductivity type on the first ion implantation layer 204. Referring to fig. 13, in the embodiment of the present application, a silicon carbide substrate (not shown) may be provided; then, an epitaxial process is performed on the silicon carbide substrate, thereby forming the silicon carbide epitaxial layer 202. Then, an ion implantation process is performed on the silicon carbide epitaxial layer 202 to obtain the first ion implantation layer 204, where P-type ion implantation is performed on the silicon carbide epitaxial layer 202 to obtain the P-type first ion implantation layer 204. Then, an ion implantation process is performed on the first ion implantation layer 204 to obtain the second ion implantation layer 206, where N-type heavy doping is performed on the first ion implantation layer 204 to obtain an N + -type second ion implantation layer 206. In other embodiments of the present application, the doping types of the first ion implantation layer 204 and the second ion implantation layer 206 may also be opposite.
Next, as shown in fig. 14, a first patterned mask structure 208 is formed on the second ion implantation layer 206 by using a photolithography process. Here, the first patterned mask structure 208 is a hard mask layer, and may be a silicon oxide material. Specifically, a silicon oxide layer may be formed on the second ion implantation layer 206; next, an exposure process is performed on the silicon oxide layer by using a mask plate, and in the embodiment of the present application, an etching process is performed on the exposed silicon oxide layer to obtain the first patterned mask structure 208. The first patterned mask structure 208 exposes a portion of the second ion implantation layer 206.
Referring to fig. 15, next, a trench 210 is formed in the substrate structure 200 by using the first patterned mask structure 208. Specifically, the trenches 210 are formed by etching the second ion implantation layer 206, the first ion implantation layer 204, and a portion of the thickness of the silicon carbide epitaxial layer 202. Here, the trench 210 communicates with an opening in the first patterned mask structure 208, whereby the trench 210 extends from the surface of the first patterned mask structure 208 into the silicon carbide epitaxial layer 202.
In the present embodiment, a gate structure is then formed in the trench 210. Specifically, as shown in fig. 16 and 17, first, an ion implantation process is performed on the bottom of the trench 210 to form a third ion implantation layer 212 of the first conductivity type on the bottom of the trench 210. Here, P-type ion implantation is performed on the bottom of the trench 210 to form a P-type third ion implantation layer 212 at the bottom of the trench 210. Next, a dielectric layer 214 is formed, wherein the dielectric layer 214 covers the inner wall of the trench 210 and extends to cover the surface of the first patterned mask structure 208. The material of the dielectric layer 214 may be the same as the material of the first patterned mask structure 208, such as silicon oxide. A polysilicon layer 216 is formed on the dielectric layer 214, and the polysilicon layer 216 fills the trench 210. With continued reference to fig. 17, the polysilicon layer 216 and the dielectric layer 214 on the first patterned mask structure 208 are then removed to form the gate structure 218 in the trench 210. Specifically, the polysilicon layer 216 and the dielectric layer 214 on the first patterned mask structure 208 may be removed by an etching process or a chemical mechanical polishing process.
Here, the silicon carbide epitaxial layer 202 between the first ion implantation layer 204 and the third ion implantation layer 212 may form a depletion region, so that the performance of the formed silicon carbide device may be improved.
As shown in fig. 18 to 20, in the present embodiment, a second patterned mask structure 220 is formed on the second ion implantation layer 206 by using the gate structure 218.
Specifically, referring to fig. 18, the first patterned mask structure 208 is removed to expose the second ion implantation layer 206.
Next, as shown in fig. 19, a second oxide layer 222 is formed, wherein the second oxide layer 222 covers the gate structure 218 and the second ion implantation layer 206. Here, the second oxide layer 222 may be formed through a deposition process.
Next, as shown in fig. 20, the second oxide layer 222 is etched to form a second sidewall structure on two sides of the gate structure 218, and the second sidewall structure is used as the second patterned mask structure 220. The second sidewall structure is formed using the gate structure 218, thereby forming the second patterned mask structure 220. Here, the second oxide layer 222 may be etched by a vertical dry etching process to form the second patterned mask structure 220 having a square shape, so that the distance between the gate structure 218 and a subsequently formed contact structure can be better controlled.
Next, as shown in fig. 21, an opening 224 is formed in the second ion implantation layer 206 by using the second patterned mask structure 220, wherein the opening 224 exposes a portion of the first ion implantation layer 204. Specifically, with the second patterned mask structure 220 as a mask, an etching process is performed on the second ion implantation layer 206 to form the opening 224 in the second ion implantation layer 206, where the opening 224 extends from the surface of the second ion implantation layer 206 to the surface of the first ion implantation layer 204, so as to expose the first ion implantation layer 204.
As shown in fig. 22, in the present embodiment, an oxidation process is performed to form a third oxide layer 225 on the surface of the first ion implantation layer 204, the side surfaces and the upper surface of the second ion implantation layer 206, and the surface of the gate structure 218, i.e., a third oxide layer 225 is formed on the inner wall of the opening 224, the upper surface of the second ion implantation layer 206, and the surface of the gate structure 218. Here, the third oxide layer 225 and the second patterned mask structure 220 (i.e., the second sidewall structure) formed by etching the second oxide layer 222 are both made of silicon oxide and are connected together, and no distinction is made between fig. 22 and fig. 25 in this application.
Next, as shown in fig. 23, the third oxide layer 225 on the surface of the first ion implantation layer 204 is etched and removed to expose the first ion implantation layer 204, in this embodiment, the third oxide layer 225 on the side of the second ion implantation layer 206 is also removed. Specifically, a wet or dry etching process may be used to remove the third oxide layer 225 on the inner wall of the opening 224. Here, an isotropic etching process may be adopted to remove the third oxide layer 225 on the inner wall of the opening 224, and at this time, a wet etching process may be adopted or etching parameters of a dry etching process may be adjusted to remove the third oxide layer 225 on the inner wall of the opening 224. In other embodiments of the present application, only the third oxide layer 225 on the surface of the first ion implantation layer 204 may be removed to expose the first ion implantation layer 204.
In the present embodiment, next, as shown in fig. 24, a contact structure 226 is formed in the exposed first ion implantation layer 204 by using the opening 224. Specifically, an ion implantation process is performed on the first ion implantation layer 204 to form a fourth ion implantation layer (not shown) of the first conductivity type, where the first conductivity type is P-type. The fourth ion implantation layer has a higher ion implantation concentration with respect to the first ion implantation layer 204 of the first conductivity type, where a fourth ion implantation layer of a P + -type is formed. Then, a laser annealing process is performed on the fourth ion implantation layer to form the contact structure 226. Preferably, the process temperature for performing the laser annealing process is between 800 ℃ and 1200 ℃. The laser annealing process is adopted instead of the conventional high-temperature furnace tube annealing process, so that the impurity activation can be realized at a lower temperature, and the quality and the reliability of the formed silicon carbide device are improved.
Referring to fig. 25, in the present embodiment, a conductive layer 228 is formed, and the conductive layer 228 is connected to the contact structure 226. Specifically, the conductive layer 228 can be formed by depositing a metal layer.
Accordingly, embodiments of the present application also provide a silicon carbide device, including: a base structure 200, said base structure 200 comprising: a silicon carbide substrate (not shown in the figure), a silicon carbide epitaxial layer 202 on the silicon carbide substrate, a first ion implantation layer 204 of a first conductivity type on the silicon carbide epitaxial layer 202, and a second ion implantation layer 206 of a second conductivity type on the first ion implantation layer 204; a gate structure 218 formed in the base structure 200; a second patterned mask structure 220 formed on the second ion implantation layer 206; a contact structure 226 formed in the first ion implantation layer 204 on the side of the second patterned mask structure 220; and a conductive layer 228 connected to the contact structure 226; wherein the first conductivity type and the second conductivity type have opposite conductivity types, i.e., one of the two is a P-type conductivity type and the other is an N-type conductivity type.
[ EXAMPLE III ] A method for producing a polycarbonate resin composition.
Please refer to fig. 26-38, which are cross-sectional views illustrating structures formed by performing a method of fabricating a silicon carbide device according to a third embodiment of the present invention.
As shown in fig. 26, in the present embodiment, a base structure 300 is provided, the base structure 300 including: a silicon carbide substrate (not shown), a silicon carbide epitaxial layer 302 on the silicon carbide substrate, a first ion implantation layer 304 of a first conductivity type on the silicon carbide epitaxial layer 302, and a second ion implantation layer 306 of a second conductivity type on the first ion implantation layer 304. Referring to fig. 26, in the embodiment of the present application, a silicon carbide substrate (not shown) may be provided; then, an epitaxial process is performed on the silicon carbide substrate, thereby forming the silicon carbide epitaxial layer 302. Then, an ion implantation process is performed on the silicon carbide epitaxial layer 302 to obtain the first ion implantation layer 304, where P-type ion implantation is performed on the silicon carbide epitaxial layer 302 to obtain the P-type first ion implantation layer 304. Next, an ion implantation process is performed on the first ion implantation layer 304 to obtain the second ion implantation layer 306, wherein N-type heavy doping is performed on the first ion implantation layer 304 to obtain an N + -type second ion implantation layer 306. In other embodiments of the present application, the doping types of the first ion implantation layer 304 and the second ion implantation layer 306 may be opposite.
Next, as shown in fig. 27, a first patterned mask structure 308 is formed on the second ion implantation layer 306 by using a photolithography process. Here, the first patterned mask structure 308 is a hard mask layer, and may be specifically made of a silicon oxide material. Specifically, a silicon oxide layer may be formed on the second ion implantation layer 306; next, an exposure process is performed on the silicon oxide layer by using a mask plate, and in this embodiment, an etching process is performed on the exposed silicon oxide layer to obtain the first patterned mask structure 308. The first patterned mask structure 308 exposes a portion of the second ion implantation layer 306.
Referring to fig. 28, a trench 310 is formed in the substrate structure 300 by using the first patterned mask structure 308. Specifically, the trench 310 is formed by etching the second ion implantation layer 306, the first ion implantation layer 304, and a partial thickness of the silicon carbide epitaxial layer 302. Here, the trench 310 communicates with an opening in the first patterned mask structure 308, whereby the trench 310 extends from the surface of the first patterned mask structure 308 into the silicon carbide epitaxial layer 302.
In the present embodiment, a gate structure is then formed in the trench 310. Specifically, as shown in fig. 29 and 30, first, an ion implantation process is performed on the bottom of the trench 310 to form a third ion implantation layer 312 of the first conductivity type at the bottom of the trench 310. Here, P-type ion implantation is performed on the bottom of the trench 310 to form a third ion implantation layer 312 of P-type on the bottom of the trench 310. Next, a dielectric layer 314 is formed, wherein the dielectric layer 314 covers the inner wall of the trench 310 and extends to cover the surface of the first patterned mask structure 308. The material of the dielectric layer 314 may be the same as the material of the first patterned mask structure 308, such as silicon oxide. A polysilicon layer 316 is formed on the dielectric layer 314, and the polysilicon layer 316 fills the trench 310. With continued reference to fig. 30, the polysilicon layer 316 and the dielectric layer 314 on the first patterned mask structure 308 are then removed to form the gate structure 318 in the trench 310. Specifically, the polysilicon layer 316 and the dielectric layer 314 on the first patterned mask structure 308 may be removed by an etching process or a chemical mechanical polishing process.
Here, the silicon carbide epitaxial layer 302 between the first ion implantation layer 304 and the third ion implantation layer 312 may form a depletion region, so that the performance of the formed silicon carbide device may be improved.
As shown in fig. 31 to 35, in the present embodiment, a second patterned mask structure 320 is formed on the second ion implantation layer 306 by using the gate structure 318.
Specifically, referring to fig. 31, the first patterned mask structure 308 is removed to expose the second ion implantation layer 306.
Next, as shown in fig. 32, a fourth oxide layer 322 is formed, wherein the fourth oxide layer 322 covers the gate structure 318 and the second ion implantation layer 306. Here, the fourth oxide layer 322 may be formed through a deposition process.
Next, as shown in fig. 33, the fourth oxide layer 322 is etched to form third sidewall structures 324 on two sides of the gate structure 318, and the third sidewall structures 324 expose a portion of the second ion implantation layer 306. Here, the fourth oxide layer 322 may be etched through a vertical dry etching process to form the second patterned mask structure 320 having a square shape, so that the distance between the gate structure 318 and a subsequently formed contact structure can be better controlled.
Further, as shown in fig. 34, in the present embodiment, an oxidation process is performed to form a fifth oxide layer 326 on the exposed surface of the second ion implantation layer 306 and the surface of the gate structure 318. In the present embodiment, the portion of the gate structure 318 above the surface of the two ion-implanted layers 306 is oxidized to be a portion of the fifth oxide layer 326. Wherein a ratio of an oxidation rate of the gate structure 318 to an oxidation rate of the second ion implantation layer 306 is between (3: 1) and (15: 1), for example, the ratio of the oxidation rate of the gate structure 318 to the oxidation rate of the second ion implantation layer 306 is 7:1, 10: 1 or 12:1, etc. Thus, the oxidation rate of the gate structure 318 is much faster than that of the second ion implantation layer 306, so that the thickness of the fifth oxide layer 326 on the gate structure 318 is much larger than that of the fifth oxide layer 326 on the second ion implantation layer 306. In an embodiment of the application, the thickness of the fifth oxide layer 326 on the gate structure 318 is between 3000A-10000A, and the thickness of the fifth oxide layer 326 on the second ion implanted layer 306 is 200A-2000A.
In this embodiment, as shown in fig. 35, the fifth oxide layer 326 is then etched to form the second patterned mask structure 320, and the second patterned mask structure 320 includes the third sidewall structure 324 and the remaining fifth oxide layer 326. Specifically, the fifth oxide layer 326 may be etched by a vertical dry etching process. Here, the etching is stopped to expose the second ion implantation layer 306. Since the thickness of the fifth oxide layer 326 on the second ion implantation layer 306 is relatively thin, when the second ion implantation layer 306 is etched to expose the second ion implantation layer 306, a partial thickness of the fifth oxide layer 326 still remains on the gate structure 318. The remaining fifth oxide layer 326 and the third sidewall structure 324 are used as the second patterned mask structure 320. The third sidewall structure 324 is formed by using the gate structure 318, and the second patterned mask structure 320 is formed by making a height difference in the fifth oxide layer 326.
Next, as shown in fig. 36, an opening 328 is formed in the second ion implantation layer 306 by using the second patterned mask structure 320, wherein the opening 328 exposes a portion of the first ion implantation layer 304. Specifically, with the second patterned mask structure 320 as a mask, an etching process is performed on the second ion implantation layer 306 to form the opening 328 in the second ion implantation layer 306, where the opening 328 extends from the surface of the second ion implantation layer 306 to the surface of the first ion implantation layer 304, so as to expose the first ion implantation layer 304.
In the present embodiment, next, as shown in fig. 37, a contact structure 330 is formed in the exposed first ion implantation layer 304 by using the opening 328. Specifically, an ion implantation process is performed on the first ion implantation layer 304 to form a fourth ion implantation layer (not shown) of the first conductivity type, where the first conductivity type is P-type. The fourth ion implantation layer has a higher ion implantation concentration with respect to the first ion implantation layer 304 of the first conductivity type, where a fourth ion implantation layer of a P + -type is formed. Then, a laser annealing process is performed on the fourth ion implantation layer to form the contact structure 330. Preferably, the process temperature for performing the laser annealing process is between 800 ℃ and 1200 ℃. The laser annealing process is adopted instead of the conventional high-temperature furnace tube annealing process, so that the impurity activation can be realized at a lower temperature, and the quality and the reliability of the formed silicon carbide device are improved.
Referring to fig. 38, in the embodiment of the present application, a conductive layer 332 is formed, and the conductive layer 332 is connected to the contact structure 330. Specifically, the conductive layer 332 may be formed by depositing a metal layer.
Accordingly, embodiments of the present application also provide a silicon carbide device, including: a base structure 300, said base structure 300 comprising: a silicon carbide substrate (not shown in the figure), a silicon carbide epitaxial layer 302 on the silicon carbide substrate, a first ion implantation layer 304 of a first conductivity type on the silicon carbide epitaxial layer 302, and a second ion implantation layer 306 of a second conductivity type on the first ion implantation layer 304; a gate structure 318 formed in the base structure 300; a second patterned mask structure 320 formed on the second ion implantation layer 306; a contact structure 330 formed in the first ion implantation layer 304 at the side of the second patterned mask structure 320; and a conductive layer 332 connected to the contact structure 330; wherein the first conductivity type and the second conductivity type have opposite conductivity types, i.e., one of the two is a P-type conductivity type and the other is an N-type conductivity type.
In summary, in the silicon carbide device and the method for manufacturing the same provided by the embodiment of the present application, only one photolithography process is required in the process of forming the gate structure and the contact structure, specifically, the trench is formed by one photolithography process to form the gate structure in the trench, and then the contact structure is formed by a self-aligned process. Therefore, the problem of alignment precision difference between two photoetching processes can be avoided. Further, the distance between the gate structure and the contact structure is also better controlled by forming the contact structure through a self-aligned process.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (12)
1. A method for manufacturing a silicon carbide device, the method comprising:
providing a base structure comprising: the silicon carbide epitaxial layer is positioned on the silicon carbide substrate, the first ion implantation layer of the first conductivity type is positioned on the silicon carbide epitaxial layer, and the second ion implantation layer of the second conductivity type is positioned on the first ion implantation layer;
forming a first patterned mask structure on the second ion implantation layer by utilizing a photoetching process;
forming a trench in the base structure using the first patterned mask structure;
forming a gate structure in the trench;
forming a second patterned mask structure on the second ion implantation layer by using the gate structure;
forming an opening in the second ion implantation layer by using the second patterned mask structure, wherein part of the first ion implantation layer is exposed by the opening;
forming a contact structure in the exposed first ion implantation layer by using the opening; and
forming a conductive layer connected to the contact structure;
wherein the first conductivity type and the second conductivity type are opposite conductivity types.
2. The method of fabricating a silicon carbide device according to claim 1, wherein forming a second patterned mask structure on the second ion implantation layer using the gate structure comprises:
etching the first graphical mask structure, forming first side wall structures on two sides of the grid structure and exposing part of the second ion implantation layer;
performing an oxidation process to form a first oxide layer on the surface of the second ion implantation layer and the surface of the grid structure; and
and etching the first oxide layer to form the second patterned mask structure, wherein the second patterned mask structure comprises the first side wall structure and the rest first oxide layer.
3. The method of fabricating a silicon carbide device according to claim 1, wherein forming a second patterned mask structure on the second ion implantation layer using the gate structure comprises:
removing the first graphical mask structure;
forming a second oxide layer covering the gate structure and the second ion implantation layer; and
and etching the second oxide layer to form second side wall structures on two sides of the grid structure, wherein the second side wall structures are used as the second patterning mask structures.
4. The method of claim 3, wherein after forming an opening in the second ion implantation layer using the second patterned mask structure, the opening exposing a portion of the first ion implantation layer, and prior to forming a contact structure in the exposed first ion implantation layer using the opening, the method further comprises:
performing an oxidation process to form a third oxide layer on the inner wall of the opening, the upper surface of the second ion injection layer and the surface of the gate structure; and
and etching to remove the third oxide layer on the surface of the first ion implantation layer.
5. The method of fabricating a silicon carbide device according to claim 1, wherein forming a second patterned mask structure on the second ion implantation layer using the gate structure comprises:
removing the first graphical mask structure;
forming a fourth oxide layer, wherein the fourth oxide layer covers the grid structure and the second ion implantation layer;
etching the fourth oxide layer to form a third side wall structure on two sides of the grid structure;
performing an oxidation process to form a fifth oxide layer on the surface of the second ion implantation layer and the surface of the grid structure; and
and etching the fifth oxide layer to form the second patterned mask structure, wherein the second patterned mask structure comprises the third sidewall structure and the remaining fifth oxide layer.
6. The method according to any one of claims 1 to 5, wherein the first patterned mask structure is made of silicon oxide.
7. The method of any of claims 1 to 5, wherein forming a trench in the base structure using the first patterned mask structure comprises:
and performing an etching process on the substrate structure by taking the first patterned mask structure as a mask to form the groove, wherein the groove extends from the surface of the first patterned mask structure to the silicon carbide epitaxial layer.
8. The method of making a silicon carbide device according to any one of claims 1 to 5, wherein forming a gate structure in the trench comprises:
performing an ion implantation process on the bottom of the trench to form a third ion implantation layer of the first conductivity type at the bottom of the trench;
forming a dielectric layer, wherein the dielectric layer covers the inner wall of the groove; and
and filling a polysilicon layer in the groove to form the gate structure.
9. The method of claim 8, wherein the ratio of the oxidation rate of the gate structure to the oxidation rate of the second ion-implanted layer is between (3: 1) and (15: 1).
10. The method of any of claims 1 to 5, wherein forming a contact structure in the exposed first ion-implanted layer using the opening comprises:
performing an ion implantation process on the first ion implantation layer to form a fourth ion implantation layer; and
and performing a laser annealing process on the fourth ion implantation layer to form the contact structure.
11. The method of claim 10, wherein the laser annealing process is performed at a process temperature between 800 ℃ and 1200 ℃.
12. A silicon carbide device, comprising:
a base structure, the base structure comprising: the device comprises a silicon carbide substrate, a silicon carbide epitaxial layer positioned on the silicon carbide substrate, a first ion implantation layer of a first conductivity type positioned on the silicon carbide epitaxial layer, and a second ion implantation layer of a second conductivity type positioned on the first ion implantation layer;
a gate structure formed in the base structure;
a second patterned mask structure formed on the second ion implantation layer;
a contact structure formed in the first ion implantation layer on the side of the second patterned mask structure; and
a conductive layer connected to the contact structure;
wherein the first conductivity type and the second conductivity type are opposite conductivity types.
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