CN114625207A - DAC circuit and gain adjustment method thereof - Google Patents

DAC circuit and gain adjustment method thereof Download PDF

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CN114625207A
CN114625207A CN202210280325.4A CN202210280325A CN114625207A CN 114625207 A CN114625207 A CN 114625207A CN 202210280325 A CN202210280325 A CN 202210280325A CN 114625207 A CN114625207 A CN 114625207A
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dio
circuit
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不公告发明人
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Sichuan Chuang'an Microelectronics Co ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
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    • G05F3/262—Current mirrors using field-effect transistors only

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Abstract

The invention discloses a DAC circuit and a gain adjustment method thereof, wherein the DAC circuit comprises a current mirror DIO, a slope generation circuit and an output resistance circuit, the current mirror DIO adopts a multi-gear parallel structure, the output resistance circuit adopts a plurality of resistors parallel structure, the current mirror DIO and the output resistance circuit are both integrated with switches respectively used for controlling the parallel number of MOS (metal oxide semiconductor) tubes of the current mirror DIO and the parallel number of the resistors. The gain adjustment method adopts a gain linkage adjustment mode, has simple and ingenious overall design, can reduce the area of a layout, saves the cost, ensures that a current source tube of the ramp generation circuit is always in a saturation region when the DAC is in gain switching, and greatly improves the gain adjustment range of the DAC.

Description

DAC circuit and gain adjustment method thereof
Technical Field
The invention relates to the field of integrated circuits, in particular to a DAC circuit and a gain adjustment method thereof.
Background
In an extremely dark shooting environment, the effective image signal is weak, and the gain of the system needs to be increased in order to achieve a specified video amplitude or image brightness.
For the ADC of the Pipe line architecture, the gain is mainly controlled by adjusting the voltage amplitude of the output ramp of the DAC.
For the current steering DAC, the current change at 24dB gain is 1/16 times 0 dB. Due to the fact that the current changes too much, the saturation margin of a current source tube of the ramp generation circuit is insufficient or the current source tube is directly moved from a saturation region to a non-saturation region.
If the saturation margin of the current tube is insufficient or the current tube enters a non-saturation region, the power supply rejection ratio of the DAC and the linearity of the ramp are poor, the ramp under high gain cannot be normally used, and therefore the gain of the current tube after the current tube enters the non-saturation region is unusable.
However, in order to read out useful image signals in an extremely dark environment, the gain of the DAC needs to reach 24dB or more than 24dB, and for this reason, how to ensure that the current source tube of the ramp generation circuit is always in the saturation region when the DAC is in gain switching is important for the improvement of the present application.
Disclosure of Invention
The invention aims to provide a DAC circuit which can ensure that a current source tube of a ramp generating circuit is always in a saturation region when a DAC is switched in gain and can greatly improve the use range of the DAC gain.
In order to solve the technical problem, the invention provides a DAC circuit, which comprises a current mirror DIO, a ramp generation circuit and an output resistance circuit, wherein the current mirror DIO adopts a multi-stage parallel structure, the output resistance circuit adopts a plurality of resistors parallel structure, and the current mirror DIO and the output resistance circuit are both integrated with switches respectively used for controlling the parallel number of MOS transistors of the current mirror DIO and the parallel number of resistors.
As a preferred embodiment of the present application, the current mirror DIO adopts a multi-stage parallel structure, and each stage includes a first PMOS transistor; the drain electrode of the first PMOS tube is respectively connected with the drain electrode of the NMOS tube and the source electrode of the other PMOS tube, and the source electrode of the first PMOS tube is connected with the power supply; and the grid electrode of the first PMOS tube is connected with the source electrode of the NMOS tube and the drain electrode of the other PMOS tube and is connected with the reference current.
As a preferred embodiment of the present application, the current mirror DIO is divided into four stages and connected in parallel.
In a preferred embodiment of the present application, the ramp generating circuit includes a plurality of second PMOS transistors connected in parallel, a gate of each second PMOS transistor is connected to a gate of a first PMOS transistor in the current mirror DIO, a source of each second PMOS transistor is connected to the power supply, and a drain of each second PMOS transistor is connected to the output resistor circuit.
In a preferred embodiment of the present application, an input end of each resistor in the output resistor circuit is connected to the ramp generating circuit, and an output end of each resistor is connected to a drain of an NMOS transistor and a source of a PMOS transistor, respectively, and a source of the NMOS transistor and a drain of the PMOS transistor are grounded.
In a preferred embodiment of the present application, four sets of resistors of the output resistor circuit are connected in parallel.
A gain adjustment method specifically adopts linkage adjustment of the parallel number of MOS tubes in a current mirror DIO and the resistance value of an output resistor according to gain change, so that the MOS tubes are kept in a saturation region, and the output voltage is set voltage.
In a preferred embodiment of the present application, the current mirror DIO is connected to a reference current, the reference current changes with a change in gain, and the reference current is output to the output resistor circuit via the ramp generating circuit.
When the gain is increased, the reference current is reduced, the number of the parallel current mirrors DIO is reduced, and the resistance value of the output resistance circuit is correspondingly reduced, so that the output voltage is the set voltage.
When the gain is reduced, the reference current is increased, the number of the parallel current mirrors DIO is increased, and the resistance value of the output resistance circuit is correspondingly increased, so that the output voltage is the set voltage.
In a preferred embodiment of the present application, the output resistor circuit is formed by connecting a plurality of resistors in parallel.
The invention has the beneficial effects that: the DAC circuit and the gain adjustment method thereof are simple and ingenious in design, and the current mirror DIO and the output resistor are connected in parallel in multiple stages, so that the layout area can be effectively reduced, and the cost is saved. The current source tube of the ramp generating circuit is ensured to be always in a saturation region when the gain is switched by adjusting in a gain linkage mode, the application range of the DAC gain is greatly improved, effective image signals can be read out in an extremely dark environment, and therefore the efficient work of the image sensor is guaranteed.
Drawings
Fig. 1 is a diagram illustrating the relationship between the ADC count and the DAC gain of an image sensor.
Fig. 2 is a conventional DAC circuit diagram.
FIG. 3 is a schematic diagram of a DAC circuit according to the present invention.
Fig. 4 is a comparison diagram of different linearity of the ramp signal when the ramp generating circuit is in a saturation region and a non-saturation region.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.
Also, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The following is described in detail with reference to the embodiments, and for the sake of simplicity, the following omits technical common knowledge known to those skilled in the art.
In current image sensor applications, when the pixel signal is small, the DAC gain is often required to be increased to obtain a larger output, i.e., the count value of the ADC, so as to obtain the effective pixel signal. Fig. 1 shows the relationship of ADC count and DAC gain of an image sensor.
Referring to fig. 1, for example, when the pixel voltage is constant, the DAC gain is switched from 0dB to 12dB, the DAC slope becomes 1/4, and the ADC count becomes four times. This can satisfy that the high-performance image sensor can read out effective image signals even in an extremely dark environment, and can be realized by adjusting the gain of the DAC. In practical applications, the gain of the DAC needs to reach 24dB or more than 24dB, and the conventional DAC cannot meet the requirement.
FIG. 2 schematically shows a DAC circuit of the prior art, in which a current mirror DIO of a ramp generation circuit employs a first PMOS transistor MP11First PMOS transistor MP11The drain of the transistor is connected with the reference current, and the source is connected with the power supply.
First PMOS transistor MP11The grid electrode of the second PMOS tube is connected with the grid electrodes of a plurality of second PMOS tubes connected in parallel, and the second PMOS tube comprises a second PMOS tube MP0And a second PMOS transistor MP1The second PMOS tube MP2Until the second PMOS transistor MPN. The source electrode of the second PMOS tube is connected with the power supply, and the drain electrode is connected with the output resistor R1。
The output voltage of the circuit is:
Figure BDA0003556594010000041
when the gain increases, the reference current IinAlso becomes smaller when the reference current I isinWhen the MOS tube voltage is reduced to a certain degree, all MOS tubes enter a non-saturation region.
For example, when the gain is switched from 0dB to 24dB, the input reference current becomes 1/16 of 0 dB.
Reference current I, as known in the artinRelationship to Vgs is as follows:
Figure BDA0003556594010000042
wherein the other parameters are fixed values, so that the reference current IinThe decrease necessarily results in a decrease in Vgs. When Vgs is smaller than Vth, all MOS tubes enter a non-saturation region, and all current tubes of the ramp generation circuit also enter the non-saturation region.
For example, when the current is reduced 1/16, the driving voltage Vgs-Vth is reduced by about 4 times without changing the aspect ratio and the m-number of the DIO. Since Vth is generally constant, Vgs is reduced more in order to reduce current. When Vgs is smaller than Vth, the tube enters a non-saturation region, and the current tube of the ramp generation circuit also enters the non-saturation region completely.
Fig. 4 shows a comparison of different linearity of ramp signals in a saturated region and a non-saturated region of the ramp generation circuit. As shown in fig. 4, when all the current tubes of the ramp generating circuit enter the non-saturation region, the linearity of the generated ramp signal is degraded, which causes deviation of the count value of the counter of the image sensor at high gain, thereby affecting the imaging effect, and the power supply rejection ratio of the DAC is degraded.
In order to solve the problem, the application provides a novel DAC circuit, which can realize the adjustment of ADC gain and ensure that an MOS (metal oxide semiconductor) tube in the circuit is always in a saturation region when the DAC gain is increased, thereby ensuring the normal work of an image sensor.
The DAC circuit comprises a current mirror, a ramp generating circuit and an output resistor circuit.
The current mirror DIO adopts a multi-gear parallel structure, and the output resistance circuit adopts a structure that a plurality of resistors are connected in parallel. Meanwhile, the current mirror DIO is integrated with a switch for controlling the number of MOS tubes of the current mirror DIO in parallel connection; the output resistance circuit is also integrated with switches for controlling the parallel number of the resistors.
In specific implementation, through the structural improvement design of the ramp generation circuit, the current mirror DIO in the ramp generation circuit is divided into multiple stages to be connected in parallel, and the output resistor is also divided into several stages to be connected in parallel.
The number of the current mirrors DIO and the resistors connected in parallel can be controlled by the switches, and the number of the current mirrors DIO and the resistors connected in parallel can be selected according to the magnitude of the output current of the gain control.
Fig. 3 shows a schematic structural diagram of a DAC circuit of the present invention, in which a plurality of stages of current mirrors DIO are connected in parallel, and each stage includes a first PMOS transistor, a drain of the first PMOS transistor is connected to a drain of an NMOS transistor and a source of another PMOS transistor, respectively, and a source of the first PMOS transistor is connected to a power supply.
And the grid electrode of the first PMOS tube is connected with the source electrode of the NMOS tube and the drain electrode of the other PMOS tube and is connected with the reference current.
The slope generation circuit comprises a plurality of second PMOS tubes connected in parallel, the grid electrodes of the second PMOS tubes are connected with the grid electrode of the first PMOS tube in the current mirror DIO, the source electrode of each second PMOS tube is connected with the power supply, and the drain electrode of each second PMOS tube is connected with the output resistor circuit.
The input end of each resistor in the output resistor circuit is connected with the ramp generating circuit, the output end of each resistor is respectively connected with the drain electrode of an NMOS tube and the source electrode of a PMOS tube, and the source electrode of the NMOS tube and the drain electrode of the PMOS tube are grounded.
As a preferred embodiment of the present application, the current mirror DIO is divided into four stages for parallel connection, and each stage is the first stage respectivelyPMOS pipe MP14The first PMOS transistor MP13The first PMOS transistor MP12And a first PMOS transistor MP11。
The ramp generation circuit consists of a plurality of second PMOS tubes connected in parallel, and the second PMOS tubes comprise second PMOS tubes MP0And a second PMOS transistor MP1And a second PMOS transistor MP2To the second PMOS transistor MPN。
In a preferred embodiment of the present application, the resistors of the output resistor circuit are also divided into four groups, which are R1, R2, R3 and R4, and connected in parallel, and all the resistors are grounded.
The output voltage formula of the DAC circuit is as follows:
Figure BDA0003556594010000061
according to the application, the current mirror DIO is divided into four gears to be connected in parallel, and then the resistor in the output resistor circuit is divided into four gears to be connected in parallel.
The current mirror DIO and the resistor are controlled by a switch, the number of the current mirror DIO and the resistor connected in parallel can be controlled in a stepping mode, and finally the number of the current mirror DIO and the resistor connected in parallel is selected according to the size of output current of gain control.
The parallel connection method is adopted to change the parallel connection number of the current mirrors DIO and the resistors through the switches, the gain is improved in a gain linkage mode, the layout area can be reduced, the cost is saved, and the popularization and the application are convenient.
According to an embodiment of the application, a gain adjustment method is provided, and specifically, according to gain change, the parallel connection number of MOS transistors in a current mirror DIO and the resistance value of an output resistor are adjusted in a linkage manner, so that the MOS transistors are kept in a saturation region, and the output voltage is a set voltage.
The current mirror DIO is connected with reference current, the reference current changes along with gain change, the reference current is output to the output resistance circuit after passing through the slope generation circuit, and the output voltage is unchanged by adjusting the resistance value connected into the output resistance circuit.
The output resistance circuit can adopt a mode of connecting a plurality of resistors in parallel, and the number of the resistors connected in parallel is controlled by a switch, so that the resistance value of the output resistance circuit is controlled.
At low gain, the input current IinAnd at the moment, selecting a large current mirror DIO number, outputting a small current by the slope output circuit, and selecting a large output resistor to reach the set voltage of the output voltage, namely, the output voltage is unchanged.
When the gain is high, the input current is small, at the moment, a small current mirror DIO number is selected, the slope output circuit outputs a large current, and a small output resistor is selected to enable the output voltage to be the set voltage, namely the output voltage is unchanged.
Specifically, the resistance of the output resistor matches the number of the current mirrors DIO. For example, the number Nx of the current mirrors DIO before adjustment is n1+ n2+ n3+ n4, and the output resistances are R1, R2, R3, and R4 in parallel (Rx R1// R2// R3// R4); the number Nx of the DIOs after adjustment is n2+ n3+ n4, and the output resistors R2, R3, and R4 are connected in parallel (Rx is R2// R3// R4), that is, the resistance value before adjustment/the resistance value after adjustment is the number DIO of the current mirrors before adjustment/the number DIO of the current mirrors after adjustment.
In actual operation, when switching to high gain, a small current mirror DIO and a small output resistor can be selected, and under the condition of ensuring that the output voltage is not changed, the current source tube is always in a saturation region, so that a useful image signal can be read out in an extremely dark environment, and the high-efficiency work of the image sensor is ensured.
In order to compare the DAC of the prior art with the DAC circuit of the present invention, the basic parameter settings are performed according to table 1, and then the simulation results are shown in tables 2 and 3.
TABLE 1 basic parameter configuration table of circuit
Figure BDA0003556594010000081
TABLE 2 simulation result statistical table of the existing DAC circuit
Figure BDA0003556594010000082
TABLE 3 simulation result statistics table of DAC circuit of the present invention
Figure BDA0003556594010000083
Figure BDA0003556594010000091
From the simulation results, it can be easily seen that the current of the existing DAC circuit is too small at high gain, so that the tube enters the non-saturation region at 24 dB. The circuit of the application can automatically adjust proper DIO number and output resistance along with the size of input current, and the current tube is still in a saturation region at 36 dB. If the parallel connection number of the current mirror DIO and the output resistor is continuously increased, the current tube can be in a saturation region when the gain is above 36 dB.
It should be noted that the above is only one implementation data, and the technology to be protected in the present application is not limited to the parameter data setting.
Compared with the prior art, the invention has the advantages that:
1. the gain range of the DAC circuit is improved, the MOS tube in the DAC circuit can still be in a saturation region when the DAC gain is increased, and normal work of the image sensor is guaranteed; the upper limit of the using gain of the common DAC is about 24dB, and the using gain of the DAC can be increased to be more than 36dB in a gain linkage mode;
2. the input current can be reduced along with the increase of the DAC gain, and the DIO parallel number of the self-adjusting current mirror ensures that Vgs can not become too small along with the increase of the gain, thereby avoiding the problem that a tube enters a non-saturation region;
3. when the output current of the current mirror DIO is increased by adjusting the number of the current mirrors DIO, the output voltage is ensured to be the same as the set voltage by adjusting the resistance value of the output resistor, namely, the resistance value of the output resistor is reduced by the same multiple.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A DAC circuit, characterized by: including current mirror DIO, slope generating circuit and output resistance circuit, current mirror DIO adopts many grades of parallel structure, and output resistance circuit adopts a plurality of resistance parallel structure, current mirror DIO and output resistance circuit all integrate the switch, are used for controlling the parallelly connected number of MOS pipe of current mirror DIO and the parallelly connected number of resistance respectively.
2. The DAC circuit of claim 1 wherein: the DIO of the current mirror adopts a multi-gear parallel structure, and each gear comprises a first PMOS (P-channel metal oxide semiconductor) tube; the drain electrode of the first PMOS tube is respectively connected with the drain electrode of the NMOS tube and the source electrode of the other PMOS tube, and the source electrode of the first PMOS tube is connected with the power supply; and the grid electrode of the first PMOS tube is connected with the source electrode of the NMOS tube and the drain electrode of the other PMOS tube and is connected with the reference current.
3. The DAC circuit of claim 2 wherein: the current mirror DIO is divided into four stages for parallel connection.
4. The DAC circuit of claim 2 wherein: the ramp generating circuit comprises a plurality of second PMOS tubes connected in parallel, the grid electrodes of the second PMOS tubes are connected with the grid electrode of the first PMOS tube in the current mirror DIO, the source electrodes of the second PMOS tubes are connected with a power supply, and the drain electrodes of the second PMOS tubes are connected with the output resistor circuit.
5. The DAC circuit of claim 1 wherein: the input end of each resistor in the output resistor circuit is connected with the ramp generating circuit, the output end of each resistor is respectively connected with the drain electrode of an NMOS tube and the source electrode of a PMOS tube, and the source electrode of the NMOS tube and the drain electrode of the PMOS tube are grounded.
6. The DAC circuit of claim 5, wherein: the resistors of the output resistor circuit are in a structure that four groups of resistors are connected in parallel.
7. A method of gain adjustment, characterized by: according to the gain change, the parallel connection number of the MOS tubes in the current mirror DIO and the resistance value of the output resistor are adjusted in a linkage mode, the MOS tubes are kept in a saturation region, and the output voltage is set.
8. The gain adjustment method according to claim 7, wherein: the current mirror DIO is connected with reference current, the reference current changes along with gain change, and the reference current is output to the output resistance circuit after passing through the slope generation circuit.
9. The gain adjustment method according to claim 7, wherein:
when the gain is increased, the number of the parallel current mirrors DIO is reduced, and the resistance value of the output resistance circuit is correspondingly reduced, so that the output voltage is the set voltage.
When the gain is reduced, the number of the parallel current mirrors DIO is increased, and the resistance value of the output resistance circuit is correspondingly increased, so that the output voltage is the set voltage.
10. The gain adjustment method according to claim 7, wherein: the pre-adjustment resistance value/the post-adjustment resistance value is the number of the pre-adjustment current mirrors DIO/the number of the post-adjustment current mirrors DIO.
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CN112104371A (en) * 2019-06-17 2020-12-18 意法半导体国际有限公司 Adaptive low-power consumption common mode buffer
CN212435676U (en) * 2019-06-17 2021-01-29 意法半导体国际有限公司 Analog-to-digital converter and electronic circuit
CN212724728U (en) * 2019-08-01 2021-03-16 意法半导体股份有限公司 Current generator circuit and phase change memory device
CN111897209A (en) * 2020-05-19 2020-11-06 成都天锐星通科技有限公司 Millimeter wave chip gain high-low temperature self-adaptive bias structure and method
CN112383725A (en) * 2020-11-13 2021-02-19 成都微光集电科技有限公司 Ramp signal generating circuit and method, CMOS image sensor and readout circuit thereof
CN114034411A (en) * 2021-11-10 2022-02-11 四川创安微电子有限公司 Image sensor temperature measurement system and method

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Application publication date: 20220614