CN114614657B - Adjusting network, rectifying circuit and electronic equipment - Google Patents

Adjusting network, rectifying circuit and electronic equipment Download PDF

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Publication number
CN114614657B
CN114614657B CN202210261236.5A CN202210261236A CN114614657B CN 114614657 B CN114614657 B CN 114614657B CN 202210261236 A CN202210261236 A CN 202210261236A CN 114614657 B CN114614657 B CN 114614657B
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current signal
network
capacitor
alternating current
terminal
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CN114614657A (en
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李小飞
路延
马许愿
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Um Zhuhai Research Institute
University of Macau
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Um Zhuhai Research Institute
University of Macau
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)

Abstract

The invention discloses an adjusting network, a rectifying circuit and electronic equipment, and relates to the technical field of power supplies. The rectification circuit comprises a bridge rectification network and an adjusting network, the direct current voltage difference value at two ends of the voltage-controlled capacitor associated with the rectification circuit can be indirectly adjusted by adjusting the direct current voltage value on the second low-pass filter, namely the capacitance value of the voltage-controlled capacitor can be adjusted, the alternating current signal amplitude of the grid electrode of the associated MOS tube is changed by reasonably adjusting the capacitance value of the voltage-controlled capacitor, and the rectification circuit can obtain higher energy conversion efficiency.

Description

Adjusting network, rectifying circuit and electronic equipment
Technical Field
The invention relates to the technical field of power supplies, in particular to a regulating network, a rectifying circuit and electronic equipment.
Background
High frequency ac/rf energy conversion is widely used in isolated energy conversion systems, wireless energy transmission systems with implanted chips, and various rf energy collection systems. The high frequency ac/rf energy conversion of the related art mainly includes: a diode-operated rectifier and a cross-coupled-operated rectifier. The rectifier working in a diode state is difficult to realize high-efficiency energy conversion under low input voltage; although a rectifier operating in a cross-coupled state can obtain high energy conversion efficiency at low voltage input, the voltage input range for maintaining high energy conversion efficiency is narrow, and the energy conversion efficiency is rapidly reduced at high input voltage. Meanwhile, the input voltage corresponding to the highest energy conversion efficiency of the rectifier working in the cross-coupling state is also influenced by the voltage threshold of the device.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides a regulating network, a rectifying circuit and an electronic device, which can obtain higher energy conversion efficiency.
In one aspect, an embodiment of the present invention provides an adjusting network, which includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first low-pass filter, and a second low-pass filter, where the third capacitor and the fourth capacitor are both voltage-controlled capacitors, a first end of the third capacitor is connected to a second end of the first capacitor, a first end of the fourth capacitor is connected to a second end of the second capacitor, the first low-pass filter includes a fifth capacitor, a first resistor, and a second resistor, a second end of the fifth capacitor is connected to a first end of the first resistor and a first end of the second resistor, a second end of the first resistor is connected to a second end of the fourth capacitor, a second end of the second resistor is connected to a second end of the third capacitor, and the second low-pass filter includes a sixth capacitor, a third resistor, and a fourth resistor, the second end of the sixth capacitor is connected to the first end of the third resistor and the first end of the fourth resistor, the second end of the third resistor is connected to the first end of the third capacitor, and the second end of the fourth resistor is connected to the first end of the fourth capacitor, wherein the first end of the first capacitor is used as the first end of the regulating network, the second end of the third capacitor is used as the second end of the regulating network, the first end of the second capacitor is used as the third end of the regulating network, the second end of the fourth capacitor is used as the fourth end of the regulating network, the first end of the fifth capacitor is used as the fifth end of the regulating network, the first end of the sixth capacitor is used as the sixth end of the regulating network, and the second end of the sixth capacitor is used as the seventh end of the regulating network.
According to some embodiments of the invention, the first resistance is replaced by a first inductance and the second resistance is replaced by a second inductance.
According to some embodiments of the invention, the third resistance is replaced with a third inductance and the fourth resistance is replaced with a fourth inductance.
On the other hand, the embodiment of the present invention provides a rectifier circuit, including a bridge rectifier network and the above-mentioned regulating network, where the bridge rectifier network is connected to the regulating network;
according to some embodiments of the present invention, the bridge rectification network has a first ac signal terminal, a second ac signal terminal, a first dc signal terminal, and a second dc signal terminal, and the bridge rectification network includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor; the drain end of the first NMOS tube is connected to the first alternating current signal end, and the source end of the first NMOS tube is connected to the first direct current signal end; the drain end of the second NMOS tube is connected to the second alternating current signal end, and the source end of the second NMOS tube is connected to the first direct current signal end; the drain end of the first PMOS tube is connected to the first alternating current signal end, the gate end of the first PMOS tube is connected to the second alternating current signal end, and the source end of the first PMOS tube is connected to the second direct current signal end; the drain end of the second PMOS tube is connected to the second alternating current signal end, the gate end of the second PMOS tube is connected to the first alternating current signal end, and the source end of the second PMOS tube is connected to the second direct current signal end; the first end of the adjusting network is connected to the first alternating current signal end, and the second end of the adjusting network is connected to the gate end of the second NMOS tube; the third end of the adjusting network is connected to the second alternating current signal end, the fourth end of the adjusting network is connected to the grid end of the first NMOS tube, the fifth end and the sixth end of the adjusting network are connected to the first direct current signal end, and the seventh end of the adjusting network is used for receiving adjusting signals.
According to some embodiments of the present invention, the bridge rectifier network has a first ac signal terminal, a second ac signal terminal, a first dc signal terminal, and a second dc signal terminal, and the bridge rectifier network includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor; the drain terminal of the first NMOS tube is connected to the first alternating current signal terminal, the gate terminal of the first NMOS tube is connected to the second alternating current signal terminal, and the source terminal of the first NMOS tube is connected to the first direct current signal terminal; the drain end of the second NMOS tube is connected to the second alternating current signal end, the gate end of the second NMOS tube is connected to the first alternating current signal end, and the source end of the second NMOS tube is connected to the first direct current signal end; the drain end of the first PMOS tube is connected to the first alternating current signal end, the gate end of the first PMOS tube is connected to the second alternating current signal end, and the source end of the first PMOS tube is connected to the second direct current signal end; the drain terminal of the second PMOS tube is connected to the second alternating-current signal terminal, the gate terminal of the second PMOS tube is connected to the first alternating-current signal terminal, and the source terminal of the second PMOS tube is connected to the second direct-current signal terminal; a first end of the adjusting network is connected to the first alternating current signal end, and a second end of the adjusting network is connected to a grid end of the second PMOS tube; the third end of the adjusting network is connected to the second alternating current signal end, the fourth end of the adjusting network is connected to the grid end of the first PMOS tube, the fifth end and the sixth end of the adjusting network are connected to the first direct current signal end, and the seventh end of the adjusting network is used for receiving adjusting signals.
According to some embodiments of the invention, the number of said regulating networks is two, one of them being a first regulating network and the other being a second regulating network; the bridge type rectification network is provided with a first alternating current signal end, a second alternating current signal end, a first direct current signal end and a second direct current signal end, and comprises a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first PMOS (P-channel metal oxide semiconductor) tube and a second PMOS tube; the drain end of the first NMOS tube is connected to the first alternating current signal end, the gate end of the first NMOS tube is connected to the second alternating current signal end, and the source end of the first NMOS tube is connected to the first direct current signal end; the drain end of the second NMOS tube is connected to the second alternating current signal end, the gate end of the second NMOS tube is connected to the first alternating current signal end, and the source end of the second NMOS tube is connected to the first direct current signal end; the drain end of the first PMOS tube is connected to the first alternating current signal end, the gate end of the first PMOS tube is connected to the second alternating current signal end, and the source end of the first PMOS tube is connected to the second direct current signal end; the drain end of the second PMOS tube is connected to the second alternating current signal end, the gate end of the second PMOS tube is connected to the first alternating current signal end, and the source end of the second PMOS tube is connected to the second direct current signal end; the first end of the first adjusting network is connected to the first alternating current signal end, and the second end of the first adjusting network is connected to the gate end of the second NMOS tube; a third end of the first adjusting network is connected to the second alternating current signal end, a fourth end of the first adjusting network is connected to a gate end of the first NMOS tube, a fifth end and a sixth end of the first adjusting network are connected to the first direct current signal end, and a seventh end of the first adjusting network is used for receiving a first adjusting signal; the first end of the second regulating network is connected to the first alternating current signal end, and the second end of the second regulating network is connected to the gate end of the second PMOS tube; the third end of the second adjusting network is connected to the second alternating current signal end, the fourth end of the second adjusting network is connected to the gate end of the first PMOS tube, the fifth end and the sixth end of the second adjusting network are connected to the first direct current signal end, and the seventh end of the second adjusting network is used for receiving a second adjusting signal.
According to some embodiments of the invention, a seventh capacitor is connected to the first ac signal terminal, and an eighth capacitor is connected to the second ac signal terminal.
According to some embodiments of the invention, a first filter capacitor is connected to the second dc signal terminal.
In another aspect, an embodiment of the present invention provides an electronic device, which includes the rectifier circuit.
The embodiment of the invention at least has the following beneficial effects:
the embodiment of the invention can indirectly adjust the direct-current voltage value of the voltage-controlled capacitor associated with the second low-pass filter by adjusting the direct-current voltage value on the second low-pass filter, namely adjust the capacitance value of the voltage-controlled capacitor, and can ensure that the rectifying circuit obtains higher energy conversion efficiency by reasonably adjusting the capacitance values at the two ends of the voltage-controlled capacitor to change the amplitude of the alternating-current signal of the grid electrode of the associated MOS tube.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic circuit diagram of a cross-coupled state rectifier of the related art;
FIG. 2 is one of the schematic circuit diagrams of a rectifier circuit according to an embodiment of the present invention;
FIG. 3 is the output power and voltage V of the rectifier circuit shown in FIG. 2 BNi -V INi A change curve therebetween;
FIG. 4 is a graph showing the power conversion efficiency and the input voltage V of the rectifier circuit shown in FIG. 2 IN Graph of the relationship between;
FIG. 5 is a second schematic circuit diagram of a rectifier circuit according to the second embodiment of the present invention;
FIG. 6 shows the output power and voltage V of the rectifier circuit shown in FIG. 5 BCNi -V INi Wherein (a) is a change curve at a low input voltage, and (b) is a change curve at a high input voltage;
FIG. 7 is a graph showing the power conversion efficiency and the input voltage V of the rectifier circuit shown in FIG. 5 IN Graph of the relationship between;
FIG. 8 is a schematic diagram of the DC voltage to VINI circuit of the rectifier circuit shown in FIG. 2;
FIG. 9 is a third schematic circuit diagram of a rectifier circuit according to an embodiment of the present invention;
FIG. 10 is a fourth schematic circuit diagram of a rectifier circuit according to an embodiment of the present invention;
FIG. 11 is a graph showing a relationship between a voltage value and a capacitance value of a voltage-controlled capacitor according to an embodiment of the present invention;
fig. 12 is a circuit schematic block diagram of a rectifier adaptive adjustment scheme of an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, "a plurality" means one or more, "a plurality" means two or more, and greater than, less than, more than, etc. are understood as excluding the present number, and "greater than", "lower than", "inner", etc. are understood as including the present number. If the description of "first", "second", etc. is used for the purpose of distinguishing technical features, it is not intended to indicate or imply relative importance or to implicitly indicate the number of indicated technical features or to implicitly indicate the precedence of the indicated technical features.
In the description of the present invention, unless otherwise explicitly limited, the terms "disposed," "connected," and the like are to be construed broadly, and those skilled in the art can reasonably determine the specific meaning of the above-mentioned terms in the present invention by combining the detailed contents of the technical solutions.
Referring to fig. 1, fig. 1 shows a schematic circuit diagram of a cross-coupled mode rectifier. The rectifier shown in fig. 1 includes a bridge rectifier network 100, the bridge rectifier network 100 has a first ac signal terminal, a second ac signal terminal, a first dc signal terminal and a second dc signal terminal, the bridge rectifier network 100 includes a first NMOS transistor (for example, the MOS transistor M1 in fig. 1), a second NMOS transistor (for example, the MOS transistor M2 in fig. 1), a first PMOS transistor (for example, the MOS transistor M3 in fig. 1) and a second PMOS transistor (for example, the MOS transistor M4 in fig. 1), a drain terminal of the first NMOS transistor is connected to the first ac signal terminal, a gate terminal of the first NMOS transistor is connected to the second ac signal terminal, a source terminal of the first NMOS transistor is connected to the first dc signal terminal, a drain terminal of the second NMOS transistor is connected to the second ac signal terminal, a gate terminal of the second NMOS transistor is connected to the first ac signal terminal, a drain terminal of the first PMOS transistor is connected to the first ac signal terminal, a gate terminal of the first NMOS transistor is connected to the second ac signal terminal, a gate terminal of the second NMOS transistor is connected to the second dc signal terminal, and a drain terminal of the second PMOS transistor is connected to the second ac signal terminal.
In use, the bridge typeA seventh capacitor (e.g., capacitor C in fig. 1) is connected to the first ac signal end of the rectifier network 100 k1 ) And connected to the first end of the ac signal source through a seventh capacitor, and the second ac signal end of the bridge rectifier network 100 is connected to an eighth capacitor (e.g., capacitor C in fig. 1) k2 ) And is connected to the second end of the ac signal source through an eighth capacitor, wherein the seventh capacitor and the eighth capacitor both play a role of ac signal coupling, and the second dc signal end of the bridge rectifier network 100 is connected to a first filter capacitor (for example, a capacitor Co in fig. 1) and is grounded through the first filter capacitor, it is contemplated that the second dc signal end of the bridge rectifier network 100 is connected to a load (not shown) and is configured to provide a dc voltage to the load. When the first end of the alternating current signal source is positive, the first PMOS tube and the second NMOS tube are conducted, the first NMOS tube and the second PMOS tube are cut off, and current passes through a node V OUTi Flows to the first filter capacitor and the load and flows back to the node V via Ground (GND) INi Namely, the seventh capacitor, the first PMOS transistor, the first filter capacitor (or load), the ground, the second NMOS transistor and the eighth capacitor form a signal loop; when the second end of the alternating current signal source is positive, the first NMOS tube and the second PMOS tube are conducted, the first PMOS tube and the second NMOS tube are cut off, and the eighth capacitor, the second PMOS tube, the first filter capacitor (or load), the ground, the first NMOS tube and the seventh capacitor form a signal loop.
Although the rectifier operating in the cross-coupled state can obtain high energy conversion efficiency at low voltage input, the voltage input range for maintaining high energy conversion efficiency is narrow, and the energy conversion efficiency is drastically reduced at high input voltage (see fig. 4). Meanwhile, the input voltage corresponding to the highest energy conversion efficiency of the rectifier working in the cross-coupled state is also influenced by the voltage threshold of the device, so that the input voltage range for maintaining high efficiency is narrow.
In response to the deficiencies of the related art, the present embodiments provide various solutions for an adaptive cross-coupled amplitude regulated high frequency rectifier. By adjusting the cross coupling state of the gate end of the MOS tube, the high-frequency rectifier can realize maximum power output at a certain cross coupling working point and simultaneously realize higher energy conversion efficiency. Various solutions of the present embodiment are explained in detail below.
Referring to fig. 2, fig. 2 shows a schematic circuit diagram of a rectifier circuit in one solution. The rectifier circuit shown in fig. 2 includes a bridge rectifier network 100 and a regulating network connected to the bridge rectifier network 100, where the regulating network includes a first capacitor (e.g., a capacitor C2 in fig. 2), a second capacitor (e.g., a capacitor C3 in fig. 2), and a first low-pass filter, where the first capacitor and the second capacitor are both voltage-controlled capacitors, the first low-pass filter includes a fifth capacitor (e.g., a capacitor C5 in fig. 2), a first resistor (e.g., a resistor R1 in fig. 2), and a second resistor (e.g., a resistor R2 in fig. 2), a first end of the first capacitor is used as a first end of the regulating network and connected to a first ac signal terminal, a second end of the first capacitor is used as a second end of the regulating network and connected to a gate terminal of a second NMOS transistor, a first end of the second capacitor is used as a second end of the regulating network and connected to a second ac signal terminal, a second end of the second capacitor is used as a fourth terminal of the regulating network and connected to a gate terminal of the first NMOS transistor, a first end of the fifth capacitor is connected to a second terminal of the second capacitor, and a second end of the second capacitor is connected to the second terminal of the second resistor, and the second terminal of the second capacitor.
When the first end of the alternating current signal source is positive, one part of the alternating current signal (positive signal) is coupled to the grid end of the second PMOS tube through the seventh capacitor, one part of the alternating current signal (positive signal) is coupled to the first capacitor through the seventh capacitor and is coupled to the grid end of the second NMOS tube through the first capacitor, the second NMOS tube is conducted, and the second PMOS tube is cut off; similarly, a part of the alternating current signal (negative signal) is coupled to the gate end of the first PMOS transistor through the eighth capacitor, a part of the alternating current signal (negative signal) is coupled to the second capacitor through the eighth capacitor and is coupled to the gate end of the first NMOS transistor through the second capacitor, the first PMOS transistor is turned on, and the first NMOS transistor is turned off. The alternating current signal passes through the seventh capacitor, the first PMOS tube, the first filter capacitor (or load), the ground, the second NMOS tube and the eighth capacitor to form a loop.
When the second end of the alternating current signal source is positive, one part of an alternating current signal (positive signal) is coupled to the grid end of the first PMOS tube through the eighth capacitor, one part of the alternating current signal (positive signal) is coupled to the second capacitor through the eighth capacitor and is coupled to the grid end of the first NMOS tube through the second capacitor, the first NMOS tube is conducted, and the first PMOS tube is cut off; similarly, a part of the alternating current signal (negative signal) is coupled to the second PMOS transistor through the seventh capacitor, a part of the alternating current signal (negative signal) is coupled to the first capacitor through the seventh capacitor and is coupled to the gate terminal of the second NMOS transistor through the first capacitor, the second PMOS transistor is turned on, and the second NMOS transistor is turned off. The alternating current signal passes through the eighth capacitor, the second PMOS tube, the first filter capacitor (or load), the ground, the first NMOS tube and the seventh capacitor to form a loop.
Wherein, the node V BNi The direct current voltage of the first NMOS tube is equal to the grid end voltage of the first NMOS tube and the grid end voltage of the second NMOS tube. By adjusting the difference in DC voltage across the fifth capacitor, i.e. node V BNi And node V INi The direct current voltage value of the grid end of the first NMOS tube and the direct current voltage value of the grid end of the second NMOS tube can be adjusted simultaneously by the voltage difference value, the working state (the conduction depth) of the first NMOS tube and the second NMOS tube can be effectively changed, and the working state of the rectification circuit can be further changed. Wherein, the output power of the rectifying circuit and the voltage V at two ends of the fifth capacitor BNi -V INi The change curve between them is shown in fig. 3. As can be seen from FIGS. 2 and 3, node V is adjusted appropriately BNi The voltage value of the node can be adjusted to the node V BNi And node V INi The voltage difference between them makes a certain cross-coupling working point of the rectification circuit capable of realizing maximum power output and simultaneously realizing higher energy conversion efficiency, wherein fig. 4 shows the power conversion efficiency PCE (or output power POUT, output voltage VOUT) and input voltage V of the rectification circuit (curve Q3) of fig. 2, the rectifier (curve Q2) of fig. 1 and the rectifier (curve Q1) of diode state operation in the related art IN Graph of the relationship between, wherein the input voltage V IN Generated for an ac signal source. As can be seen from the graph, the rectifier circuit shown in fig. 2 can obtain high energy conversion efficiency, and the voltage input range for maintaining high energy conversion efficiency is wide, and when the input voltage is high, the energy conversion efficiency can be maintained at a high level.
It should be noted that, during stable operation, the gate voltage of the first NMOS transistor and the gate voltage of the second NMOS transistor have both an ac component and a dc component, and the first filter capacitor is used for filtering, so that the second dc signal terminal maintains a dc voltage state. The first resistor and the second resistor have larger resistance values, so that the first resistor and the second resistor consume smaller alternating current power.
Referring to fig. 5, fig. 5 shows a schematic circuit diagram of a rectifier circuit in another solution. The rectifier circuit shown in fig. 5 includes a bridge rectifier network 100 and a regulation network connected to the bridge rectifier network 100. A regulating network comprising a first capacitor (e.g. the capacitor C2 in fig. 5), a second capacitor (e.g. the capacitor C5 in fig. 5), a third capacitor (e.g. the capacitor C3 in fig. 5), a fourth capacitor (e.g. the capacitor C4 in fig. 5), a first low-pass filter and a second low-pass filter, a first terminal of the third capacitor being connected to a second terminal of the first capacitor, a first terminal of the fourth capacitor being connected to a second terminal of the second capacitor, the first low-pass filter comprising a fifth capacitor (e.g. the capacitor C7 in fig. 5), a first resistor (e.g. the resistor R1 in fig. 5) and a second resistor (e.g. the resistor R2 in fig. 5), a second terminal of the fifth capacitor being connected to a first terminal of the first resistor and a first terminal of the second resistor, a second terminal of the first resistor being connected to a second terminal of the fourth capacitor, the second end of the second resistor is connected to the second end of the third capacitor, the second low-pass filter includes a sixth capacitor (e.g., the capacitor C8 in fig. 5), a third resistor (e.g., the resistor R3 in fig. 5) and a fourth resistor (e.g., the resistor R4 in fig. 5), the second end of the sixth capacitor is connected to the first end of the third resistor and the first end of the fourth resistor, the second end of the third resistor is connected to the first end of the third capacitor, the second end of the fourth resistor is connected to the first end of the fourth capacitor, wherein the first end of the first capacitor is used as the first end of the regulating network, the second end of the third capacitor is used as the second end of the regulating network, the first end of the second capacitor is used as the third end of the regulating network, the second end of the fourth capacitor is used as the fourth end of the regulating network, and the first end of the fifth capacitor is used as the fifth end of the regulating network, the first terminal of the sixth capacitor serves as the sixth terminal of the regulating network and the second terminal of the sixth capacitor serves as the seventh terminal of the regulating network.
In the rectifier circuit shown in fig. 5, the first end of the regulating network is connected to the first ac signal end, and the second end of the regulating network is connected to the gate end of the second MMOS tube; the third end of the adjusting network is connected to the second alternating current signal end, the fourth end of the adjusting network is connected to the grid end of the first NMOS tube, the fifth end and the sixth end of the adjusting network are connected to the first direct current signal end, and the seventh end of the adjusting network is used for receiving adjusting signals.
When the first terminal of the ac signal source is positive, through the coupling of the seventh capacitor and the eighth capacitor, the positive signal of the ac signal source can be considered to be fully coupled to the lower plate of the seventh capacitor (i.e., node a in fig. 5), and the negative signal of the ac signal source can be considered to be fully coupled to the upper plate of the eighth capacitor (i.e., node F in fig. 5). Meanwhile, a signal of a lower electrode plate of the seventh capacitor is coupled to the gate end of the second NMOS tube through the first capacitor and the third capacitor, and the coupling strength of the alternating current signal is obtained by the following formula (1):
Figure 502830DEST_PATH_IMAGE001
（1）
in the formula, V C Is the value of the alternating voltage of node C, V A Is the value of the alternating voltage at node A, C 2 Is the capacitance value of the first capacitor, C 3 Is the capacitance value of the third capacitor, Z C Operator for the AC impedance looking into the left side from the arrow in FIG. 5s=2πf. According to the formula, V can be effectively adjusted by adjusting the capacitance value of the third capacitor C And V A The ratio therebetween. The capacitance of the third capacitor changes with the DC voltage of the node B, which is equal to the node V BCNi Thus, by adjusting the value of the DC voltage across the sixth capacitorWith a direct voltage difference therebetween, i.e. node V BCNi And node V INi The value of the capacitance of the third capacitor can be adjusted by the voltage difference between the first and second capacitors. Similarly, the capacitance of the fourth capacitor varies with the DC voltage at node E, which is equal to node V BCNi The capacitance value of the fourth capacitor can be adjusted by adjusting the direct-current voltage difference between the two ends of the sixth capacitor, so that the voltage amplitude of the alternating-current signal coupled to the gate end of the first NMOS tube and the gate end of the second NMOS tube is changed, the working state (conduction depth) of the first NMOS tube and the second NMOS tube is further changed, and the rectifying circuit works in the maximum output power state. Wherein FIG. 6 shows the output power of the rectifying circuit and the voltage V across the sixth capacitor BCNi -V INi The change curve therebetween. From fig. 5 and 6, it can be seen that the node V is properly adjusted BCNi The voltage value of the node can be adjusted to the node V BCNi And node V INi There is an optimum value of the voltage difference between the output voltage and the output voltage, so that the maximum power output can be achieved at a certain cross-coupled operating point of the rectifier circuit, and at the same time, a higher energy conversion efficiency can be achieved, wherein fig. 7 shows the power conversion efficiencies PCE (or output power POUT, output voltage VOUT) and input voltage V of the rectifier circuit of fig. 5 (curve Q4), the rectifier circuit of fig. 8 (curve Q5), and the diode-state-operated rectifier of the related art (curve Q1) IN The graph of the relationship between the first and second MOS transistors M1 and M2 is shown in fig. 8, and the curve Q4 is shown in fig. 8 based on the graph of the rectifier circuit shown in fig. 2 (see 5,V for a graph of the circuit schematic diagram of fig. 8), where the curve Q5 is obtained when the rectifier circuit shown in fig. 2 is not applied with ac amplitude modulation and the dc voltage of the first MOS transistor (i.e., MOS transistor M1) and the second MOS transistor (i.e., MOS transistor M2) is connected to VINi BNi Is connected to V INi ) A curve obtained by alternating current amplitude modulation is adopted; input voltage V IN Generated for an ac signal source. As can be seen from the graph, the rectifier circuit shown in fig. 5 can obtain high energy conversion efficiency, and the voltage input range for maintaining high energy conversion efficiency is wide, and when the input voltage is high, the energy conversion efficiency can be maintained at a high level; in the case of a low input voltage, the curve Q4 and the curve Q5 are relatively close, which shows thatIn the case of a low input voltage, the rectifier circuit shown in fig. 5 and the rectifier circuit shown in fig. 8 have substantially the same energy conversion efficiency; in the case of a high input voltage, the curve Q4 can be maintained at a high level, and the curve Q5 starts to decrease, which indicates that in the case of a high input voltage, the energy conversion efficiency of the rectifier circuit shown in fig. 5 is better than that of the rectifier circuit shown in fig. 8, and the energy conversion efficiency (efficiency curve Q5) of the rectifier circuit shown in fig. 8 is greatly improved in comparison with that of the rectifier circuit shown in fig. 1 (efficiency curve Q2) in the case of a high input voltage, but also faces the problem of gradual efficiency decrease as the voltage increases, and the rectifier circuit using ac amplitude modulation shown in fig. 5 (efficiency curve Q4) can effectively solve the problem, so that the energy conversion efficiency is basically maintained in a high efficiency state, and the efficiency curves Q4 and Q5 are compared in the case of a high input voltage. Compared with the efficiency curve Q1 of the circuit diagram of fig. 1, the efficiency curve Q3 obtained by the dc voltage modulation technique of fig. 2 is also kept in a high efficiency state at a high input voltage, and the effect of the energy conversion efficiency of the rectifier circuit shown in fig. 5 can be substantially equal to the effect of the energy conversion efficiency of the rectifier circuit shown in fig. 2 at a high input voltage. It should be noted that, in the rectifier circuit shown in fig. 5, the dc voltage components at the nodes C and D are fixed, so that the node V does not need to be adjusted BNi The "low input voltage" and the "high input voltage" referred to in this embodiment are relative to the curve change critical points of the curves Q4 and Q5, and there is no definite voltage value between the two as a boundary, and the critical point voltage may vary with different devices, processing technologies and working environments in practical applications.
Referring to fig. 9, fig. 9 shows a schematic circuit diagram of a rectifier circuit according to still another solution. The rectifier circuit shown in fig. 9 includes a bridge rectifier network 100 and a regulation network connected to the bridge rectifier network 100. The difference from the rectifier circuit shown in fig. 5 is that the second end of the regulating network is connected to the gate terminal of the second PMOS transistor, and the fourth end of the regulating network is connected to the gate terminal of the first PMOS transistor. The rectifier circuit shown in fig. 9 solves the same technical problems as the rectifier circuit shown in fig. 5, and achieves the same technical effects as the rectifier circuit shown in fig. 5. For avoiding redundancy, please refer to the above.
Referring to fig. 10, fig. 10 shows a schematic circuit diagram of a rectifier circuit in yet another solution. The rectifier circuit shown in fig. 10 includes a bridge rectifier network 100, and a first regulation network 201 and a second regulation network 202 connected to the bridge rectifier network 100. The connection between the first adjusting network 201 and the bridge rectifier network 100 may refer to the rectifier circuit shown in fig. 5, and the connection between the second adjusting network 202 and the bridge rectifier network 100 may refer to the rectifier circuit shown in fig. 9, which is not described herein. The rectifier circuit shown in fig. 10 solves the same technical problems as the rectifier circuit shown in fig. 5, and achieves the same technical effects as the rectifier circuit shown in fig. 5. For avoiding redundancy, please refer to the above.
It should be noted that, in the above solutions:
the first low-pass filter can adopt an RC filter or an LC filter, namely, the first resistor can be replaced by a first inductor, and the second resistor can be replaced by a second inductor; similarly, the second low-pass filter may adopt an RC filter or an LC filter, that is, the third resistor may be replaced by a third inductor, and the fourth resistor may be replaced by a fourth inductor.
The voltage-controlled capacitor may be formed by a MOS transistor, for example, a drain terminal and a source terminal of the MOS transistor are connected to each other and then used as a first terminal of the voltage-controlled capacitor, and a gate terminal of the MOS transistor is used as a second terminal of the voltage-controlled capacitor. The relationship between the voltage value and the capacitance value is shown in fig. 11, and the voltage between Vth and Vfb can be selected as the voltage regulation range.
It is worth mentioning that the rectifier circuits shown in fig. 2, 5, 9 and 10 can be operated in cascade, for example, fig. 12 shows a schematic circuit diagram of a rectifier including an adaptive feedback adjusting module and a plurality of cascade rectifier circuits, a second dc signal terminal of a previous rectifier circuit is connected to a first dc signal terminal of a next rectifier circuit, and first ac signal terminals of all the cascade rectifier circuits are connected to a first dc signal terminal of a next rectifier circuitThe first ends of the alternating current signal sources are connected, the second alternating current signal ends of all the rectifying circuits are connected with the second ends of the alternating current signal sources, and the self-adaptive feedback adjusting module is provided with a plurality of output ends and used for outputting adjusting signals. The self-adaptive feedback adjusting module can adjust the voltage to the node V according to different rectifying circuits BNi Node V BCNi Or node V BPNi And sending a regulating signal, thereby obtaining higher output power and energy conversion efficiency.
The embodiment also provides an electronic device comprising the rectifying circuit. The electronic equipment can be wireless energy transmission equipment, internet of things radio frequency energy collection equipment and the like.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.

Claims (10)

1. A regulation network, comprising:
a first capacitor;
a first end of the third capacitor is connected with a second end of the first capacitor, and the third capacitor is a voltage-controlled capacitor;
a second capacitor;
a first end of the fourth capacitor is connected with a second end of the second capacitor, and the fourth capacitor is a voltage-controlled capacitor;
the second end of the first resistor is connected to the second end of the fourth capacitor, and the second end of the second resistor is connected to the second end of the third capacitor;
the second low-pass filter comprises a sixth capacitor, a third resistor and a fourth resistor, wherein the second end of the sixth capacitor is connected to the first end of the third resistor and the first end of the fourth resistor, the second end of the third resistor is connected to the first end of the third capacitor, and the second end of the fourth resistor is connected to the first end of the fourth capacitor;
wherein the first terminal of the first capacitor is used as the first terminal of the regulation network, the second terminal of the third capacitor is used as the second terminal of the regulation network, the first terminal of the second capacitor is used as the third terminal of the regulation network, the second terminal of the fourth capacitor is used as the fourth terminal of the regulation network, the first terminal of the fifth capacitor is used as the fifth terminal of the regulation network, the first terminal of the sixth capacitor is used as the sixth terminal of the regulation network, and the second terminal of the sixth capacitor is used as the seventh terminal of the regulation network;
the first end of the adjusting network is used for connecting a first alternating current signal end, and the second end of the adjusting network is used for connecting the grid end of a second NMOS tube; the third end of the adjusting network is used for being connected with a second alternating current signal end, the fourth end of the adjusting network is used for being connected with a grid end of a first NMOS (N-channel metal oxide semiconductor) tube, the fifth end and the sixth end of the adjusting network are used for being connected with a first direct current signal end, and the seventh end of the adjusting network is used for receiving an adjusting signal.
2. The regulation network of claim 1 wherein the first resistance is replaced with a first inductance and the second resistance is replaced with a second inductance.
3. The regulating network according to claim 1 or 2, characterized in that the third resistance is replaced by a third inductance and the fourth resistance is replaced by a fourth inductance.
4. A rectifier circuit comprising a bridge rectifier network and a regulating network as claimed in any one of claims 1 to 3, said bridge rectifier network being connected to said regulating network.
5. The rectifier circuit according to claim 4, wherein the bridge rectifier network has a first ac signal terminal, a second ac signal terminal, a first dc signal terminal, and a second dc signal terminal, and the bridge rectifier network comprises a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor;
the drain end of the first NMOS tube is connected to the first alternating current signal end, and the source end of the first NMOS tube is connected to the first direct current signal end;
the drain end of the second NMOS tube is connected to the second alternating current signal end, and the source end of the second NMOS tube is connected to the first direct current signal end;
the drain end of the first PMOS tube is connected to the first alternating current signal end, the gate end of the first PMOS tube is connected to the second alternating current signal end, and the source end of the first PMOS tube is connected to the second direct current signal end;
the drain end of the second PMOS tube is connected to the second alternating current signal end, the gate end of the second PMOS tube is connected to the first alternating current signal end, and the source end of the second PMOS tube is connected to the second direct current signal end;
the first end of the adjusting network is connected to the first alternating current signal end, and the second end of the adjusting network is connected to the gate end of the second NMOS tube; the third end of the adjusting network is connected to the second alternating current signal end, the fourth end of the adjusting network is connected to the grid end of the first NMOS tube, the fifth end and the sixth end of the adjusting network are connected to the first direct current signal end, and the seventh end of the adjusting network is used for receiving adjusting signals.
6. The rectifier circuit of claim 4 wherein the bridge rectifier network has a first AC signal terminal, a second AC signal terminal, a first DC signal terminal, and a second DC signal terminal, the bridge rectifier network comprises a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor;
the drain end of the first NMOS tube is connected to the first alternating current signal end, the gate end of the first NMOS tube is connected to the second alternating current signal end, and the source end of the first NMOS tube is connected to the first direct current signal end;
the drain terminal of the second NMOS tube is connected to the second alternating current signal terminal, the gate terminal of the second NMOS tube is connected to the first alternating current signal terminal, and the source terminal of the second NMOS tube is connected to the first direct current signal terminal;
the drain end of the first PMOS tube is connected to the first alternating current signal end, the gate end of the first PMOS tube is connected to the second alternating current signal end, and the source end of the first PMOS tube is connected to the second direct current signal end;
the drain end of the second PMOS tube is connected to the second alternating current signal end, the gate end of the second PMOS tube is connected to the first alternating current signal end, and the source end of the second PMOS tube is connected to the second direct current signal end;
the first end of the adjusting network is connected to the first alternating current signal end, and the second end of the adjusting network is connected to the grid end of the second PMOS tube; the third end of the adjusting network is connected to the second alternating current signal end, the fourth end of the adjusting network is connected to the grid end of the first PMOS tube, the fifth end and the sixth end of the adjusting network are connected to the first direct current signal end, and the seventh end of the adjusting network is used for receiving adjusting signals.
7. The rectifier circuit according to claim 4, wherein the number of the regulating networks is two, one of which is a first regulating network and the other of which is a second regulating network;
the bridge type rectification network is provided with a first alternating current signal end, a second alternating current signal end, a first direct current signal end and a second direct current signal end and comprises a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first PMOS (P-channel metal oxide semiconductor) tube and a second PMOS tube;
the drain end of the first NMOS tube is connected to the first alternating current signal end, the gate end of the first NMOS tube is connected to the second alternating current signal end, and the source end of the first NMOS tube is connected to the first direct current signal end;
the drain end of the second NMOS tube is connected to the second alternating current signal end, the gate end of the second NMOS tube is connected to the first alternating current signal end, and the source end of the second NMOS tube is connected to the first direct current signal end;
the drain end of the first PMOS tube is connected to the first alternating current signal end, the gate end of the first PMOS tube is connected to the second alternating current signal end, and the source end of the first PMOS tube is connected to the second direct current signal end;
the drain end of the second PMOS tube is connected to the second alternating current signal end, the gate end of the second PMOS tube is connected to the first alternating current signal end, and the source end of the second PMOS tube is connected to the second direct current signal end;
the first end of the first adjusting network is connected to the first alternating current signal end, and the second end of the first adjusting network is connected to the gate end of the second NMOS tube; a third end of the first adjusting network is connected to the second alternating current signal end, a fourth end of the first adjusting network is connected to a gate end of the first NMOS tube, a fifth end and a sixth end of the first adjusting network are connected to the first direct current signal end, and a seventh end of the first adjusting network is used for receiving a first adjusting signal;
the first end of the second regulating network is connected to the first alternating current signal end, and the second end of the second regulating network is connected to the gate end of the second PMOS tube; the third end of the second adjusting network is connected to the second alternating current signal end, the fourth end of the second adjusting network is connected to the gate end of the first PMOS tube, the fifth end and the sixth end of the second adjusting network are connected to the first direct current signal end, and the seventh end of the second adjusting network is used for receiving a second adjusting signal.
8. The rectifier circuit according to claim 4, wherein a seventh capacitor is connected to the first ac signal terminal, and an eighth capacitor is connected to the second ac signal terminal.
9. The rectifier circuit according to any one of claims 5 to 7, wherein a first filter capacitor is connected to the second DC signal terminal.
10. An electronic device characterized by comprising the rectifier circuit according to any one of claims 4 to 9.
CN202210261236.5A 2022-03-16 2022-03-16 Adjusting network, rectifying circuit and electronic equipment Active CN114614657B (en)

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