CN107248847B - Differential reference voltage-controlled oscillator - Google Patents
Differential reference voltage-controlled oscillator Download PDFInfo
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- CN107248847B CN107248847B CN201710366566.XA CN201710366566A CN107248847B CN 107248847 B CN107248847 B CN 107248847B CN 201710366566 A CN201710366566 A CN 201710366566A CN 107248847 B CN107248847 B CN 107248847B
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- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
- H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
- H03B5/36—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
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Abstract
The invention discloses a differential reference ratio voltage-controlled oscillator which comprises a resonant circuit, a first negative resistance circuit, a second negative resistance circuit and a negative resistance enhancing circuit. The resonant circuit is an inductance-capacitance parallel resonance structure which determines the oscillation frequency of the oscillator and provides a frequency tuning function; the first negative resistance circuit and the second negative resistance circuit are used for generating negative resistance so as to offset resistive loss of the resonance circuit, and therefore stable oscillation output is generated; the negative resistance enhancing circuit is used for further improving the negative resistance of the active circuit of the oscillator and shortening the oscillation starting time of the oscillator; and two ports of the resonance circuit are output ports of differential oscillation signals. The invention can output single-ended oscillation amplitude exceeding the power supply voltage under lower power supply voltage and provide good phase noise performance; the method has the characteristics of low voltage operation, high oscillation amplitude, low phase noise and short oscillation starting time.
Description
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a differential reference ratio voltage-controlled oscillator.
Background
A voltage-controlled oscillator (VCO) is one of the key components in a wireless transceiver, and plays a crucial role in the performance of the system. The phase noise of the vco will degrade the system performance by mixing with the reciprocity of out-of-band interference, degrading the error vector magnitude of the signal, and raising the receive noise floor of a simultaneous co-frequency full duplex system.
As feature sizes of Complementary Metal Oxide Semiconductor (CMOS) processes continue to shrink, the voltage endurance of MOS field effect transistors (MOSFETs) also continues to decrease, forcing the power supply voltage of the chips to continue to decrease. However, the lower supply voltage severely limits the performance of the voltage controlled oscillator: first, the oscillation amplitude of the VCO is limited by the supply voltage, and the remote phase noise (1/f) of the VCO2Region) is inversely proportional to the power of the oscillating signal and thus its remote phase noise performance is deteriorated. Second, the lower gate-source bias voltage causes the transistor to operate in the sub-threshold region, making the start-up of the oscillator more difficult. Finally, the low oscillation swing of the vco increases the power consumption of the lo buffer, since the lo buffer needs to provide the mixer with the rail-to-rail lo signal.
A colpitts voltage controlled oscillator has excellent phase noise performance due to the pulse operation mode of its transistor, and thus is widely used in wireless transceiving systems, and a typical drain-source feedback differential colpitts voltage controlled oscillator structure is shown in fig. 1. However, this structure suffers from the problem of difficulty in starting up under low voltage operating conditions, and the output swing of the oscillator is also limited by the supply voltage. To increase the output swing of the oscillator at low voltage conditions, the current major approaches include the use of transformer feedback techniques and the use of additional inductors. Fig. 2(a) shows a low-voltage cross-coupled NMOS voltage-controlled oscillator structure based on transformer feedback, in which both the drain and the source of the NMOS transistor have inductors, so that both the drain voltage and the source voltage can exceed the power rail, thereby achieving the purpose of increasing the oscillation swing and reducing the phase noise. This increases the circuit design difficulty of the structure, since the modeling of the on-chip transformer is complex. Fig. 2(b) shows a differential reference voltage-controlled oscillator structure with enhanced swing, which can make the oscillating voltage lower than the ground level by adding extra inductance to the source of the NMOS transistor. However, the extra inductor occupies a larger chip area, thereby increasing the chip cost.
Disclosure of Invention
The invention provides a differential reference-ratio voltage-controlled oscillator for solving the technical problems, and the differential reference-ratio voltage-controlled oscillator realizes excellent performances of high oscillation amplitude, low phase noise and short oscillation starting time under the condition of not using an additional passive device.
The technical scheme adopted by the invention is as follows: a differential colpitts voltage controlled oscillator comprising: the circuit comprises a first negative resistance circuit, a second negative resistance circuit, a negative resistance enhancing circuit and a resonant circuit; the resonance circuit is an inductance-capacitance parallel resonance structure and determines the oscillation frequency of the oscillator; the first negative resistance circuit and the second negative resistance circuit are used for generating negative resistance to offset resistive loss of the resonance circuit, so that stable oscillation output is generated; the negative resistance enhancing circuit is used for improving the negative resistance of the oscillator and reducing the starting difficulty;
the first end of the first negative resistance circuit is connected with the fifth end of the negative resistance enhancement circuit, and the first negative resistance circuit is connected with the fifth end of the negative resistance enhancement circuitThe second end of the negative resistance circuit is connected with the first end of the resonant circuit; the second end of the resonant circuit is connected with the second end of the second negative resistance circuit, and the third end of the resonant circuit is connected with a power supply VDDThe fourth end of the resonant circuit is connected with a frequency tuning voltage; the first end of the second negative resistance circuit is connected with the fifth end of the negative resistance enhancing circuit; the third end of the first negative resistance circuit is connected with the first end of the negative resistance enhancing circuit, and the second end of the first negative resistance circuit is connected with the second end of the negative resistance enhancing circuit; the third end of the second negative resistance circuit is connected with the third end of the negative resistance enhancing circuit, and the second end of the second negative resistance circuit is connected with the fourth end of the negative resistance enhancing circuit; and the fifth end of the negative resistance enhancing circuit is grounded.
Further, the resonance circuit includes: a first inductor, a second inductor, a first varactor, and a second varactor; a first end of the first varactor is connected with a first end of a first inductor, and the first end of the first varactor and the first end of the first inductor are used as a first end of a resonant circuit together for outputting a first oscillation signal; the second end of the first inductor is connected with the first end of the second inductor, and the first end and the second end of the first inductor are used as the third end of the resonant circuit; a second end of the second inductor is connected with a first end of a second varactor and is used as a second end of the resonant circuit to output a second oscillation signal; and the second end of the second variable capacitor is connected with the second end of the first variable capacitor and is used as the fourth end of the resonant circuit together.
Further, the first negative resistance circuit includes: the first NMOS transistor, the first capacitor and the second capacitor; the grid electrode of the first NMOS transistor is used as the second end of the first negative resistance circuit, and the drain electrode of the first NMOS transistor is connected with the power supply VDDThe source electrode of the first NMOS transistor is connected with the first end of the first capacitor; the source electrode of the first NMOS transistor is connected with the body end of the first NMOS transistor and is used as the third end of the first negative resistance circuit; the second end of the first capacitor is connected with the grid electrode of the first NMOS transistor; the source electrode of the first NMOS transistor is also connected with the first end of the second capacitor; and the second end of the second capacitor is used as the first end of the first negative resistance circuit.
Further, the second negative resistance circuit includes: second NMOS crystalA transistor, a third capacitor and a fourth capacitor; the grid electrode of the second NMOS transistor is used as the second end of the second negative resistance circuit, and the drain electrode of the second NMOS transistor is connected with the power supply VDDThe source electrode of the second NMOS transistor is connected with the first end of the third capacitor; the source electrode of the second NMOS transistor is connected with the body end of the second NMOS transistor and is used as the third end of the second negative resistance circuit; the second end of the third capacitor is connected with the grid electrode of the second NMOS transistor; the source electrode of the second NMOS transistor is also connected with the first end of the fourth capacitor; and the second end of the fourth capacitor is used as the first end of the second negative resistance circuit.
Further, the negative resistance boost circuit includes: a third NMOS transistor and a fourth NMOS transistor; the drain electrode of the third NMOS transistor is used as the first end of the negative resistance enhancing circuit, and the grid electrode of the third NMOS transistor is used as the fourth end of the negative resistance enhancing circuit; the source electrode of the third NMOS transistor is connected with the source electrode of the fourth NMOS transistor and is used as the fifth end of the negative resistance enhancing circuit together; the body end of the third NMOS transistor is connected with the drain electrode of the fourth NMOS transistor; the drain electrode of the fourth NMOS transistor is used as the third end of the negative resistance enhancement circuit, and the grid electrode of the fourth NMOS transistor is used as the second end of the negative resistance enhancement circuit; and the body end of the fourth NMOS transistor is connected with the drain electrode of the third NMOS transistor.
The other technical scheme of the invention is as follows: a differential colpitts voltage controlled oscillator, comprising: the circuit comprises a first negative resistance circuit, a second negative resistance circuit, a negative resistance enhancing circuit and a resonant circuit; the resonance circuit is an inductance-capacitance parallel resonance structure and determines the oscillation frequency of the oscillator; the first negative resistance circuit and the second negative resistance circuit are used for generating negative resistance to offset resistive loss of the resonance circuit, so that stable oscillation output is generated; the negative resistance enhancing circuit is used for improving the negative resistance of the oscillator and reducing the starting difficulty;
the first end of the first negative resistance circuit is connected with the fifth end of the negative resistance enhancing circuit, and the second end of the first negative resistance circuit is connected with the first end of the resonant circuit; the second end of the resonant circuit is connected with the second end of the second negative resistance circuit, the third end of the resonant circuit is grounded,the fourth end of the resonant circuit is connected with a frequency tuning voltage; the first end of the second negative resistance circuit is connected with the fifth end of the negative resistance enhancing circuit; the third end of the first negative resistance circuit is connected with the first end of the negative resistance enhancing circuit, and the second end of the first negative resistance circuit is connected with the second end of the negative resistance enhancing circuit; the third end of the second negative resistance circuit is connected with the third end of the negative resistance enhancing circuit, and the second end of the second negative resistance circuit is connected with the fourth end of the negative resistance enhancing circuit; the fifth end of the negative resistance enhancing circuit is connected with a power supply VDD。
Further, the resonance circuit includes: a first inductor, a second inductor, a first varactor, and a second varactor; a first end of the first varactor is connected with a first end of a first inductor, and the first end of the first varactor and the first end of the first inductor are used as a first end of a resonant circuit together for outputting a first oscillation signal; the second end of the first inductor is connected with the first end of the second inductor, and the first end and the second end of the first inductor are used as the third end of the resonant circuit; a second end of the second inductor is connected with a first end of a second varactor and is used as a second end of the resonant circuit to output a second oscillation signal; and the second end of the second variable capacitor is connected with the second end of the first variable capacitor and is used as the fourth end of the resonant circuit together.
Further, the first negative resistance circuit includes: the first PMOS transistor, the first capacitor and the second capacitor; the grid electrode of the first PMOS transistor is used as the second end of the first negative resistance circuit, the drain electrode of the first PMOS transistor is grounded, the source electrode of the first PMOS transistor is used as the third end of the first negative resistance circuit, and the source electrode of the first PMOS transistor is connected with the first end of the first capacitor; the source electrode of the first PMOS transistor is connected with the body end of the first PMOS transistor and is used as the third end of the first negative resistance circuit; the second end of the first capacitor is connected with the grid electrode of the first PMOS transistor; the source electrode of the first PMOS transistor is also connected with the first end of the second capacitor; and the second end of the second capacitor is used as the first end of the first negative resistance circuit.
Further, the second negative resistance circuit includes: a second PMOS transistor, a third capacitor and a fourth capacitor; the grid electrode of the second PMOS transistor is used as a second end of the second negative resistance circuit, the drain electrode of the second PMOS transistor is grounded, the source electrode of the second PMOS transistor is used as a third end of the second negative resistance circuit, and the source electrode of the second PMOS transistor is connected with the first end of the third capacitor; the source electrode of the second PMOS transistor is connected with the body end of the second PMOS transistor and is used as the third end of the second negative resistance circuit; the second end of the third capacitor is connected with the grid electrode of the second PMOS transistor; the source electrode of the second PMOS transistor is also connected with the first end of the fourth capacitor; and the second end of the fourth capacitor is used as the first end of the second negative resistance circuit.
Further, the negative resistance boost circuit includes: a third PMOS transistor and a fourth PMOS transistor; the drain electrode of the third PMOS transistor is used as the first end of the negative resistance enhancement circuit, and the grid electrode of the third PMOS transistor is used as the fourth end of the negative resistance enhancement circuit; the source electrode of the third PMOS transistor is connected with the source electrode of the fourth PMOS transistor and is used as the fifth end of the negative resistance enhancing circuit together; the body end of the third PMOS transistor is connected with the drain electrode of the fourth PMOS transistor; the drain electrode of the fourth PMOS transistor is used as the third end of the negative resistance enhancement circuit, and the grid electrode of the fourth PMOS transistor is used as the second end of the negative resistance enhancement circuit; and the body end of the fourth PMOS transistor is connected with the drain electrode of the third PMOS transistor.
The invention has the beneficial effects that: according to the differential reference voltage-controlled oscillator, the tailless current source structure is adopted, so that the contribution of a tail current source to the phase noise of the oscillator is eliminated, and the minimum power supply voltage required by the oscillator is reduced; by adjusting the capacitance voltage division ratio, the oscillator can obtain an oscillation output swing exceeding a power supply rail under the condition of low power supply voltage, so that the far-end phase noise performance of the oscillator is improved; the node with lower oscillation amplitude is obtained by utilizing the tap capacitor inherent in the structure of the colpitts oscillator, so that the problem of forward conduction of a transistor body-drain parasitic diode and a body-source parasitic diode caused by a dynamic body bias technology under the condition of high output oscillation amplitude is solved; meanwhile, the dynamic body bias technology also improves the negative resistance of the active circuit and shortens the oscillation starting time; because the transistors in the negative resistance enhancement circuit are operated in a switching state, and the transistors in the first negative resistance circuit and the second negative resistance circuitThe source of the transistor has no common mode node, so that the oscillator has excellent 1/f3Phase noise performance; in addition, the invention does not need to use a complex transformer feedback technology or an additional inductor to improve the oscillation amplitude, so the occupied area of a chip is small, and the cost is low; in summary, the differential reference voltage controlled oscillator of the present invention can achieve the characteristics of high output swing and low phase noise under the low power supply voltage operating condition, and does not need to use additional passive devices.
Drawings
Fig. 1 is a block diagram of a conventional differential colpitts oscillator circuit.
Fig. 2 is a structural diagram of a conventional low-voltage high-swing voltage-controlled oscillator:
fig. 2(a) is an NMOS cross-coupled vco based on transformer feedback, and fig. 2(b) is a colpitts vco using an additional inductor.
Fig. 3 is a circuit structure diagram of a differential reference voltage-controlled oscillator according to the present invention.
Fig. 4 is a circuit structure diagram of another differential reference voltage-controlled oscillator according to the present invention.
Fig. 5 is a circuit configuration diagram of an active circuit portion of the differential reference voltage controlled oscillator of fig. 3.
FIG. 6 shows the body-side current as a function of the body-side voltage V for an NMOS transistor with a size of 2 μm/0.18 μmbsThe curve of the change.
Fig. 7 is a schematic diagram of voltage waveforms at various nodes of a differential colpitts voltage controlled oscillator shown in fig. 3.
Fig. 8 is a simulation result of steady-state voltage and current waveforms of a differential reference voltage-controlled oscillator according to the present invention.
Fig. 9 is a simulation result of phase noise performance of the differential reference ratio voltage-controlled oscillator provided by the invention at an oscillation frequency of 3.76 GHz.
Fig. 10 is a circuit structure diagram of a differential reference voltage controlled oscillator based on BJT/HBT transistors according to the present invention.
Fig. 11 is a circuit structure diagram of a differential reference voltage controlled oscillator based on NPN BJT transistors and NMOS transistors according to the present invention.
Detailed Description
In order to facilitate the understanding of the technical contents of the present invention by those skilled in the art, the present invention will be further explained with reference to the accompanying drawings.
As shown in fig. 3, which is one of the solutions of the present invention, a differential reference voltage controlled oscillator includes: a first negative resistance circuit 101, a second negative resistance circuit 102, a negative resistance enhancement circuit 103, and a resonance circuit 104; the resonant circuit 104 is an inductance-capacitance parallel resonance structure, determines the oscillation frequency of the oscillator and provides a frequency tuning function; the first negative resistance circuit 101 and the second negative resistance circuit 102 are used for generating negative resistance to counteract resistive loss of the resonance circuit 104, so as to generate stable oscillation output; the negative resistance enhancing circuit 103 is used for further improving the negative resistance of the active circuit of the oscillator, so that the oscillation starting time of the oscillator is shortened;
the first end of the first negative resistance circuit 101 is connected with the fifth end of the negative resistance enhancement circuit 103, and the second end of the first negative resistance circuit 101 is connected with the first end of the resonant circuit 104; the second terminal of the resonant circuit 104 is connected to the second terminal of the second negative resistance circuit 102, and the third terminal of the resonant circuit 104 is connected to the power supply VDDThe fourth terminal of the resonant circuit 104 is connected to a frequency tuning voltage Vtune(ii) a The first end of the second negative resistance circuit 102 is connected with the fifth end of the negative resistance enhancement circuit 103; the third end of the first negative resistance circuit 101 is connected with the first end of the negative resistance enhancement circuit 103, and the second end of the first negative resistance circuit 101 is connected with the second end of the negative resistance enhancement circuit 103; a third end of the second negative resistance circuit 102 is connected with a third end of the negative resistance enhancement circuit 103, and a second end of the second negative resistance circuit 102 is connected with a fourth end of the negative resistance enhancement circuit 103; the fifth terminal of the negative resistance enhancing circuit 103 is grounded.
As shown in fig. 3, the resonant circuit 104 includes: first inductance L1A second inductor L2A first varactor Cvar1And a second varactor Cvar2(ii) a The first varactor Cvar1First terminal and first inductor L1Are connected together as a first terminal V of the resonant circuit 104opFor outputting a first oscillation signal; the first inductor L1Second terminal and second inductor L2Are connected together as a third terminal of the resonant circuit 104; the second inductor L2Second terminal of and a second varactor Cvar2Are connected together as a second terminal V of the resonant circuit 104onFor outputting a second oscillation signal; the second varactor Cvar2Second terminal of and first varactor Cvar1Are connected together as a fourth terminal of the resonant circuit 104.
As shown in fig. 3, the first negative resistance circuit 101 includes: first NMOS transistor M1A first capacitor C1And a second capacitor C2(ii) a First NMOS transistor M1As a second terminal of the first negative resistance circuit 101, a first NMOS transistor M1Drain electrode of the transistor is connected with a power supply VDDFirst NMOS transistor M1Source electrode of and the first capacitor C1Is connected with the first end of the first connecting pipe; first NMOS transistor M1Source and M of1Is connected to be used as a third end of the first negative resistance circuit 101; a first capacitor C1And the first NMOS transistor M1The gate of (1) is connected; first NMOS transistor M1And a second capacitor C2Is connected with the first end of the first connecting pipe; second capacitor C2As a first terminal of the first negative resistance circuit 101.
As shown in fig. 3, the second negative resistance circuit 102 includes: second NMOS transistor M2A third capacitor C3And a fourth capacitance C4(ii) a Second NMOS transistor M2As a second terminal of the second negative resistance circuit 102, and a second NMOS transistor M2Drain electrode of the transistor is connected with a power supply VDDSecond NMOS transistor M2Source electrode of and third capacitor C3Is connected with the first end of the first connecting pipe; second NMOS transistor M2Source and M of2Is connected to serve as a third terminal of the second negative resistance circuit 102; third capacitor C3And the second end of the second NMOS transistor M2The gate of (1) is connected; second NMOS transistor M2And a fourth capacitor C4Is connected with the first end of the first connecting pipe; fourth capacitor C4As a first terminal of the second negative resistance circuit 102.
As shown in fig. 3, the negative resistance boost circuit 103 includes: third NMOS transistor M3And a fourth NMOS transistor M4(ii) a Third NMOS transistor M3As a first terminal of the negative resistance boost circuit 103, a third NMOS transistor M3As a fourth terminal of the negative resistance boost circuit 103; third NMOS transistor M3And the fourth NMOS transistor M4Is connected to as the fifth terminal of the negative resistance enhancing circuit 103, and a third NMOS transistor M3And the fourth NMOS transistor M4Is connected with the drain electrode of the transistor; fourth NMOS transistor M4As a third terminal of the negative resistance enhancing circuit 103, a fourth NMOS transistor M4As a second terminal of the negative resistance boost circuit 103; fourth NMOS transistor M4And the body terminal of the third NMOS transistor M3Is connected to the drain of (1).
Another aspect of the present invention is shown in fig. 4, which is a differential reference voltage controlled oscillator, including: a first negative resistance circuit 201, a second negative resistance circuit 202, a negative resistance enhancement circuit 203, and a resonant circuit 204; the resonant circuit 204 is an inductance-capacitance parallel resonance structure, determines the oscillation frequency of the oscillator and provides a frequency tuning function; the first negative resistance circuit 201 and the second negative resistance circuit 202 are used for generating negative resistance to counteract resistive loss of the resonance circuit 204, so as to generate stable oscillation output; the negative resistance enhancing circuit 203 is used for further improving the negative resistance of the active circuit of the oscillator, so that the oscillation starting time of the oscillator is shortened;
the first end of the first negative resistance circuit 201 is connected with the fifth end of the negative resistance enhancement circuit 203, and the second end of the first negative resistance circuit 201 is connected with the first end of the resonant circuit 204; the second end of the resonant circuit 204 is connected to the second end of the second negative resistance circuit 202, the third end of the resonant circuit 204 is grounded, and the fourth end of the resonant circuit 204 is connected to the frequency tuning voltage Vtune(ii) a The first end of the second negative resistance circuit 202 is connected with the fifth end of the negative resistance enhancement circuit 203; the third terminal of the first negative resistance circuit 201 is connected with the first terminal of the negative resistance enhancement circuit 203, and the second terminal of the first negative resistance circuit 201 is connected withThe second end of the negative resistance enhancing circuit 203 is connected; the third end of the second negative resistance circuit 202 is connected with the third end of the negative resistance enhancement circuit 203, and the second end of the second negative resistance circuit 202 is connected with the fourth end of the negative resistance enhancement circuit 203; the fifth end of the negative resistance enhancing circuit 203 is connected with a power supply VDD。
As shown in fig. 4, the resonant circuit 204 includes: first inductance L1A second inductor L2A first varactor Cvar1And a second varactor Cvar2(ii) a The first varactor Cvar1First terminal and first inductor L1Are connected together as a first terminal V of the resonant circuit 204opFor outputting a first oscillation signal; the first inductor L1Second terminal and second inductor L2Are connected together as a third terminal of the resonant circuit 204; the second inductor L2Second terminal of and a second varactor Cvar2Are connected together as a second terminal V of the resonant circuit 204onFor outputting a second oscillation signal; the second varactor Cvar2Second terminal of and first varactor Cvar1Are connected together as a fourth terminal of the resonant circuit 204.
As shown in fig. 4, the first negative resistance circuit 201 includes: first PMOS transistor M1A first capacitor C1And a second capacitor C2(ii) a The first PMOS transistor M1As a second terminal of the first negative resistance circuit 201, a first PMOS transistor M1Is grounded, a first PMOS transistor M1As the third terminal of the first negative resistance circuit 201, a first PMOS transistor M1Source electrode of and the first capacitor C1Is connected with the first end of the first connecting pipe; the first PMOS transistor M1And the first PMOS transistor M1Is connected to serve as the third terminal of the first negative resistance circuit 201; the first capacitor C1Second terminal of and first PMOS transistor M1The gate of (1) is connected; the first PMOS transistor M1And a second capacitor C2Is connected with the first end of the first connecting pipe; the second capacitor C2As a first terminal of the first negative resistance circuit 201.
As shown in fig. 4, the second negative resistance circuit 202 includes: second PMOS transistor M2A third capacitor C3And a fourth capacitance C4(ii) a The second PMOS transistor M2As a second terminal of the second negative resistance circuit 202, and a second PMOS transistor M2Is grounded, a second PMOS transistor M2As a third terminal of the second negative resistance circuit 202, a second PMOS transistor M2Source electrode of and third capacitor C3Is connected with the first end of the first connecting pipe; the second PMOS transistor M2And the second PMOS transistor M2Is connected to serve as a third terminal of the second negative resistance circuit 202; the third capacitor C3Second terminal of and second PMOS transistor M2The gate of (1) is connected; the second PMOS transistor M2And a fourth capacitor C4Is connected with the first end of the first connecting pipe; the fourth capacitor C4As a first terminal of the second negative resistance circuit 202.
As shown in fig. 4, the negative resistance boost circuit 203 includes: third PMOS transistor M3And a fourth PMOS transistor M4(ii) a The third PMOS transistor M3As a first terminal of the negative resistance boost circuit 203, a third PMOS transistor M3As the fourth terminal of the negative resistance boost circuit 203; the third PMOS transistor M3And the fourth PMOS transistor M4Are connected to collectively serve as the fifth terminal of the negative resistance boosting circuit 203; the third PMOS transistor M3And the body terminal of the fourth PMOS transistor M4Is connected with the drain electrode of the transistor; the fourth PMOS transistor M4As the third terminal of the negative resistance enhancing circuit 203, and a fourth PMOS transistor M4As a second terminal of the negative resistance boost circuit 203; the fourth PMOS transistor M4And the body terminal of the third PMOS transistor M3Is connected to the drain of (1).
The invention is explained in the following by a specific workflow in conjunction with fig. 3:
first inductance L in resonant circuit 1041A second inductor L2A first varactor Cvar1And a second varactor Cvar2A parallel inductance capacitance resonance circuit is formed, and the resonance frequency of the oscillation circuit is determined; through to port VtuneApplying a variable voltage to change the first varactor Cvar1And a second varactor Cvar2The tuning function of the oscillation frequency is realized.
The first negative resistance circuit 101 and the second negative resistance circuit 102 form a main negative resistance circuit of the oscillator; capacitor C1And C2The capacitive divider is formed in the first NMOS transistor M1The gate and source of (a) form a positive feedback, thereby creating a negative resistance to compensate for the resistive losses of the resonant circuit 104; in the same way, capacitor C3And C4Forming a capacitive voltage divider at M2The gate and source of (a) form a positive feedback, thereby creating a negative resistance to compensate for the resistive losses of the resonant circuit 104; the first negative resistance circuit 101 and the second negative resistance circuit 102 pass through the capacitor C2And C4The coupling of the common ground terminal of (a) enables differential oscillation.
The negative resistance enhancing circuit 103 provides extra negative resistance in the oscillation starting process of the circuit, and enhances the total negative resistance of the active circuit part, thereby reducing the oscillation starting difficulty of the oscillator and shortening the oscillation starting time of the oscillator; m3And M4Respectively passing through low oscillation amplitude node VsnAnd VspImplementing dynamic body biasing, which dynamically reduces M3And M4While at the same time, also M3And M4The bulk transconductance of (a) is utilized to further enhance the negative resistance of the circuit.
High oscillation amplitude node V in the differential reference ratio voltage-controlled oscillatoropAnd VonA differential oscillating output signal is provided.
The principle of reducing the required power supply voltage and enhancing the negative resistance is as follows: with the NMOS transistor M in FIG. 33For example, its body terminal is connected to an NMOS transistor M2Is dynamically biased. When node VsnWhen the voltage of (3) is in positive half cycle, the NMOS transistor M can be obtained3Threshold voltage V ofth,M3Is composed of
Wherein, Vth0Is the intrinsic threshold voltage of the NMOS transistor, gamma denotes the bulk effect coefficient, phiFIs the work function, V, of the silicon substrates,DCDenotes an NMOS transistor M2Static bias voltage of source, VoRepresenting the single-ended output swing of the oscillator, omega being the oscillation angular frequency, n being the tapped capacitor C1、C2(and C)3、C4) Is given by
Wherein, C1＝C3、C2＝C4. From equation (1), the NMOS transistor M is formed by using a dynamic forward body bias structure3Is reduced. Similarly, NMOS transistor M4Is also dynamically adjusted, thus reducing the minimum supply voltage required for the circuit to start up.
Dynamic body biasing technique other than reducing NMOS transistor M3And M4In addition to the threshold voltage (and thus the minimum supply voltage required by the circuit), the difficulty of starting the oscillator is also reduced. FIG. 5 is a schematic diagram of the active circuit portion of the voltage controlled oscillator shown in FIG. 3, the differential admittance Y of which is obtained using a small signal equivalent circuit analysis methodINHas a real part of
Wherein, gm1And gm3Are respectively NMOS transistors M1/M2And M3/M4Small signal transconductance, gmb3Is an NMOS transistor M3/M4Small signal body transconductance. Similarly, the small signal conductance of the conventional drain-source feedback differential reference oscillator shown in FIG. 1 is
Wherein, gm1Is an NMOS transistor M1/M2Small signal transconductance.
Comparing the formula (3) with the formula (4) shows that: under the same bias condition, the negative conductance of the Copytz oscillator is improved by about 0.5{1+ (g) compared with the negative conductance of the traditional Copytz oscillatorm3+gmb3)/[(1–n)(gm1–gmb3)]}. Therefore, the reference oscillator has shorter oscillation starting time than the reference oscillator under the same power consumption; or at the same attack time, the power consumption of the present invention is lower than that of a z oscillator.
By appropriate selection of tap capacitance C1、C2(and C)3、C4) The voltage division ratio n of the oscillator can improve the output swing of the oscillator and reduce the phase noise of the oscillator. When the NMOS transistor M is as shown in FIG. 31/M2When entering into the triode region, the single-ended output swing V of the colpitts voltage-controlled oscillator of the inventionoCan be approximated as
Wherein, VDDAnd VSSupply voltage and low swing node V, respectivelysp/VsnThe steady state average voltage of. As can be seen from the formula (5): by choosing a smaller n, the output swing of the oscillator can be increased. Although a smaller n is not beneficial to the start-up of the circuit, the use of the negative resistance enhancement circuit reduces the difficulty of the start-up of the circuit to some extent, so that a smaller n can be selected to obtain a high output swing and a lower far-end phase noise.
When the output swing of the oscillator is large, the direct use of the high-swing node to realize the dynamic adjustment of the threshold voltage of the transistor may cause the body-drain and body-source parasitic diodes of the transistor to be in forward conduction, so that the quality factor of the resonant circuit may be significantly reduced, thereby deteriorating the phase noise performance of the oscillator. FIG. 6 shows an NMOS crystal with a width-to-length ratio of 2 μm/0.18 μmBody end current of tube is dependent on body source voltage VbsFrom the varying curves, it can be seen that: when V isbsAbove 0.8V, the body-side current of the transistor increases sharply, at which time the parasitic diode of the NMOS transistor is turned on in the forward direction. As shown in FIG. 7, the invention utilizes the inherent tap capacitance of the Colpitts oscillator to obtain the low swing node by combining two low swing nodes VspAnd VsnAre respectively connected to the NMOS transistors M4And M3The body terminal of the transistor realizes dynamic body bias, thereby avoiding the forward conduction problem of a transistor parasitic diode under high voltage.
With reference to fig. 7, the specific principle of the low phase noise characteristic of the present invention is as follows:
1. as known from the Lesson theory: the remote phase noise of the oscillator is inversely proportional to the power of the oscillating signal. By adjusting the ratio of the tap capacitors, the output swing of the differential reference oscillator can exceed the power rail, thereby reducing the phase noise (1/f) at the far end2Region);
2. from the pulse sensitivity function theory of Hajimiiri and Lee, it can be known that: pulsed mode of operation of the colpitts oscillator causes the NMOS transistor M to be turned on1And M2Is the largest when the output signal is at the peak, and the phase of the output oscillation signal is the least sensitive to noise at this time, so the NMOS transistor M1And M2The channel thermal noise is converted into less phase noise, so the Zetz oscillator has the characteristic of low phase noise;
3. the transistor flicker noise is related to the trapping/releasing process of the minority carrier by the trap of the silicon-gate-oxide contact surface, and the transistor working in the switch state has lower flicker noise by modulating the time constant of trapping/releasing. NMOS transistor M in negative resistance enhancement circuit3And M4Periodically operating in inversion region and accumulation region, the switch operation state reduces the transistor M3And M4Flicker noise of (2); furthermore, the use of dynamic body biasing techniques enables the NMOS transistor M to be formed3And M4Into the deep accumulation region in the off state, which further reduces its flicker noise and hence also the oscillatorNear end phase noise (1/f)3Region);
NMOS transistor M1And M2The sources of (a) are separated, i.e. there is no common mode node between them, so that the flicker noise up-conversion generated by the second harmonic at the common mode node is greatly suppressed, thereby improving the near-end phase noise performance of the oscillator.
The effect of the present invention is illustrated by specific experimental data, in this embodiment, the differential reference ratio voltage controlled oscillator circuit is implemented by TSMC 0.18 μm RF CMOS process, and is powered by 0.6V power supply, and the steady-state operating current of the circuit is 7.85 mA. To obtain a high oscillation swing, the value of the capacitive voltage division ratio n is chosen to be 1/5.
Fig. 8 shows the voltage waveforms at the nodes of the differential colpitts voltage controlled oscillator and the drain current waveforms of the four NMOS transistors shown in fig. 3, and it can be seen from the figure that: voltage controlled oscillator output node VopAnd VonThe swing of the power supply exceeds the power supply voltage and the ground, and high swing output is realized. Low swing node VspAnd VsnIs about 0.5V (lower than the supply voltage of 0.6V), thus avoiding dynamic body biasing of the NMOS transistor M3And M4The body-drain and body-source parasitic diodes are conducted in the forward direction.
Fig. 9 shows the simulation result of the phase noise performance of the differential reference ratio voltage-controlled oscillator at the oscillation frequency of 3.76 GHz: the phase noise at frequency offset of 10kHz/100kHz/1MHz is-77.89/-104.64/-127.66 dBc/Hz, and 1/f of the phase noise3The corner frequency is only 60 kHz. The Figure-of-Merit (FoM) of the oscillator obtained from equation (6) is 192.4dBc/Hz, taking into account the power consumption and phase noise performance of the VCO.
FoM＝20lg(f0/Δf)–10lg(Pdiss/1mW)–L(Δf) (6)
The above results indicate that the differential reference voltage-controlled oscillator of the present application exhibits excellent phase noise performance under low-voltage operating conditions, obtains a single-ended output swing exceeding a power supply voltage without using complicated transformer coupling or additional inductors, and has the advantages of low-voltage operation, high performance, and low cost.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. For those skilled in the art, the transistor M in the present invention1、M2、M3、M4It may also be a bipolar junction transistor BJT or a heterojunction bipolar transistor HBT, as shown in FIG. 10 by a transistor M1、M2、M3、M4Circuit connection schematic of Bipolar Junction Transistor (BJT) type, M1、M2、M3、M4The specific circuit connection selected as the heterojunction bipolar transistor HBT can also refer to the connection mode of fig. 10;
and a transistor M1、M2、M3、M4Can be a combination of PMOS, NMOS, BJT, HBT, as shown in FIG. 11 as M1、M2The selected type is NPN type BJT, M3、M4The selection type is a schematic diagram of the connection of a combination circuit of an NMOS, and the technical effects of the application can be realized by the above deformation; in summary, the present disclosure is susceptible to various modifications and alternative forms. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (4)
1. A differential colpitts voltage controlled oscillator, comprising: the circuit comprises a first negative resistance circuit, a second negative resistance circuit, a negative resistance enhancing circuit and a resonant circuit; the resonance circuit is an inductance-capacitance parallel resonance structure and determines the oscillation frequency of the oscillator; the first negative resistance circuit and the second negative resistance circuit are used for generating negative resistance to offset resistive loss of the resonance circuit, so that stable oscillation output is generated; the negative resistance enhancing circuit is used for improving the negative resistance of the oscillator and reducing the starting difficulty;
the first end of the first negative resistance circuit is connected with the fifth end of the negative resistance enhancing circuit, and the second end of the first negative resistance circuit is connected with the first end of the resonant circuit(ii) a The second end of the resonant circuit is connected with the second end of the second negative resistance circuit, and the third end of the resonant circuit is connected with a power supply VDDThe fourth end of the resonant circuit is connected with a frequency tuning voltage; the first end of the second negative resistance circuit is connected with the fifth end of the negative resistance enhancing circuit; the third end of the first negative resistance circuit is connected with the first end of the negative resistance enhancing circuit, and the second end of the first negative resistance circuit is connected with the second end of the negative resistance enhancing circuit; the third end of the second negative resistance circuit is connected with the third end of the negative resistance enhancing circuit, and the second end of the second negative resistance circuit is connected with the fourth end of the negative resistance enhancing circuit; the fifth end of the negative resistance enhancing circuit is grounded;
the first negative resistance circuit includes: the first NMOS transistor, the first capacitor and the second capacitor; the grid electrode of the first NMOS transistor is used as the second end of the first negative resistance circuit, and the drain electrode of the first NMOS transistor is connected with the power supply VDDThe source electrode of the first NMOS transistor is connected with the first end of the first capacitor; the source electrode of the first NMOS transistor is connected with the body end of the first NMOS transistor and is used as the third end of the first negative resistance circuit; the second end of the first capacitor is connected with the grid electrode of the first NMOS transistor; the source electrode of the first NMOS transistor is also connected with the first end of the second capacitor; the second end of the second capacitor is used as the first end of the first negative resistance circuit;
the second negative resistance circuit includes: a second NMOS transistor, a third capacitor and a fourth capacitor; the grid electrode of the second NMOS transistor is used as the second end of the second negative resistance circuit, and the drain electrode of the second NMOS transistor is connected with the power supply VDDThe source electrode of the second NMOS transistor is connected with the first end of the third capacitor; the source electrode of the second NMOS transistor is connected with the body end of the second NMOS transistor and is used as the third end of the second negative resistance circuit; the second end of the third capacitor is connected with the grid electrode of the second NMOS transistor; the source electrode of the second NMOS transistor is also connected with the first end of the fourth capacitor; a second end of the fourth capacitor is used as a first end of a second negative resistance circuit;
the negative resistance boost circuit includes: a third NMOS transistor and a fourth NMOS transistor; the drain electrode of the third NMOS transistor is used as the first end of the negative resistance enhancing circuit, and the grid electrode of the third NMOS transistor is used as the fourth end of the negative resistance enhancing circuit; the source electrode of the third NMOS transistor is connected with the source electrode of the fourth NMOS transistor and is used as the fifth end of the negative resistance enhancing circuit together; the body end of the third NMOS transistor is connected with the drain electrode of the fourth NMOS transistor; the drain electrode of the fourth NMOS transistor is used as the third end of the negative resistance enhancement circuit, and the grid electrode of the fourth NMOS transistor is used as the second end of the negative resistance enhancement circuit; the body end of the fourth NMOS transistor is connected with the drain electrode of the third NMOS transistor;
the third NMOS transistor body terminal is dynamically biased by the source voltage of the second NMOS transistor and the fourth NMOS transistor body terminal is dynamically biased by the source voltage of the first NMOS transistor.
2. A differential colpitts voltage controlled oscillator as claimed in claim 1, wherein said resonant circuit comprises: a first inductor, a second inductor, a first varactor, and a second varactor; a first end of the first varactor is connected with a first end of a first inductor, and the first end of the first varactor and the first end of the first inductor are used as a first end of a resonant circuit together for outputting a first oscillation signal; the second end of the first inductor is connected with the first end of the second inductor, and the first end and the second end of the first inductor are used as the third end of the resonant circuit; a second end of the second inductor is connected with a first end of a second varactor and is used as a second end of the resonant circuit to output a second oscillation signal; and the second end of the second variable capacitor is connected with the second end of the first variable capacitor and is used as the fourth end of the resonant circuit together.
3. A differential colpitts voltage controlled oscillator, comprising: the circuit comprises a first negative resistance circuit, a second negative resistance circuit, a negative resistance enhancing circuit and a resonant circuit; the resonance circuit is an inductance-capacitance parallel resonance structure and determines the oscillation frequency of the oscillator; the first negative resistance circuit and the second negative resistance circuit are used for generating negative resistance to offset resistive loss of the resonance circuit, so that stable oscillation output is generated; the negative resistance enhancing circuit is used for improving the negative resistance of the oscillator and reducing the starting difficulty;
first negative resistance circuitThe end of the first negative resistance circuit is connected with the fifth end of the negative resistance enhancing circuit, and the second end of the first negative resistance circuit is connected with the first end of the resonant circuit; the second end of the resonant circuit is connected with the second end of the second negative resistance circuit, the third end of the resonant circuit is grounded, and the fourth end of the resonant circuit is connected with a frequency tuning voltage; the first end of the second negative resistance circuit is connected with the fifth end of the negative resistance enhancing circuit; the third end of the first negative resistance circuit is connected with the first end of the negative resistance enhancing circuit, and the second end of the first negative resistance circuit is connected with the second end of the negative resistance enhancing circuit; the third end of the second negative resistance circuit is connected with the third end of the negative resistance enhancing circuit, and the second end of the second negative resistance circuit is connected with the fourth end of the negative resistance enhancing circuit; the fifth end of the negative resistance enhancing circuit is connected with a power supply VDD；
The first negative resistance circuit includes: the first PMOS transistor, the first capacitor and the second capacitor; the grid electrode of the first PMOS transistor is used as the second end of the first negative resistance circuit, the drain electrode of the first PMOS transistor is grounded, the source electrode of the first PMOS transistor is used as the third end of the first negative resistance circuit, and the source electrode of the first PMOS transistor is connected with the first end of the first capacitor; the source electrode of the first PMOS transistor is connected with the body end of the first PMOS transistor and is used as the third end of the first negative resistance circuit; the second end of the first capacitor is connected with the grid electrode of the first PMOS transistor; the source electrode of the first PMOS transistor is also connected with the first end of the second capacitor; the second end of the second capacitor is used as the first end of the first negative resistance circuit;
the second negative resistance circuit includes: a second PMOS transistor, a third capacitor and a fourth capacitor; the grid electrode of the second PMOS transistor is used as a second end of the second negative resistance circuit, the drain electrode of the second PMOS transistor is grounded, the source electrode of the second PMOS transistor is used as a third end of the second negative resistance circuit, and the source electrode of the second PMOS transistor is connected with the first end of the third capacitor; the source electrode of the second PMOS transistor is connected with the body end of the second PMOS transistor and is used as the third end of the second negative resistance circuit; the second end of the third capacitor is connected with the grid electrode of the second PMOS transistor; the source electrode of the second PMOS transistor is also connected with the first end of the fourth capacitor; a second end of the fourth capacitor is used as a first end of a second negative resistance circuit;
the negative resistance boost circuit includes: a third PMOS transistor and a fourth PMOS transistor; the drain electrode of the third PMOS transistor is used as the first end of the negative resistance enhancement circuit, and the grid electrode of the third PMOS transistor is used as the fourth end of the negative resistance enhancement circuit; the source electrode of the third PMOS transistor is connected with the source electrode of the fourth PMOS transistor and is used as the fifth end of the negative resistance enhancing circuit together; the body end of the third PMOS transistor is connected with the drain electrode of the fourth PMOS transistor; the drain electrode of the fourth PMOS transistor is used as the third end of the negative resistance enhancement circuit, and the grid electrode of the fourth PMOS transistor is used as the second end of the negative resistance enhancement circuit; the body end of the fourth PMOS transistor is connected with the drain electrode of the third PMOS transistor;
the third PMOS transistor body terminal is dynamically biased by the source voltage of the second PMOS transistor and the fourth PMOS transistor body terminal is dynamically biased by the source voltage of the first PMOS transistor.
4. A differential colpitts voltage controlled oscillator as claimed in claim 3, wherein said resonant circuit comprises: a first inductor, a second inductor, a first varactor, and a second varactor; a first end of the first varactor is connected with a first end of a first inductor, and the first end of the first varactor and the first end of the first inductor are used as a first end of a resonant circuit together for outputting a first oscillation signal; the second end of the first inductor is connected with the first end of the second inductor, and the first end and the second end of the first inductor are used as the third end of the resonant circuit; a second end of the second inductor is connected with a first end of a second varactor and is used as a second end of the resonant circuit to output a second oscillation signal; and the second end of the second variable capacitor is connected with the second end of the first variable capacitor and is used as the fourth end of the resonant circuit together.
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| CN110719070B (en) * | 2019-09-29 | 2023-05-12 | 天津大学 | Low-power consumption voltage-controlled oscillator based on dynamic threshold technology |
| CN111277222B (en) * | 2020-02-17 | 2023-04-25 | 电子科技大学 | Current multiplexing voltage-controlled oscillator based on feedback of gate-source transformer |
| CN111628725B (en) * | 2020-06-19 | 2022-11-01 | 南京邮电大学 | LC voltage-controlled oscillator circuit with noise circulation |
| CN112653455A (en) * | 2020-12-04 | 2021-04-13 | 电子科技大学 | High-frequency low-power-consumption self-mixing millimeter wave voltage-controlled oscillator |
| CN114079428B (en) * | 2022-01-19 | 2022-04-22 | 成都明夷电子科技有限公司 | Tunable differential input cascode low-noise amplifier based on CMOS |
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