CN114613311A - 9T2C circuit for improving stability of display screen and driving method thereof - Google Patents
9T2C circuit for improving stability of display screen and driving method thereof Download PDFInfo
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- CN114613311A CN114613311A CN202210324384.7A CN202210324384A CN114613311A CN 114613311 A CN114613311 A CN 114613311A CN 202210324384 A CN202210324384 A CN 202210324384A CN 114613311 A CN114613311 A CN 114613311A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The invention discloses a 9T2C circuit for improving stability of a display screen and a driving method thereof.A grid electrode of a transistor T1 is connected with a first GIP output signal Gn-4, a grid electrode of a transistor T7 is connected with a second GIP output signal Gn +4, a drain electrode of a transistor T1 and a drain electrode of a transistor T7 are respectively and electrically connected with a grid electrode of a transistor T2, a drain electrode of a transistor T3, a grid electrode of a transistor T4, a grid electrode of a transistor T8, a grid electrode of a transistor T9 and one end of a capacitor C2, and a drain electrode of a transistor T2 is respectively and electrically connected with a grid electrode of a transistor T3, a grid electrode of a transistor T6 and one end of a capacitor C1; the other end of the capacitor C1 is grounded; the source of the transistor T3 is connected to the source of the transistor T8 and the drain of the transistor T9, respectively, and the source of the transistor T4, the drain of the transistor T5, the drain of the transistor T6, and the other end of the capacitor C2 are all connected to the third GIP output signal Gn. The invention effectively reduces the leakage current of the transistor T3, thereby improving the stability of the display screen.
Description
Technical Field
The invention relates to the technical field of panel display, in particular to a 9T2C circuit for improving stability of a display screen and a driving method thereof.
Background
In a display screen driving circuit, a TFT device often has the problem of electric leakage of the TFT device due to the influence of various factors, and once the potential of a key node position loses a required level, the display screen has abnormal display.
Disclosure of Invention
The invention aims to provide a 9T2C circuit for improving the stability of a display screen and a driving method thereof, which prevent a key node from influencing subsequent stage transmission due to the fact that the TFT electric leakage does not reach the standard level, achieve the purpose of improving poor picture difference of the display screen due to the electric leakage, and effectively improve the stability of the display screen.
The technical scheme adopted by the invention is as follows:
A9T 2C circuit for improving stability of a display screen comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a capacitor C1 and a capacitor C2, wherein a gate of the transistor T1 is connected with a first GIP output signal Gn-4, a gate of the transistor T7 is connected with a second GIP output signal Gn +4,
the drain of the transistor T1 and the drain of the transistor T7 are electrically connected to the gate of the transistor T2, the drain of the transistor T3, the gate of the transistor T4, the gate of the transistor T8, the gate of the transistor T9, and one end of the capacitor C2, respectively,
the drain of the transistor T2 is electrically connected to the gate of the transistor T3, the gate of the transistor T6 and one end of the capacitor C1, respectively; the other end of the capacitor C1 is grounded;
a source of the transistor T3 is connected to the source of the transistor T8 and the drain of the transistor T9 respectively,
the source of the transistor T4, the drain of the transistor T5, the drain of the transistor T6, and the other end of the capacitor C2 are all connected to the third GIP output signal Gn.
Further, the drain of the transistor T4 is connected to the first clock signal CK1, and the gate of the transistor T5 is connected to the second clock signal CK 5.
Further, the source of the transistor T1 and the drain of the transistor T8 are both connected to the positive electrode VGH of the power supply.
Further, the source of the transistor T2, the source of the transistor T5, the source of the transistor T6, the source of the transistor T7 and the source of the transistor T9 are all connected to the negative electrode VGL of the power supply.
Further, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, and the transistor T8 are all N-channel MOS transistors, and the transistor T9 is a P-channel MOS transistor.
A drive method of a 9T2C circuit for improving the stability of a display screen comprises a scanning cycle including a first time period, a second time period, a third time period, a fourth time period, a fifth time period, a sixth time period and a seventh time period; wherein the content of the first and second substances,
at a first time period t 1: the first clock signal CK1 is at high level, the capacitor C1 is charged, the potential of the first node P is changed to high level, the transistors T3 and T6 are turned on, the potential of the third GIP output signal Gn is pulled to low level, the second node Q is pulled to low level under the coupling action of the capacitor C2, and the transistor T9 is turned on;
at a second time period t 2: the first clock signal CK1 changes to low level, the potential at the point P of the first node changes to low level, and the transistors T3 and T6 are turned off;
at a third time period t 3: the first GIP output signal Gn-4 is at a high level, the second clock signal CK5 is at a high level, the transistors T1 and T5 are turned on, the second node Q point becomes a high potential, and the transistors T2, T4, and T8 are turned on; the third node R point becomes high;
during a fourth time period t 4: the first GIP output signal Gn-4 and the second clock signal CK5 become low level, the transistors T1 and T5 are turned off, and the second node Q point maintains high potential;
at a fifth time period t 5: the first clock signal CK1 changes to high level, the third GIP output signal Gn outputs high potential, the second node Q point is pulled down to higher potential under the coupling action of the capacitor C2, the transistor T8 keeps an opening state, the third node R point is high potential, even if T3 is greatly floated negatively due to Vth, the potential of the transistor T3 leaking into the Q point is still high potential, and the transistor T4 normally works;
at a sixth time period t 6: the first clock signal CK1 changes to low level, the third GIP output signal Gn changes to low level, and the existing potential of the second node Q point at the capacitor C2 drops to high level;
at a seventh time period t 7: the second GIP output signal Gn +4 and the second clock signal CK5 are at a high level, the transistor T7 is turned on to pull the potential at the second node Q point to a low level, the transistor T8 is turned off, the transistor T9 is turned on, and the third node R point becomes a low level.
By adopting the technical scheme, the leakage current of the TFT device depends on the relationship between the voltage difference between the gate voltage and the source voltage and the Vth, and when the driving process is T5, even if the Vth of the T3 device has negative drift, the fact that the voltage of the source (R point) of the T3 is increased when the R point is pulled to the high potential is equivalent to that of the source (R point) of the T3, the leakage current of the T3 is effectively reduced, and therefore the stability of the display screen is improved. In the GIP driving process, the invention prevents the key node from influencing the subsequent stage transmission because the TFT electric leakage cannot reach the quasi-position, achieves the aim of improving the poor picture caused by the electric leakage of the display screen, and effectively improves the stability of the display screen.
Drawings
The invention is described in further detail below with reference to the accompanying drawings and the detailed description;
FIG. 1 is a schematic diagram of a 9T2C circuit for improving the stability of a display panel according to the present invention;
fig. 2 is a timing diagram corresponding to the 9T2C circuit for improving the stability of the display panel according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
As shown in fig. 1, the invention discloses a 9T2C circuit for improving stability of a display screen, which includes a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a capacitor C1 and a capacitor C2, wherein a gate of the transistor T1 is connected to a first GIP output signal Gn-4, a gate of the transistor T7 is connected to a second GIP output signal Gn +4,
the drain of the transistor T1 and the drain of the transistor T7 are electrically connected to the gate of the transistor T2, the drain of the transistor T3, the gate of the transistor T4, the gate of the transistor T8, the gate of the transistor T9, and one end of the capacitor C2, respectively,
the drain of the transistor T2 is electrically connected to the gate of the transistor T3, the gate of the transistor T6 and one end of the capacitor C1, respectively; the other end of the capacitor C1 is grounded;
a source of the transistor T3 is connected to the source of the transistor T8 and the drain of the transistor T9 respectively,
the source of the transistor T4, the drain of the transistor T5, the drain of the transistor T6 and the other end of the capacitor C2 are all connected to the third GIP output signal Gn;
further, the drain of the transistor T4 is connected to the first clock signal CK1, and the gate of the transistor T5 is connected to the second clock signal CK 5.
Further, the source of the transistor T1 and the drain of the transistor T8 are both connected to the positive electrode VGH of the power supply.
Further, the source of the transistor T2, the source of the transistor T5, the source of the transistor T6, the source of the transistor T7 and the source of the transistor T9 are all connected to the negative electrode VGL of the power supply.
Specifically, VGH is a dc high voltage and VGL is a dc low voltage.
Further, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, and the transistor T8 are all N-channel MOS transistors, and the transistor T9 is a P-channel MOS transistor.
As shown in fig. 2, a driving method of a 9T2C circuit for improving stability of a display screen, a scan cycle includes a first period, a second period, a third period, a fourth period, a fifth period, a sixth period and a seventh period; wherein the content of the first and second substances,
at a first time period t 1: the first clock signal CK1 is at high level, the capacitor C1 is charged, the potential of the first node P is changed to high level, the transistors T3 and T6 are turned on, the potential of the third GIP output signal Gn is pulled to low level, the second node Q is pulled to low level under the coupling action of the capacitor C2, and the transistor T9 is turned on;
at a second time period t 2: the first clock signal CK1 changes to low level, the potential at the point P of the first node changes to low level, and the transistors T3 and T6 are turned off;
at a third time period t 3: the first GIP output signal Gn-4 is at a high level, the second clock signal CK5 is at a high level, the transistors T1 and T5 are turned on, the second node Q point becomes a high potential, and the transistors T2, T4, and T8 are turned on; the third node R point becomes high;
at the fourth time period t 4: the first GIP output signal Gn-4 and the second clock signal CK5 become low level, the transistors T1 and T5 are turned off, and the second node Q point maintains high potential;
at a fifth time period t 5: the first clock signal CK1 changes to high level, the third GIP output signal Gn outputs high potential, the second node Q point is pulled down to higher potential under the coupling action of the capacitor C2, the transistor T8 keeps an opening state, the third node R point is high potential, even if T3 is greatly floated negatively due to Vth, the potential of the transistor T3 leaking into the Q point is still high potential, and the transistor T4 normally works;
at a sixth time period t 6: the first clock signal CK1 changes to low level, the third GIP output signal Gn changes to low level, and the existing potential of the second node Q point at the capacitor C2 drops to high level;
at the seventh time period t 7: the second GIP output signal Gn +4 and the second clock signal CK5 are at a high level, the transistor T7 is turned on to pull the potential at the second node Q point to a low level, the transistor T8 is turned off, the transistor T9 is turned on, and the third node R point becomes a low level.
By adopting the technical scheme, the leakage current of the TFT device depends on the relationship between the voltage difference between the gate voltage and the source voltage and the Vth, and when the fifth time period T5 in the driving process, even if the Vth of the transistor T3 device has negative drift, the third node R is pulled to the high potential at the moment, which is equivalent to the fact that the voltage of the source (R point) of the transistor T3 is pulled high, so that the leakage current of the transistor T3 is effectively reduced, and the stability of the display screen is improved. In the GIP driving process, the invention prevents the key node from influencing the subsequent stage transmission because the TFT electric leakage cannot reach the quasi-position, achieves the aim of improving the poor picture caused by the electric leakage of the display screen, and effectively improves the stability of the display screen.
It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. The embodiments and features of the embodiments in the present application may be combined with each other without conflict. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the detailed description of the embodiments of the present application is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Claims (6)
1. The utility model provides a improve 9T2C circuit of display screen stability which characterized in that: which comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a capacitor C1 and a capacitor C2, wherein the gate of the transistor T1 is connected with a first GIP output signal Gn-4, the gate of the transistor T7 is connected with a second GIP output signal Gn +4,
the drain of the transistor T1 and the drain of the transistor T7 are electrically connected to the gate of the transistor T2, the drain of the transistor T3, the gate of the transistor T4, the gate of the transistor T8, the gate of the transistor T9, and one end of the capacitor C2, respectively,
the drain of the transistor T2 is electrically connected to the gate of the transistor T3, the gate of the transistor T6 and one end of the capacitor C1, respectively; the other end of the capacitor C1 is grounded;
a source of the transistor T3 is connected to the source of the transistor T8 and the drain of the transistor T9 respectively,
the source of the transistor T4, the drain of the transistor T5, the drain of the transistor T6, and the other end of the capacitor C2 are all connected to the third GIP output signal Gn.
2. The 9T2C circuit for improving stability of a display screen according to claim 1, wherein: the drain of the transistor T4 is connected to the first clock signal CK1, and the gate of the transistor T5 is connected to the second clock signal CK 5.
3. The 9T2C circuit for improving stability of a display screen according to claim 1, wherein: the source of the transistor T1 and the drain of the transistor T8 are both connected to the positive electrode VGH of the power supply.
4. The 9T2C circuit for improving stability of a display screen according to claim 1, wherein: the source electrode of the transistor T2, the source electrode of the transistor T5, the source electrode of the transistor T6, the source electrode of the transistor T7 and the source electrode of the transistor T9 are all connected with the negative electrode VGL of the power supply.
5. The 9T2C circuit for improving stability of a display screen according to claim 1, wherein: the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7 and the transistor T8 are all N-channel MOS transistors, and the transistor T9 is a P-channel MOS transistor.
6. A driving method of a 9T2C circuit for improving stability of a display screen, which is applied to the 9T2C circuit for improving stability of a display screen of any one of claims 1 to 5, wherein: the scanning cycle comprises a first time period, a second time period, a third time period, a fourth time period, a fifth time period, a sixth time period and a seventh time period; wherein, the first and the second end of the pipe are connected with each other,
at a first time period t 1: the first clock signal CK1 is at high level, the capacitor C1 is charged, the potential of the first node P is changed to high level, the transistors T3 and T6 are turned on, the potential of the third GIP output signal Gn is pulled to low level, the second node Q is pulled to low level under the coupling action of the capacitor C2, and the transistor T9 is turned on;
at a second time period t 2: the first clock signal CK1 changes to low level, the potential at the point P of the first node changes to low level, and the transistors T3 and T6 are turned off;
at a third time period t 3: the first GIP output signal Gn-4 is at a high level, the second clock signal CK5 is at a high level, the transistors T1 and T5 are turned on, the second node Q point becomes a high potential, and the transistors T2, T4, and T8 are turned on; the third node R point becomes high;
during a fourth time period t 4: the first GIP output signal Gn-4 and the second clock signal CK5 become low level, the transistors T1 and T5 are turned off, and the second node Q point maintains high potential;
at a fifth time period t 5: the first clock signal CK1 changes to high level, the third GIP output signal Gn outputs high potential, the second node Q point is pulled down to higher potential under the coupling action of the capacitor C2, the transistor T8 keeps an opening state, the third node R point is high potential, even if T3 is greatly floated negatively due to Vth, the potential of the transistor T3 leaking into the Q point is still high potential, and the transistor T4 normally works;
at a sixth time period t 6: the first clock signal CK1 changes to low level, the third GIP output signal Gn changes to low level, and the existing potential of the second node Q point at the capacitor C2 drops to high level;
at the seventh time period t 7: the second GIP output signal Gn +4 and the second clock signal CK5 are at a high level, the transistor T7 is turned on to pull the potential at the second node Q point to a low level, the transistor T8 is turned off, the transistor T9 is turned on, and the third node R point becomes a low level.
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