CN1146112C - Reliable clock phase detecting logic circuit - Google Patents
Reliable clock phase detecting logic circuit Download PDFInfo
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- CN1146112C CN1146112C CNB991250915A CN99125091A CN1146112C CN 1146112 C CN1146112 C CN 1146112C CN B991250915 A CNB991250915 A CN B991250915A CN 99125091 A CN99125091 A CN 99125091A CN 1146112 C CN1146112 C CN 1146112C
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Abstract
The present invention relates to a clock phase detecting logic circuit with reliable work, which is composed of four D flip flops, an alternative selector and two phase reversers, wherein the clock input terminals of the first D flip flop and the second D flip flop respectively receive a first clock signal and a second clock signal which come from the outside and need phase detection, and the output terminals a clock phase difference signal, a clock phase advance mark signal and a delay mark signal. The circuit has the advantages of simple structure, capability of saving space for a circuit board, stable and reliable work and fast phase locking speed. Especially, the circuit can directly obtain the relation between advance and delay of clock phase, and has a very good application perspective.
Description
The present invention relates to a kind of pulse digit logical circuit, exactly, relate to the logical circuit of quick, the reliable clock phase discrimination of a kind of work, the frequency of its phase demodulation is below 20MHz, and recommendation is 1KHz or 8KHz.Belong to the pulse technique field in the basic electronic circuit.
Programmable logic chip has obtained extensive application in the present Design of Digital Circuit, and for a design, clock influences a vital aspect of Design of Digital Circuit quality often.It is phase-locked to use clock in a lot of occasions, and phase-locked loop is a degenerative closed circuit of phase place, and it is made up of three basic elements of character, i.e. phase discriminator, loop filter and voltage controlled oscillator.Here relate to the problem of a phase demodulation.Phase demodulation, the instantaneous phase that is actually input signal and voltage controlled oscillator output signal compares, produce one and the corresponding error voltage of two signals, this error voltage is by after the loop filter, be added on the voltage controlled oscillator, adjust the frequency and the phase place of voltage controlled oscillator, can reduce the frequency difference between input signal and the output signal and differ, thereby in phase-locked loop, finish the change action of phase difference to voltage.For clock phase discrimination, there is the more general scheme of two kinds of uses available at present, promptly realize with special chip or with logical circuit.The method of coming phase demodulation with special chip as long as will need the clock of phase demodulation to introduce the input pin of special chip, can obtain required differing and the leading relation that falls behind of phase place at this chip output, and its advantage is a function admirable, and phase demodulation speed is very fast; But it is often account for very much circuit board space, nor economical.Use the logical circuit phase demodulation, need not to take specially circuit board space, because used programmable logic chip in the present Design of Digital Circuit in a large number, it is that the clock that needs phase demodulation is introduced in the FPGA (Field Programmable Gate Array), utilize logical circuit to obtain the phase difference, this method often is not very reliable, nor knows the relation that phase place is leading with backward, need suppose again to judge, influence phase-locked speed greatly.
The clock phase discrimination logical circuit that the purpose of this invention is to provide a kind of reliable operation, it makes the developer can both save the space in conjunction with the advantage of two kinds of schemes of above-mentioned present commonplace use, very economical again, but also very realize clock phase discrimination reliably.
The object of the present invention is achieved like this: it is made of four d type flip flops, an alternative selector and two inverters, and it is characterized in that: the annexation of above-mentioned each device is such:
First d type flip flop, its input end of clock receives to come from the outside needs first clock signal clk 1 of phase demodulation, its clear terminal is connected with the output of an inverter, the input of this inverter needs the second clock of phase demodulation signal CLK2 to be connected with coming from the outside, and its state output end is connected to the state input of 3d flip-flop and an input of selector respectively;
Second d type flip flop, its input end of clock receives to come from the outside needs the second clock of phase demodulation signal CLK2, its clear terminal is connected with the output of another inverter, the input of this inverter then needs first clock signal clk 1 of phase demodulation to be connected with coming from the outside, its state output end is connected to the state input of four d flip-flop and another input of selector respectively, and the state input of above-mentioned first d type flip flop and second d type flip flop all is connected with Vcc;
3d flip-flop, its input end of clock receives to come from the outside needs the second clock of phase demodulation signal CLK2, and its state output end then is connected to the selection input of above-mentioned selector, simultaneously, again as the output of the leading marking signal of clock phase of this circuit;
Four d flip-flop, its input end of clock receive to come from the outside needs first clock signal clk of phase demodulation, 1 its state output end then as the output of the hour hands phase lag marking signal of this circuit;
Selector, its output are the outputs of the clock phase difference signal of this circuit.
Its phase demodulation clock frequency that is suitable for should be not more than 20MHz.
Its best phase demodulation clock frequency that is suitable for is 1KHz or 8KHz.
Characteristics of the present invention are: this clock phase discrimination logical circuit combines the advantage of present special chip and two kinds of phase detecting methods of logical circuit, adopts digital circuit that clock is carried out phase demodulation.Its circuit structure is very simple, mainly selects 1 selector, 4 d type flip flops and 2 not gates to be formed by 1 two, has both saved circuit board space, and working stability is reliable again, and phase-locked speed is fast; Especially can directly obtain the lead and lag relation of clock phase, this is that traditional logic phase discriminator is unexistent.After traditional method obtains differing of two signals often, suppose the leading and relation that falls behind of both phase places again by software, and check the accuracy of this hypothesis by the operation of this software program; If the result is not right, then get the result opposite with this hypothesis.Like this, traditional phase-locked process and this phase discriminator come comparison, and be relatively just slow.So the present invention has good application prospects.
Introduce circuit structure composition of the present invention, feature and effect in detail below in conjunction with drawings and Examples:
Fig. 1 is a circuit structure schematic diagram of the present invention.
Fig. 2 is the leading timing waveform of clock signal phase in the circuit structure of the present invention.
Fig. 3 is the timing waveform that clock signal phase lags behind in the circuit structure of the present invention
Referring to Fig. 1, CLK1, CLK2 are respectively the clock signal of two 1K that need phase demodulation among the figure; EN is the phase difference signal of clock phase discrimination logical circuit output of the present invention; Label up, Label dn are leading sign of the phase place of the phase clock of clock phase discrimination logical circuit output of the present invention and phase lag sign.
Circuit structure of the present invention is very simple, mainly is to select 1 selector 5, four 1,2,3,4 and 2 inverters of d type flip flop to constitute by one two.Wherein the annexation of circuit is such: first d type flip flop 1, its input end of clock receives to come from the outside needs first clock signal clk 1 of phase demodulation, its clear terminal is connected with the output of an inverter, the input of this inverter needs the second clock of phase demodulation signal CLK2 to be connected with coming from the outside, and its state output end is connected to the state input of 3d flip-flop 3 and an input of selector 5 respectively; Second d type flip flop 2, its input end of clock receives to come from the outside needs the second clock of phase demodulation signal CLK2, its clear terminal is connected with the output of another inverter, the input of this inverter then needs first clock signal clk 1 of phase demodulation to be connected with coming from the outside, its state output end is connected to the state input of four d flip-flop 4 and another input of selector 5 respectively, and the state input of above-mentioned first d type flip flop 1 and second d type flip flop 2 all is connected with power Vcc; 3d flip-flop 3, its input end of clock receives to come from the outside needs the second clock of phase demodulation signal CLK2, its state output end then is connected to the selection input of above-mentioned selector 5, simultaneously, and again as the output Label up of the leading marking signal of hour hands phase place of this circuit; Four d flip-flop 4, its input end of clock receives to come from the outside needs first clock signal clk 1 of phase demodulation, and its state output end is then as the output Label dn of the hour hands phase lag marking signal of this circuit; Selector 5, its output are the output EN of the clock phase difference signal of this circuit.
Referring to Fig. 2, Fig. 3, the concrete running of circuit of the present invention is such:
(1) if the 1k clock signal phase of CLK1 is leading, then when the rising edge of CLK1 arrives, first d type flip flop, 1 output terminals A point is a high level, and when the 1K of CLK2 clock signal high level arrives, first d type flip flop 1 is wanted zero clearing, again its output terminals A point is set to low level, so, the phase difference signal of two 1K clock signals can be obtained by the A point.Because when the input clock CLK2 rising edge of second d type flip flop 2 arrived, this trigger was in the CLK1 signal to its clear terminal effectual time.So second d type flip flop, 2 output B points then are low level.The level signal that these two output terminals A, B are ordered is sent to two inputs of selector 5 again respectively, simultaneously, the state output end of first d type flip flop 1 is connected to the state input of 3d flip-flop 3 again, make the output D point of 3d flip-flop 3 be high level always, this D point high level is connected to the selection input of selector 5 again, and making the corresponding phase difference signal of selector 5 outputs is A point signal; And the output E point of four d flip-flop 4 is a low level always.The level signal of output Label dn, the Label up of the leading sign of two clock phases of circuit of the present invention and the sign that lags behind then is respectively " 0 ", " 1 " at this moment.
(2) if the 1k clock signal phase of CLK1 lags behind, the B point that then can analyze second d type flip flop, 2 outputs in Fig. 1 equally can obtain the phase difference signal of two 1K clock signals, does not repeat them here.This moment, first d type flip flop, 1 output terminals A point was a low level.Four d flip-flop 4 output E points are high level then always, and 3d flip-flop 3 output D points are low level always, and the corresponding phase difference signal of selector 5 outputs is a B point signal like this; The level signal of output Label dn, the Label up of the leading sign of two clock phases of circuit of the present invention and the sign that lags behind then is respectively " 1 ", " 0 ".
In a word, the present invention is and two corresponding phase difference signal of clock signal that simultaneously, data wire is as long as just can obtain the relation that corresponding phase place is leading and lag behind by collection Label dn, the formed binary coding of label up from what output EN exported.
Claims (3)
1. a clock phase discrimination logical circuit is made of four d type flip flops, an alternative selector and two inverters, and it is characterized in that: the annexation of above-mentioned each device is such:
First d type flip flop, its input end of clock receives to come from the outside needs first clock signal of phase demodulation (CLK1), its clear terminal is connected with the output of an inverter, the input of this inverter needs the second clock of phase demodulation signal (CLK2) to be connected with coming from the outside, and its state output end is connected to the state input of 3d flip-flop and an input of selector respectively;
Second d type flip flop, its input end of clock receives to come from the outside needs the second clock of phase demodulation signal (CLK2), its clear terminal is connected with the output of another inverter, the input of this inverter then needs first clock signal of phase demodulation (CLK1) to be connected with coming from the outside, its state output end is connected to the state input of four d flip-flop and another input of selector respectively, and the state input of above-mentioned first d type flip flop and second d type flip flop all is connected with power Vcc;
3d flip-flop, its input end of clock receives to come from the outside needs the second clock of phase demodulation signal (CLK2), and its state output end then is connected to the selection input of above-mentioned selector, simultaneously, again as the output of the leading marking signal of clock phase of this circuit;
Four d flip-flop, its input end of clock receives to come from the outside needs first clock signal of phase demodulation (CLK1), and its state output end is then as the output of the hour hands phase lag marking signal of this circuit; Selector, its output are the outputs of the clock phase difference signal of this circuit;
Selector, its output are the outputs of the clock phase difference signal of this circuit.
2. clock phase discrimination logical circuit as claimed in claim 1 is characterized in that: first clock signal (CLK1) is or/and the suitable phase demodulation clock frequency of second clock signal (CLK2) should be not more than 20MHz.
3. clock phase discrimination logical circuit as claimed in claim 1 is characterized in that: first clock signal (CLK1) is or/and the suitable best phase demodulation clock frequency of second clock signal (CLK2) is 1KHz or 8KHz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB991250915A CN1146112C (en) | 1999-11-26 | 1999-11-26 | Reliable clock phase detecting logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB991250915A CN1146112C (en) | 1999-11-26 | 1999-11-26 | Reliable clock phase detecting logic circuit |
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| Publication Number | Publication Date |
|---|---|
| CN1298227A CN1298227A (en) | 2001-06-06 |
| CN1146112C true CN1146112C (en) | 2004-04-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB991250915A Expired - Fee Related CN1146112C (en) | 1999-11-26 | 1999-11-26 | Reliable clock phase detecting logic circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102364877A (en) * | 2011-11-18 | 2012-02-29 | 中国船舶重工集团公司第七○四研究所 | Field programmable gate array (FPGA)-based hardware phase discrimination circuit |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055469B (en) * | 2009-11-05 | 2014-04-30 | 中兴通讯股份有限公司 | Phase discriminator and phase locked loop circuit |
| US9197226B2 (en) * | 2013-07-08 | 2015-11-24 | Analog Devices, Inc. | Digital phase detector |
-
1999
- 1999-11-26 CN CNB991250915A patent/CN1146112C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102364877A (en) * | 2011-11-18 | 2012-02-29 | 中国船舶重工集团公司第七○四研究所 | Field programmable gate array (FPGA)-based hardware phase discrimination circuit |
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| Publication number | Publication date |
|---|---|
| CN1298227A (en) | 2001-06-06 |
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