CN111565038A

CN111565038A - Phase-locked loop state detection circuit and phase-locked loop circuit

Info

Publication number: CN111565038A
Application number: CN202010467776.XA
Authority: CN
Inventors: 彭振宇; 韩智毅
Original assignee: Guangdong Huaxin Weite Integrated Circuit Co ltd
Current assignee: Guangdong Huaxin Weite Integrated Circuit Co ltd
Priority date: 2020-05-28
Filing date: 2020-05-28
Publication date: 2020-08-21

Abstract

The invention relates to a phase-locked loop state detection circuit and a phase-locked loop circuit, wherein the phase-locked loop state detection circuit comprises: the state monitoring circuit is used for monitoring the phase difference between a feedback clock and a reference clock of the phase-locked loop and outputting a first trigger signal when the phase difference is constant; the timing circuit is used for timing the time length of the phase difference maintaining constant and outputting a second trigger signal when the timing exceeds a set threshold value; and the latch circuit is used for outputting a state signal when the phase-locked loop is locked when receiving the first trigger signal and the second trigger signal. The phase difference change condition of the two clocks is monitored by accessing the feedback clock and the reference clock of the phase-locked loop through the state monitoring circuit, and the state monitoring circuit, the timing circuit and the latch circuit are designed to be matched with each other based on the clock phase detection principle, so that the locking state of the phase-locked loop can be detected in real time, the detection power consumption is low, and the effect of greatly improving the detection performance is achieved.

Description

Phase-locked loop state detection circuit and phase-locked loop circuit

Technical Field

The invention relates to the technical field of phase-locked loops, in particular to a phase-locked loop state detection circuit and a phase-locked loop circuit.

Background

The phase-locked loop is used as a core component in the microelectronic industry and is widely applied to the fields of communication, radar, aerospace, automotive electronics, measuring instruments, MCU and the like. The phase-locked loop mainly functions to generate a stable and reliable high-frequency clock signal and mainly comprises a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator, a frequency divider and the like. In order to detect the state lock of the phase locked loop, a state lock detection circuit is usually included in the circuitry of the phase locked loop. The working state of the phase-locked loop can be divided into a locked state and an unlocked state, and the locking time is a key index of the phase-locked loop design.

In a traditional phase-locked loop state locking detection circuit, in order to judge whether a phase-locked loop is locked, a counter timing method is directly adopted, and the locking of the phase-locked loop is judged by the fact that the timing of the counter is greater than the locking time of the phase-locked loop; and a method of using a digital gate level unit counts through a multiple relation between an input frequency and an output frequency, thereby judging the locking state of the phase-locked loop. However, in the process of implementing the present invention, the inventor finds that the conventional pll state lock detection circuit has at least a problem of poor detection performance.

Disclosure of Invention

Therefore, it is desirable to provide a pll status detection circuit and a pll circuit with greatly improved detection performance.

In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:

in one aspect, an embodiment of the present invention provides a phase-locked loop state detection circuit, including:

the state monitoring circuit is used for monitoring the phase difference between a feedback clock and a reference clock of the phase-locked loop and outputting a first trigger signal when the phase difference is constant;

the timing circuit is used for timing the time length of the phase difference maintaining constant and outputting a second trigger signal when the timing exceeds a set threshold value;

and the latch circuit is used for outputting a state signal when the phase-locked loop is locked when receiving the first trigger signal and the second trigger signal.

In one embodiment, the state monitoring circuit comprises a NAND gate N1 and a flip-flop DFF1, wherein the output end of the NAND gate N1 is connected with the clock input end of the flip-flop DFF 1;

the first input end of the NAND gate N1 is used for accessing a feedback clock, and the second input end of the NAND gate N1 is used for accessing a voltage-controlled oscillation clock of a phase-locked loop;

the D end of the flip-flop DFF1 is used for accessing a reference clock, the Q end of the flip-flop DFF1 is used for outputting a first trigger signal, and the reset end of the flip-flop DFF1 is used for accessing a reset signal.

IN one embodiment, the timing circuit includes flip-flop DFF2, flip-flop DFF3, flip-flop DFF4, flip-flop DFF5, flip-flop DFF6, and flip-flop DFF7, and nand gate N2, not gate IN1, not gate IN2, not gate IN3, not gate IN4, and not gate IN 5;

the clock input end of the flip-flop DFF2 is used for accessing a reference clock, the Q end of the flip-flop DFF2 is connected with the input end of the NOT gate IN1, and the D end of the flip-flop DFF2 is connected with the output end of the NOT gate IN 1;

the clock input end of the flip-flop DFF3 is connected with the Q end of the flip-flop DFF2, the Q end of the flip-flop DFF3 is connected with the input end of the NOT gate IN2, and the D end of the flip-flop DFF3 is connected with the output end of the NOT gate IN 2;

the clock input end of the flip-flop DFF4 is connected with the Q end of the flip-flop DFF3, the Q end of the flip-flop DFF4 is connected with the input end of the NOT gate IN3, and the D end of the flip-flop DFF4 is connected with the output end of the NOT gate IN 3;

the clock input end of the flip-flop DFF5 is connected with the Q end of the flip-flop DFF4, the Q end of the flip-flop DFF5 is connected with the input end of the NOT gate IN4, and the D end of the flip-flop DFF5 is connected with the output end of the NOT gate IN 4;

the clock input end of the flip-flop DFF6 is connected with the Q end of the flip-flop DFF5, the Q end of the flip-flop DFF6 is connected with the input end of the NOT gate IN5, and the D end of the flip-flop DFF6 is connected with the output end of the NOT gate IN 5;

the reset ends of the flip-flop DFF2, the flip-flop DFF3, the flip-flop DFF4, the flip-flop DFF5 and the flip-flop DFF6 are respectively connected with the Q end of the flip-flop DFF 1;

the setting end of the flip-flop DFF7 is connected with the Q end of the flip-flop DFF1, the clock input end of the flip-flop DFF7 is used for accessing a reference clock, the D end of the flip-flop DFF7 is connected with the output end of the NAND gate N2, the Q end of the flip-flop DFF7 is used for outputting a second trigger signal, the first input end of the NAND gate N2 is connected with the Q end of the flip-flop DFF5, and the second input end of the NAND gate N2 is connected with the Q end of the flip-flop DFF 6.

In one embodiment, the latch circuit comprises a nand gate N3 and a nand gate N4;

the first input end of the nand gate N3 is used for accessing a first trigger signal, the second input end of the nand gate N4 is used for accessing a second trigger signal, the output end of the nand gate N4 is used for outputting a state signal, the second input end of the nand gate N3 is connected with the output end of the nand gate N4, and the output end of the nand gate N3 is connected with the first input end of the nand gate N4.

IN one embodiment, the latch circuit includes NOR gate NOR1, NOR gate NOR2, and NOR gate IN 6;

a first input terminal of the NOR gate NOR1 is used for receiving the first trigger signal, a second input terminal of the NOR gate NOR2 is used for receiving the second trigger signal, an output terminal of the NOR gate NOR2 is connected with an input terminal of the NOR gate IN6, an output terminal of the NOR gate IN6 is used for outputting the state signal, a second input terminal of the NOR gate NOR1 is connected with an output terminal of the NOR gate NOR2, and an output terminal of the NOR gate NOR1 is connected with a first input terminal of the NOR gate NOR 2.

On the other hand, the phase-locked loop circuit comprises a phase-locked loop, a state monitoring circuit, a timing circuit and a latch circuit;

the latch circuit is used for outputting a state signal when the phase-locked loop is locked when receiving the first trigger signal and the second trigger signal.

a first input end of the NAND gate N1 is used for accessing a feedback clock, and a second input end of the NAND gate N1 is connected with an output end of a voltage-controlled oscillator of the phase-locked loop;

One of the above technical solutions has the following advantages and beneficial effects:

the phase-locked loop state detection circuit and the phase-locked loop circuit are connected with a feedback clock and a reference clock of the phase-locked loop through the state monitoring circuit, and the phase difference change condition of the two clocks is monitored; and when the phase difference between the feedback clock and the reference clock is monitored to reach a constant state, outputting a corresponding first trigger signal to the latch circuit. When the state monitoring circuit monitors that the phase difference between the feedback clock and the reference clock reaches a constant state, the timing circuit starts to time the constant state, and outputs a corresponding second trigger signal to the latch circuit when the time exceeds a set threshold value. When the latch circuit receives the first trigger signal and the second trigger signal, the latch circuit outputs a corresponding state signal, and the phase-locked loop completes locking. Therefore, based on the clock phase detection principle, the design state monitoring circuit, the timing circuit and the latch circuit are matched with one another, the locking state of the phase-locked loop can be detected in real time, the detection power consumption is low, and the effect of greatly improving the detection performance is achieved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a block diagram of a conventional PLL circuit;

FIG. 2 is a diagram illustrating a first configuration of a phase-locked loop status detection circuit according to an embodiment;

FIG. 3 is a diagram illustrating a second exemplary phase-locked loop status detection circuit;

FIG. 4 is a diagram illustrating a third structure of a phase-locked loop status detection circuit according to an embodiment;

FIG. 5 is a diagram illustrating a fourth exemplary phase-locked loop status detection circuit;

FIG. 6 is a schematic diagram of signal waveforms at nodes of a circuit in one embodiment;

FIG. 7 is a diagram illustrating a fifth exemplary phase-locked loop status detection circuit;

FIG. 8 is a diagram illustrating an exemplary phase-locked loop circuit.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements but are not limited by these terms, which are used merely to distinguish one element from another. The "connection" in the following embodiments is understood to be "connection", "communication connection", or the like if the connected circuits, modules, units, or the like have electrical signals or data transmission therebetween.

As shown in fig. 1, the circuit structure of a conventional phase-locked loop is a block diagram, where the phase-locked loop mainly includes five components, such as a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator, and a frequency divider, and a state lock detection circuit for detecting state lock of the phase-locked loop. Wherein Ref _ Clk represents a reference clock signal, Fb _ Clk represents a feedback clock signal output by the frequency divider, Reset represents a Reset signal, Vco _ Clk represents an output signal of the voltage-controlled oscillator, that is, a voltage-controlled oscillating clock signal, and Lock _ det represents a state signal output by the phase-locked loop corresponding to state detection, which is understood in the following drawings.

The working state of the phase-locked loop can be divided into a locked state and an unlocked state, and the locking time is a key index of the phase-locked loop design. In a traditional phase-locked loop state locking detection circuit, a counter timing method is adopted to judge the locking of a phase-locked loop by utilizing the fact that the timing of the counter is greater than the locking time of the phase-locked loop, but the actual locking time of the phase-locked loop is different under the influence of different factors such as process, temperature and environment, so that the working state of the phase-locked loop cannot be monitored in real time by the method, and the phase-locked loop can only be ensured to enter the locking state by utilizing the maximum locking time of the phase-locked loop. However, the method using the digital gate unit counts by using the multiple relationship between the input frequency and the output frequency to determine the state locking of the phase-locked loop, but this method cannot identify the phase loss, and the circuit design is complex and inflexible, and the detection performance is poor. Aiming at the problems of the traditional phase-locked loop state locking detection circuit, the application provides the following technical scheme.

Referring to fig. 2, in one embodiment, a pll status detecting circuit 100 is provided, which includes a status monitoring circuit 12, a timing circuit 14, and a latch circuit 16. The state monitoring circuit 12 is configured to monitor a phase difference between a feedback clock and a reference clock of the phase-locked loop, and output a first trigger signal when the phase difference is constant. The timing circuit 14 is configured to time a duration that the phase difference is maintained constant, and output a second trigger signal when the time exceeds a set threshold. The latch circuit 16 is configured to output a status signal when the phase-locked loop is locked, when receiving the first trigger signal and the second trigger signal.

It can be understood that the feedback clock of the phase-locked loop refers to the clock signal output by the output end of the frequency divider of the phase-locked loop, the state monitoring circuit 12 may be various chip devices or circuit modules for implementing signal phase difference detection, the state monitoring circuit 12 may access two clock signals of the phase-locked loop, such as the feedback clock and the reference clock, and independently monitor the change condition of the phase difference of the two clock signals within a period of time, or may assist the feedback clock to sample the reference clock by accessing the two clock signals of the phase-locked loop, such as the feedback clock and the reference clock, and the voltage-controlled oscillation clock output by the voltage-controlled oscillator accessed to the phase-locked loop, so as to compare the phase difference of the sampling signals of the feedback clock and the reference clock, and also; the particular phase difference monitoring scheme is determined by the particular type of condition monitoring circuit 12 being utilized.

The timing circuit 14 may be any type of timer or timing circuit 14 module in the art, and the timing circuit 14 may be separately disposed from the state monitoring circuit 12, or may be disposed on an independent substrate together with the state monitoring circuit 12 or integrally disposed on a substrate where the phase-locked loop is located, as long as the timing circuit can be linked with the state monitoring circuit 12, and start timing when the state monitoring circuit 12 monitors that the phase difference between the feedback clock and the reference clock is stable, so as to time the duration of maintaining the phase difference to be constant. Latch circuit 16 may employ various latch devices known in the art for performing the clear, set, and hold functions. The set threshold may be determined according to the reference clock and a circuit design index of the entire phase-locked loop (e.g., a frequency division number set by a frequency divider of the phase-locked loop), as long as the set threshold is an integer multiple of the reference clock and facilitates counting judgment, for example, any time duration between 1ms and 31 ms. Different delay times of the second trigger signal output by the timing circuit 14 can be flexibly set by selecting different setting thresholds, so that the real-time monitoring output of states with different precisions is realized.

Specifically, in the using process of the phase-locked loop, the phase-locked loop and the phase-locked loop state detection circuit 100 are reset to give initial values to the circuits, so that the initial states of the circuits after being powered on are unified and the circuits can work normally. The state monitoring circuit 12 accesses at least two clock signals of a reference clock and a feedback clock of the phase-locked loop to judge the phase difference change situation of the two clock signals within a period of time, for example, the phase difference is stable or changed. When the state monitoring circuit 12 monitors that the phase difference between the feedback clock and the reference clock is constant, that is, the state monitoring circuit 12 outputs the first trigger signal to the latch circuit 16, the timing circuit 14 starts timing. Timing circuit 14 may be directly or indirectly electrically connected to condition monitoring circuit 12 to obtain a trigger signal from condition monitoring circuit 12 to initiate timing operations. When the state monitoring circuit 12 continuously outputs the first trigger signal and the timing circuit 14 counts the time and exceeds the set threshold value and outputs the second trigger signal to the latch circuit 16, that is, the phase difference between the feedback clock and the reference clock is kept constant and reaches the set duration, it indicates that the phase-locked loop is currently locked, therefore, when the latch circuit 16 receives the first trigger signal and the second trigger signal, the state signal when the phase-locked loop is locked is output, otherwise, the latch circuit 16 keeps outputting the out-of-lock state signal when the phase-locked loop is in the out-of-lock state. The locking state of the phase-locked loop can be known by the state signal output by the latch circuit 16.

The phase-locked loop state detection circuit 100 accesses a feedback clock and a reference clock of the phase-locked loop through the state monitoring circuit 12, and monitors the phase difference change condition of the two clocks; when the phase difference between the feedback clock and the reference clock is monitored to reach a constant state, a corresponding first trigger signal is output to the latch circuit 16. When the state monitoring circuit 12 monitors that the phase difference between the feedback clock and the reference clock reaches a constant state, the timing circuit 14 starts timing the constant state, and outputs a corresponding second trigger signal to the latch circuit 16 when the timing exceeds a set threshold. When the latch circuit 16 receives the first trigger signal and the second trigger signal, the latch circuit 16 outputs a corresponding status signal, and the phase-locked loop completes locking. Therefore, based on the clock phase detection principle, the design state monitoring circuit 12, the timing circuit 14 and the latch circuit 16 are matched with each other, the locking state of the phase-locked loop can be detected in real time, the detection power consumption is low, and the effect of greatly improving the detection performance is achieved.

Referring to FIG. 3, in one embodiment, the condition monitoring circuit 12 includes a NAND gate N1 and a flip-flop DFF 1. The output of the nand gate N1 is connected to the clock input of the flip-flop DFF 1. The first input end of the NAND gate N1 is used for accessing a feedback clock, and the second input end of the NAND gate N1 is used for accessing a voltage-controlled oscillating clock of a phase-locked loop. The D end of the flip-flop DFF1 is used for accessing a reference clock, the Q end of the flip-flop DFF1 is used for outputting a first trigger signal, and the reset end of the flip-flop DFF1 is used for accessing a reset signal.

Optionally, in this embodiment, a D flip-flop and a nand gate are used to build the required state monitoring circuit 12. It will be appreciated that the reference clock and reset signal provided to the phase locked loop may be provided by an external crystal and reset interface, respectively. Specifically, two input ends of the nand gate N1 are respectively used for accessing two clock signals, such as a reference clock of a phase-locked loop and a voltage-controlled oscillation clock, and a D end of the flip-flop DFF1 is used for accessing the reference clock signal of the phase-locked loop, so that the flip-flop DFF1 can sample the reference clock by using the feedback clock with the aid of the voltage-controlled oscillation clock, and can determine the relationship between the phases of the feedback clock and the reference clock.

In this embodiment, the reset signal of the pll or an externally provided reset signal alone may be directly used to perform a reset operation on the pll and the pll status detecting circuit 100; the trigger DFF1 is given an initial value, generally given an initial value of 0, by a reset signal, and the timing circuit 14 performs timing and zero clearing to ensure normal implementation of subsequent phase-locked loop locking state monitoring. Under the assistance of the voltage-controlled oscillating clock, the feedback clock samples the reference clock. When the phase difference between the feedback clock and the reference clock is constant, the output of the flip-flop DFF1 is high, that is, the Q terminal of the flip-flop DFF1 outputs high, and the timing circuit 14 starts to time accordingly.

If the Q terminal of the flip-flop DFF1 keeps outputting the high level (i.e. the first trigger signal) after a set number of consecutive sampling times (i.e. the duration of consecutive sampling reaches a set threshold) for the high level region of the reference clock, for example but not limited to N/2 times (N is the number of divisions of the divider), it means that the phase difference between the reference clock and the sampling clock is kept constant, i.e. the duration of the phase difference between the feedback clock and the reference clock being kept constant reaches the set threshold. At this time, the timing circuit 14 outputs the second trigger signal to the latch circuit 16, and the current input signal of the latch circuit 16 includes both the first trigger signal and the second trigger signal, so as to output a status signal when the phase-locked loop completes the locking.

It can be understood that when the phase difference between the feedback clock and the reference clock is constant, the output of the flip-flop DFF1 is at a high level, and then the output level of the Q terminal of the flip-flop DFF1 has a high level and also has a low level after a set number of consecutive sampling times in the high level region of the reference clock, which indicates that the phase difference between the feedback clock and the reference clock is not maintained constant but is still continuously changing, the timing circuit 14 is cleared without outputting the second trigger signal correspondingly, so that the output signal of the latch circuit 16 is maintained as the out-of-lock state signal when the phase-locked loop is out of lock.

By adopting the state monitoring circuit 12, the circuit structure is simple, the clock phase detection can be efficiently realized, the circuit design and manufacturing cost is low, the power consumption is low, the locking state real-time monitoring of the phase-locked loop is efficiently realized by matching the timing circuit 14 and the latch circuit 16, and the application cost and the power consumption of the whole phase-locked loop circuit system are reduced.

Referring to fig. 4, IN one embodiment, the timing circuit 14 includes a flip-flop DFF2, a flip-flop DFF3, a flip-flop DFF4, a flip-flop DFF5, a flip-flop DFF6, and a flip-flop DFF7, and a nand gate N2, a not gate IN1, a not gate IN2, a not gate IN3, a not gate IN4, and a not gate IN 5. The clock input end of the flip-flop DFF2 is used for connecting a reference clock, the Q end of the flip-flop DFF2 is connected with the input end of the NOT gate IN1, and the D end of the flip-flop DFF2 is connected with the output end of the NOT gate IN 1. The clock input terminal of the flip-flop DFF3 is connected to the Q terminal of the flip-flop DFF2, the Q terminal of the flip-flop DFF3 is connected to the input terminal of the not gate IN2, and the D terminal of the flip-flop DFF3 is connected to the output terminal of the not gate IN 2.

The clock input terminal of the flip-flop DFF4 is connected to the Q terminal of the flip-flop DFF3, the Q terminal of the flip-flop DFF4 is connected to the input terminal of the not gate IN3, and the D terminal of the flip-flop DFF4 is connected to the output terminal of the not gate IN 3. The clock input terminal of the flip-flop DFF5 is connected to the Q terminal of the flip-flop DFF4, the Q terminal of the flip-flop DFF5 is connected to the input terminal of the not gate IN4, and the D terminal of the flip-flop DFF5 is connected to the output terminal of the not gate IN 4. The clock input terminal of the flip-flop DFF6 is connected to the Q terminal of the flip-flop DFF5, the Q terminal of the flip-flop DFF6 is connected to the input terminal of the not gate IN5, and the D terminal of the flip-flop DFF6 is connected to the output terminal of the not gate IN 5. The reset terminals of the flip-flop DFF2, the flip-flop DFF3, the flip-flop DFF4, the flip-flop DFF5 and the flip-flop DFF6 are connected to the Q terminal of the flip-flop DFF1, respectively.

The setting end of the flip-flop DFF7 is connected with the Q end of the flip-flop DFF1, the clock input end of the flip-flop DFF7 is used for accessing a reference clock, the D end of the flip-flop DFF7 is connected with the output end of the NAND gate N2, and the Q end of the flip-flop DFF7 is used for outputting a second trigger signal. The first input end of the NAND gate N2 is connected with the Q end of the flip-flop DFF5, and the second input end of the NAND gate N2 is connected with the Q end of the flip-flop DFF 6.

Optionally, the above-mentioned newly designed timing circuit 14 is adopted in the present embodiment. In the process of resetting the phase-locked loop and the phase-locked loop state detection circuit 100, the output of the Q end of the trigger DFF1 is 0, and the output of the Q end of the trigger DFF1 directly controls the working states of the trigger DFF2 to the trigger DFF 7: the Q output of flip-flop DFF2 through flip-flop DFF6 is 0, while the Q of flip-flop DFF7 is set to logic 1. After the reset is completed, the state monitoring circuit 12 starts phase monitoring of the reference clock of the phase-locked loop. As long as the Q-side output of the flip-flop DFF1 is 0 (low level), that is, the phase-locked loop is not locked, the Q-side outputs from the flip-flop DFF2 to the flip-flop DFF6 are cleared, the Q-side output of the flip-flop DFF7 is set to 1 (high level), the latch circuit 16 does not receive the first trigger signal (in this embodiment, the high level output from the Q-side of the flip-flop DFF 6) and the second trigger signal (in this embodiment, the low level output from the Q-side of the flip-flop DFF 7) at the same time, and the output of the latch circuit 16 is maintained as the out-of-lock state signal when the phase-locked loop is in the out-of.

When the Q terminal output of the flip-flop DFF6 is high level 1, the counter of the composition of the flip-flop DFF6 to the flip-flop DFF2 starts counting from 5' b00000 (binary number). If the output of the Q terminal of the flip-flop DFF6 is kept at the high level 1 and the outputs from the flip-flop DFF6 to the flip-flop DFF2 are 5' b11000 (that is, the set threshold selected in this embodiment is reached, and other thresholds may be selected according to actual monitoring requirements) during the phase difference monitoring process, the high level output by the Q terminal of the flip-flop DFF6 is the first trigger signal received by the latch circuit 16, and the Q terminal of the flip-flop DFF7 is changed to output the low level at the rising edge of the next reference clock, so that the latch circuit 16 receives the first trigger signal and the second trigger signal at the same time, and the output adjustment of the state signal at the lock time of the output phase-locked loop is satisfied, and the output state signal is output, and the phase-locked loop is locked.

Through the structural design of the timing circuit 14, in cooperation with the state monitoring circuit 12, the design and manufacturing cost of the phase-locked loop state detection circuit 100 can be further reduced, and the monitoring power consumption can be reduced; the phase difference monitoring of the feedback clock and the reference clock and the realization of the timing function thereof are more efficient, so that the detection performance of the phase-locked loop state detection circuit 100 is further improved.

Referring to fig. 5, in one embodiment, the latch circuit 16 includes a nand gate N3 and a nand gate N4. A first input of the nand gate N3 is used for receiving a first trigger signal. The second input end of the nand gate N4 is used for receiving the second trigger signal, and the output end of the nand gate N4 is used for outputting the state signal. The second input end of the NAND gate N3 is connected with the output end of the NAND gate N4, and the output end of the NAND gate N3 is connected with the first input end of the NAND gate N4.

Optionally, in this embodiment, a latch circuit 16 formed by a dual nand gate is used in cooperation with the state monitoring circuit 12 and the timing circuit 14, an R end of the latch circuit 16 is a first input end of the nand gate N3, and a first input end of the nand gate N3 is connected to a Q end of the flip-flop DFF 1; the S terminal of the latch circuit 16 is the second input terminal of the nand gate N4, and the second input terminal of the nand gate N4 is connected to the Q terminal of the flip-flop DFF 7.

When the Q terminal of the flip-flop DFF1 outputs a low level, the Q terminal of the flip-flop DFF7 outputs a high level, the R terminal input of the latch circuit 16 is 0, the S terminal input is 1, and the output thereof is 0, i.e., the output terminal of the nand gate N4 outputs a low level, i.e., an out-of-lock state signal in the phase-locked loop out-of-lock state. When the Q terminal of the flip-flop DFF1 outputs a low level, the Q terminal of the flip-flop DFF7 outputs a high level, the R terminal input of the latch circuit 16 is 1, the S terminal input is 0, and the output thereof is 1, that is, the output terminal of the nand gate N4 outputs a high level, that is, outputs a state signal when the phase-locked loop completes locking. Fig. 6 shows a signal waveform diagram of each node of the circuit, where Δ Φ represents a phase difference, Φ represents a phase, Q6 represents the Q-side output signal of the flip-flop DFF1, i.e., the first trigger signal, and the state monitoring output of the pll status detecting circuit 100 can be visually observed.

By using the latch circuit 16 formed by the nand gate, the circuit structure design of the pll status detecting circuit 100 can be further simplified, the power consumption is lower, the status monitoring output is more efficient, and the detection performance of the pll status detecting circuit 100 can be further improved.

Referring to fig. 7, IN one embodiment, the latch circuit 16 includes a NOR gate NOR1, a NOR gate NOR2, and a NOR gate IN 6. A first input of the NOR gate NOR1 is used for receiving a first trigger signal. A second input of the NOR gate NOR2 is used for receiving the second trigger signal, an output of the NOR gate NOR2 is connected to an input of the NOR gate IN6, and an output of the NOR gate IN6 is used for outputting the status signal. A second input of the NOR gate NOR1 is connected to the output of the NOR gate NOR2, and an output of the NOR gate NOR1 is connected to the first input of the NOR gate NOR 2.

Optionally, IN this embodiment, a latch circuit 16 formed by a double NOR gate, i.e., an inverter (i.e., a NOR gate IN6), is matched with the state monitoring circuit 12 and the timing circuit 14, an R terminal of the latch circuit 16 is a first input terminal of a NOR gate NOR1, and a first input terminal of the NOR gate NOR1 is connected to a Q terminal of the flip-flop DFF 1; the S terminal of the latch circuit 16 is the second input terminal of the NOR gate NOR2, and the second input terminal of the NOR gate NOR2 is connected to the Q terminal of the flip-flop DFF 7.

When the Q terminal of the flip-flop DFF1 outputs a low level, the Q terminal of the flip-flop DFF7 outputs a high level, the R terminal input of the latch circuit 16 is 0, the S terminal input is 1, and the output thereof is 0, that is, the output terminal of the NOR gate NOR2 outputs a low level, that is, an out-of-lock state signal in the out-of-lock state of the phase-locked loop. When the Q terminal of the flip-flop DFF1 outputs a low level, the Q terminal of the flip-flop DFF7 outputs a high level, the R terminal input of the latch circuit 16 is 1, the S terminal input is 0, and the output thereof is 1, that is, the output terminal of the NOR gate NOR2 outputs a high level, that is, outputs a state signal when the phase-locked loop completes locking.

By using the latch circuit 16 formed by the nor gate, the circuit structure design of the pll status detecting circuit 100 can be further simplified, the power consumption is lower, the status monitoring output is more efficient, and the detection performance of the pll status detecting circuit 100 can be further improved.

Referring to fig. 8, in an embodiment, a pll circuit 200 is further provided, which includes a pll 201, a state monitoring circuit 12, a timing circuit 14, and a latch circuit 16. The state monitoring circuit 12 is configured to monitor a phase difference between a feedback clock and a reference clock of the phase locked loop 201, and output a first trigger signal when the phase difference is constant. The timing circuit 14 is configured to time a duration that the phase difference is maintained constant, and output a second trigger signal when the time exceeds a set threshold. The latch circuit 16 is configured to output a state signal when the phase-locked loop 201 is locked, when receiving the first trigger signal and the second trigger signal.

It is to be understood that, for the explanation of the circuit structures and other terms in the pll circuit 200 in this embodiment, the same explanations as those for the embodiments of the pll state detecting circuit 100 can be referred to for understanding, and repeated descriptions are not repeated here.

Specifically, the input terminal of the state monitoring circuit 12 may be connected to the reference clock input terminal of the phase-locked loop 201 and the feedback clock output terminal of the phase-locked loop 201, respectively, and directly access the reference clock signal and the feedback clock signal to be detected. In the using process of the phase-locked loop 201, the state monitoring circuit 12, the timing circuit 14 and the latch circuit 16 are reset to give initial values to the circuits, so that the initial states of the circuits after being electrified are unified to ensure that the circuits can work normally.

After the reset, the state monitoring circuit 12 accesses at least two clock signals of the reference clock and the feedback clock of the phase locked loop 201 to determine the phase difference change condition of the two clock signals within a period of time, for example, the phase difference is stable or changed. When the state monitoring circuit 12 monitors that the phase difference between the feedback clock and the reference clock is constant, that is, the state monitoring circuit 12 outputs the first trigger signal to the latch circuit 16, the timing circuit 14 starts timing. Timing circuit 14 may be directly or indirectly electrically connected to condition monitoring circuit 12 to obtain a trigger signal from condition monitoring circuit 12 to initiate timing operations.

When the state monitoring circuit 12 continuously outputs the first trigger signal, and the timing circuit 14 counts the time and exceeds the set threshold value and outputs the second trigger signal to the latch circuit 16, that is, the phase difference between the feedback clock and the reference clock is kept constant and reaches the set duration, it indicates that the phase-locked loop 201 is currently locked, therefore, when the latch circuit 16 receives the first trigger signal and the second trigger signal, a state signal when the phase-locked loop 201 is locked is output, otherwise, the latch circuit 16 keeps outputting an out-of-lock state signal when the phase-locked loop 201 is in an out-of-lock state. The lock state of the phase-locked loop 201 can be known by the state signal output from the latch circuit 16.

The phase-locked loop circuit 200 accesses the feedback clock and the reference clock of the phase-locked loop 201 through the state monitoring circuit 12, and monitors the phase difference change condition of the two clocks; when the phase difference between the feedback clock and the reference clock is monitored to reach a constant state, a corresponding first trigger signal is output to the latch circuit 16. When the state monitoring circuit 12 monitors that the phase difference between the feedback clock and the reference clock reaches a constant state, the timing circuit 14 starts timing the constant state, and outputs a corresponding second trigger signal to the latch circuit 16 when the timing exceeds a set threshold. When the latch circuit 16 receives the first trigger signal and the second trigger signal, the latch circuit 16 outputs a corresponding status signal, and the phase-locked loop 201 completes locking. Therefore, based on the clock phase detection principle, the state monitoring circuit 12, the timing circuit 14 and the latch circuit 16 are designed on the phase-locked loop circuit 200 to be matched with each other, the locking state of the phase-locked loop 201 can be detected in real time, the detection power consumption is low, and the effect of greatly improving the detection performance is achieved.

In one embodiment, the condition monitoring circuit 12 includes a NAND gate N1 and a flip-flop DFF1, the output of the NAND gate N1 being connected to the clock input of the flip-flop DFF 1. A first input terminal of the nand gate N1 is used for accessing the feedback clock, and a second input terminal of the nand gate N1 is connected to the output terminal of the voltage controlled oscillator of the phase locked loop 201. The D end of the flip-flop DFF1 is used for accessing a reference clock, the Q end of the flip-flop DFF1 is used for outputting a first trigger signal, and the reset end of the flip-flop DFF1 is used for accessing a reset signal.

It can be understood that, for the explanation of the state monitoring circuit 12 in this embodiment, the same principle as the explanation of the state monitoring circuit 12 in each embodiment of the pll state detecting circuit 100 can be referred to, and repeated descriptions are not repeated here.

By adopting the state monitoring circuit 12, the circuit structure is simple, the clock phase detection can be efficiently realized, the circuit design and manufacturing cost is low, the power consumption is low, the locking state real-time monitoring of the phase-locked loop 201 is efficiently realized by matching the timing circuit 14 and the latch circuit 16, and the application cost and the power consumption of the whole phase-locked loop 201 circuit are reduced.

IN one embodiment, as depicted IN fig. 4, the timing circuit 14 includes a flip-flop DFF2, a flip-flop DFF3, a flip-flop DFF4, a flip-flop DFF5, a flip-flop DFF6, and a flip-flop DFF7, as well as a nand gate N2, a not gate IN1, a not gate IN2, a not gate IN3, a not gate IN4, and a not gate IN 5. The clock input end of the flip-flop DFF2 is used for connecting a reference clock, the Q end of the flip-flop DFF2 is connected with the input end of the NOT gate IN1, and the D end of the flip-flop DFF2 is connected with the output end of the NOT gate IN 1. The clock input terminal of the flip-flop DFF3 is connected to the Q terminal of the flip-flop DFF2, the Q terminal of the flip-flop DFF3 is connected to the input terminal of the not gate IN2, and the D terminal of the flip-flop DFF3 is connected to the output terminal of the not gate IN 2.

It can be understood that, for the explanation of the timing circuit 14 in this embodiment, the same principle as the explanation of the timing circuit 14 in each embodiment of the pll status detecting circuit 100 can be referred to, and repeated descriptions are not repeated here.

Through the structural design of the timing circuit 14, in cooperation with the state monitoring circuit 12, the design and manufacturing cost of the phase-locked loop circuit 200 can be further reduced, and the monitoring power consumption can be reduced; the phase difference monitoring of the feedback clock and the reference clock and the realization of the timing function thereof are more efficient, thereby further improving the real-time state detection performance of the phase-locked loop circuit 200.

As shown in FIG. 5, in one embodiment, the latch circuit 16 includes a NAND gate N3 and a NAND gate N4. A first input of the nand gate N3 is used for receiving a first trigger signal. The second input end of the nand gate N4 is used for receiving the second trigger signal, and the output end of the nand gate N4 is used for outputting the state signal. The second input end of the NAND gate N3 is connected with the output end of the NAND gate N4, and the output end of the NAND gate N3 is connected with the first input end of the NAND gate N4.

It can be understood that, for the explanation of the latch circuit 16 in this embodiment, reference may be made to the explanation of the latch circuit 16 using the nand gate structure in each embodiment of the pll status detecting circuit 100, and the same understanding can be obtained, and repeated descriptions will not be provided here.

By using the latch circuit 16 formed by the nand gate, the circuit structure design of the pll circuit 200 can be further simplified, the power consumption is lower, and the state monitoring output is more efficient, so that the detection performance of the pll circuit 200 can be further improved.

As shown IN fig. 6, IN one embodiment, the latch circuit 16 includes a NOR gate NOR1, NOR gate NOR2, and NOR gate IN 6. A first input of the NOR gate NOR1 is used for receiving a first trigger signal. A second input of the NOR gate NOR2 is used for receiving the second trigger signal, an output of the NOR gate NOR2 is connected to an input of the NOR gate IN6, and an output of the NOR gate IN6 is used for outputting the status signal. A second input of the NOR gate NOR1 is connected to the output of the NOR gate NOR2, and an output of the NOR gate NOR1 is connected to the first input of the NOR gate NOR 2.

It can be understood that, for the explanation of the latch circuit 16 in this embodiment, the same explanation as that for the latch circuit 16 adopting the nor gate structure in each embodiment of the pll status detecting circuit 100 can be referred to, and repeated description is not repeated here.

By using the latch circuit 16 formed by the nor gate, the circuit structure design of the pll circuit 200 can be further simplified, the power consumption is lower, the state monitoring output is more efficient, and the detection performance of the pll circuit 200 can be further improved.

In the description herein, reference to the description of the terms "one of the embodiments," "another embodiment," "an embodiment," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A phase-locked loop state detection circuit, comprising:

2. The phase-locked loop state detection circuit of claim 1, wherein the state monitoring circuit comprises a nand gate N1 and a flip-flop DFF1, an output of the nand gate N1 being connected to a clock input of the flip-flop DFF 1;

a first input end of the nand gate N1 is used for accessing the feedback clock, and a second input end of the nand gate N1 is used for accessing the voltage-controlled oscillating clock of the phase-locked loop;

the D end of the flip-flop DFF1 is used for accessing the reference clock, the Q end of the flip-flop DFF1 is used for outputting the first trigger signal, and the reset end of the flip-flop DFF1 is used for accessing a reset signal.

3. The phase-locked loop state detection circuit of claim 2, wherein the timing circuit comprises a flip-flop DFF2, a flip-flop DFF3, a flip-flop DFF4, a flip-flop DFF5, a flip-flop DFF6, and a flip-flop DFF7, and a nand gate N2, a nor gate IN1, a nor gate IN2, a nor gate IN3, a nor gate IN4, and a nor gate IN 5;

the clock input end of the flip-flop DFF2 is used for connecting the reference clock, the Q end of the flip-flop DFF2 is connected with the input end of the NOT gate IN1, and the D end of the flip-flop DFF2 is connected with the output end of the NOT gate IN 1;

reset terminals of the flip-flop DFF2, the flip-flop DFF3, the flip-flop DFF4, the flip-flop DFF5 and the flip-flop DFF6 are respectively connected to a Q terminal of the flip-flop DFF 1;

the setting end of the flip-flop DFF7 is connected to the Q end of the flip-flop DFF1, the clock input end of the flip-flop DFF7 is used for accessing the reference clock, the D end of the flip-flop DFF7 is connected to the output end of the NAND gate N2, the Q end of the flip-flop DFF7 is used for outputting the second trigger signal, the first input end of the NAND gate N2 is connected to the Q end of the flip-flop DFF5, and the second input end of the NAND gate N2 is connected to the Q end of the flip-flop DFF 6.

4. The phase-locked loop state detection circuit of any of claims 1 to 3, wherein the latch circuit comprises a NAND gate N3 and a NAND gate N4;

the first input end of the nand gate N3 is configured to receive the first trigger signal, the second input end of the nand gate N4 is configured to receive the second trigger signal, the output end of the nand gate N4 is configured to output the status signal, the second input end of the nand gate N3 is connected to the output end of the nand gate N4, and the output end of the nand gate N3 is connected to the first input end of the nand gate N4.

5. The phase-locked loop state detection circuit according to any one of claims 1 to 3, wherein the latch circuit comprises a NOR gate NOR1, a NOR gate NOR2, and a NOR gate IN 6;

a first input terminal of the NOR gate NOR1 is configured to receive the first trigger signal, a second input terminal of the NOR gate NOR2 is configured to receive the second trigger signal, an output terminal of the NOR gate NOR2 is coupled to an input terminal of the NOR gate IN6, an output terminal of the NOR gate IN6 is configured to output the status signal, a second input terminal of the NOR gate NOR1 is coupled to an output terminal of the NOR gate NOR2, and an output terminal of the NOR gate NOR1 is coupled to the first input terminal of the NOR gate NOR 2.

6. A phase-locked loop circuit is characterized by comprising a phase-locked loop, a state monitoring circuit, a timing circuit and a latch circuit;

7. The phase-locked loop circuit of claim 6, wherein the condition monitoring circuit comprises a NAND gate N1 and a flip-flop DFF1, wherein an output of the NAND gate N1 is connected to a clock input of the flip-flop DFF 1;

a first input end of the nand gate N1 is used for accessing the feedback clock, and a second input end of the nand gate N1 is connected with an output end of a voltage-controlled oscillator of the phase-locked loop;

8. The phase-locked loop circuit of claim 7, wherein the timing circuit comprises a flip-flop DFF2, a flip-flop DFF3, a flip-flop DFF4, a flip-flop DFF5, a flip-flop DFF6, and a flip-flop DFF7, and a NAND gate N2, a NOT gate IN1, a NOT gate IN2, a NOT gate IN3, a NOT gate IN4, and a NOT gate IN 5;

9. The phase-locked loop circuit of any of claims 6 to 8, wherein the latch circuit comprises a NAND gate N3 and a NAND gate N4;

10. The phase-locked loop circuit of any of claims 6 to 8, wherein the latch circuit comprises a NOR gate NOR1, a NOR gate NOR2, and a NOR gate IN 6;