CN114609837A - Display panel and display device - Google Patents
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- CN114609837A CN114609837A CN202210178854.3A CN202210178854A CN114609837A CN 114609837 A CN114609837 A CN 114609837A CN 202210178854 A CN202210178854 A CN 202210178854A CN 114609837 A CN114609837 A CN 114609837A
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- 239000000758 substrate Substances 0.000 claims abstract description 69
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 29
- 230000000149 penetrating effect Effects 0.000 claims description 41
- 239000004020 conductor Substances 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 description 31
- 239000012535 impurity Substances 0.000 description 11
- 238000009825 accumulation Methods 0.000 description 10
- 206010047571 Visual impairment Diseases 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 210000004027 cell Anatomy 0.000 description 5
- 210000002858 crystal cell Anatomy 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133345—Insulating layers
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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Abstract
The invention provides a display panel and a display device, the display panel comprises an array substrate, a color film substrate and a liquid crystal layer, the array substrate is sequentially provided with a common electrode layer, a first insulating layer, a pixel electrode layer, a connecting graph and an alignment layer, the display panel comprises a plurality of sub-pixel units which are arranged in an array, each sub-pixel unit comprises a pixel electrode and a plurality of scanning lines which extend along a first direction, at least part of the area between two adjacent pixel electrodes along the first direction is a first area, the first insulating layer is provided with at least one first through part to expose part of the common electrode layer, in the direction vertical to the array substrate, the projection of the first through part is positioned in the first area, the projection of the connecting graph at least covers the projection of the first through part, the projection of the connecting graph is not overlapped with the projection of the pixel electrodes, and the connecting graph is contacted with the common electrode layer and the alignment layer, the connection pattern has conductivity. The invention can improve the ghost of the display panel and ensure the display effect and the reliability of the display panel.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
The existing liquid crystal display panel comprises an array substrate, a color film substrate and a liquid crystal layer positioned between the array substrate and the color film substrate, wherein the liquid crystal layer needs alignment films respectively positioned on the array substrate and the color film substrate for alignment, and a liquid crystal material contains a small amount of ionic impurities.
When the liquid crystal display panel is driven by alternating current, positive and negative voltages deviate from the symmetrical center, the voltage deviating from the symmetrical center is direct current bias voltage, the voltage causes the directional accumulation of moving charges in the liquid crystal layer, and the charges cause the alignment film to generate induced polarization and further adsorb free ions to generate charges; as the voltage is applied for a longer time, the charge residue generated by the electrostatic charge separation electrode inside the alignment film increases, and when no voltage is applied, the charge residue generated by the electrostatic charge separation electrode forms a residual dc voltage, so that the liquid crystal molecules are not driven by the signal voltage, and the image sticking occurs.
Disclosure of Invention
In view of this, embodiments of the present invention provide a display panel and a display device, which can effectively improve the afterimage of the display panel and ensure the display effect and reliability of the display panel and the display device.
In a first aspect, an embodiment of the present invention provides a display panel, including:
the liquid crystal display panel comprises an array substrate, a color film substrate and a liquid crystal layer, wherein the liquid crystal layer is positioned between the array substrate and the color film substrate;
the array substrate is provided with a substrate, a public electrode layer, a first insulating layer, a pixel electrode layer, a connecting graph and an alignment layer, wherein the first insulating layer is positioned between the public electrode layer and the pixel electrode layer, the pixel electrode layer is positioned on one side, away from the substrate, of the public electrode layer, and the alignment layer is positioned on one side, away from the substrate, of the pixel electrode layer;
the array pixel structure comprises a plurality of sub-pixel units arranged in an array, wherein each sub-pixel unit comprises a pixel electrode, a plurality of scanning lines extending along a first direction, and a region between at least two adjacent pixel electrodes along the first direction is a first region;
the first insulating layer is provided with at least one first through part to expose part of the common electrode layer, and the projection of the first through part is positioned in the first area in the direction vertical to the array substrate;
in the direction perpendicular to the array substrate, the projection of the connection pattern at least covers the projection of the first through part, the connection pattern does not overlap with the projection of the pixel electrode, the connection pattern is in contact with the common electrode layer and the alignment layer, and the connection pattern has conductivity.
In a second aspect, an embodiment of the present invention further provides a display device, which includes the display panel.
Compared with the prior art, the display panel and the display device provided by the invention at least realize the following beneficial effects:
on one hand, the first penetrating part is arranged on the first insulating layer, part of the common electrode layer is exposed out of the first penetrating part, the connecting pattern at least covers the first penetrating part, namely the connecting pattern is at least partially positioned in the first penetrating part and is electrically connected with the common electrode layer, meanwhile, the connecting pattern is contacted with the alignment layer, the connecting pattern has conductivity, and impurity ions remained on the alignment layer can be guided into the common electrode layer through the connecting pattern and then guided away through the common electrode layer, so that ion accumulation in the box can be reduced, ion dissipation in the box is accelerated, and the ghost of the display panel is improved; on the other hand, because the common electrode is thin, and in the process, the first insulation layer is etched to form the first through part, so that part of the common electrode is exposed, the part of the common electrode may cause damage, and therefore volatilization of substances of the organic film layer on one side, close to the substrate, of the common electrode cannot be prevented.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that are required in the description of the embodiments will be briefly introduced, the drawings described herein are provided to provide further understanding of the present invention and constitute a part of the present invention, and the exemplary embodiments and descriptions thereof of the present invention are provided for explaining the present invention and do not constitute a limitation of the present invention.
Fig. 1 is a schematic top view of a display panel according to an embodiment of the present invention;
FIG. 2 is an enlarged schematic view of a region S of the display panel S of FIG. 1;
FIG. 3 is a schematic cross-sectional view of FIG. 2 along line A-A';
FIG. 4 is another enlarged schematic view of the region S of the display panel of FIG. 1;
FIG. 5 is a schematic cross-sectional view taken along section line A1-A1' of FIG. 4;
FIG. 6 is a schematic enlarged view of the display panel S of FIG. 1;
FIG. 7 is a schematic enlarged view of a region S of the display panel S shown in FIG. 1;
FIG. 8 is a schematic cross-sectional view taken along section line A2-A2' of FIG. 7;
FIG. 9 is a schematic enlarged view of a region S of the display panel S of FIG. 1;
FIG. 10 is a schematic cross-sectional view taken along line B-B' of FIG. 9;
FIG. 11 is a schematic enlarged view of a region S of the display panel S of FIG. 1;
FIG. 12 is a schematic cross-sectional view of FIG. 11 taken along section line C-C';
FIG. 13 is a schematic top view of another display panel according to an embodiment of the present invention;
FIG. 14 is an enlarged view of the area S' of the display panel of FIG. 13;
FIG. 15 is a schematic cross-sectional view of FIG. 14 taken along section line D-D';
FIG. 16 is another enlarged schematic view of the area S' of the display panel of FIG. 13;
FIG. 17 is a schematic top view of another display panel according to an embodiment of the present invention;
FIG. 18 is a schematic enlarged view of a region S of the display panel S shown in FIG. 1;
FIG. 19 is a schematic enlarged view of a region S of the display panel S of FIG. 1;
FIG. 20 is another enlarged schematic view of the area S' of the display panel of FIG. 13;
fig. 21 is a schematic view of a display device according to an embodiment of the invention.
Detailed Description
The embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1 to 3, fig. 1 is a schematic top view of a display panel according to an embodiment of the present invention, fig. 2 is an enlarged schematic view of an area S of the display panel of fig. 1, and fig. 3 is a schematic cross-sectional view of fig. 2 along a sectional line a-a'; the display panel 1 provided by the embodiment of the invention comprises an array substrate 11, a color film substrate 12 and a liquid crystal layer 13, wherein the liquid crystal layer 13 is positioned between the array substrate 11 and the color film substrate 12. The array substrate 11 comprises a substrate 100, a common electrode layer 103, a first insulating layer 105, a pixel electrode layer 104, a connection pattern C1 and an alignment layer 106, wherein the first insulating layer 105 is located between the common electrode layer 103 and the pixel electrode layer 104, the pixel electrode layer 104 is located on the side of the common electrode layer 103 away from the substrate 100, and the alignment layer 106 is located on the side of the pixel electrode layer 104 away from the substrate 100, so that the substrate 100, the common electrode layer 103, the first insulating layer 105, the pixel electrode layer 104 and the alignment layer 106 are arranged on one side of the array substrate 11 from bottom to top; it should be noted that fig. 2 only shows a part of the film layers in order to more intuitively illustrate the design of the present invention, and the thickness of each film layer in fig. 3 does not represent the corresponding film layer thickness in the actual product.
As shown in fig. 1, the display panel 1 has a plurality of sub-pixel units P arranged in an array, the sub-pixel units P include pixel electrodes PE, and the display panel 1 further includes a plurality of scan lines 101 extending along a first direction X; as shown in fig. 2, along the first direction X, at least a portion of an area between two adjacent pixel electrodes PE is a first area a1, the first insulating layer 105 has at least one first through portion K1 (indicated by a dotted line in fig. 2), the first through portion K1 exposes a portion of the common electrode layer 103, and in a direction perpendicular to the array substrate 11, a projection of the first through portion K1 is located in the first area a1, the connection pattern C1 has conductivity, a projection of the connection pattern C1 at least covers a projection of the first through portion K1, the connection pattern C1 does not overlap with the projection of the pixel electrodes PE, and the connection pattern C1 contacts both the common electrode layer 103 and the alignment layer 106.
As described in the background art, the liquid crystal layer 13 of the conventional liquid crystal display panel contains ionic impurities, and a dc bias voltage exists in the liquid crystal cell, which causes the directional accumulation of mobile charges in the liquid crystal layer 13, and these charges cause the alignment film 106 to generate induced polarization and further adsorb free ions to generate charges; on one hand, according to the invention, the first penetrating part K1 is disposed on the first insulating layer 105, the first penetrating part K1 exposes part of the common electrode layer 103, and the connection pattern C1 at least covers the first penetrating part K1, that is, the connection pattern C1 is at least partially located in the first penetrating part K1, and the connection pattern C1 is electrically connected to the common electrode layer 103, meanwhile, the connection pattern C1 is in contact with the alignment layer 106, and the connection pattern C1 has conductivity, so that the impurity ions remaining in the alignment layer 106 can be introduced into the common electrode layer 103 through the connection pattern C1 and then be conducted away through the common electrode layer 103, thereby reducing ion accumulation in the box, accelerating ion dissipation in the box, and improving the afterimage of the display panel; on the other hand, because the common electrode is thinner and the first through portion K1 is formed by etching the first insulating layer 105 in the process, the first through portion K1 exposes a portion of the common electrode, which may be damaged by etching, and thus cannot block the organic film layer on the array substrate 11 on the side of the common electrode close to the substrate 100, such as the evaporation of the material of the planarization layer, and the connection pattern C1 is disposed on the common electrode, which is equivalent to enhancing the blocking capability of the common electrode, so that in the subsequent process, it is possible to suppress the gas formed by some chemical components in the organic film layer from overflowing into the liquid crystal cell, thereby reducing the occurrence of bubbles in the liquid crystal cell due to the evaporation of the material in the organic film layer, ensuring the normal display and better reliability of the display panel, and at the same time, since the first insulating layer 105 is etched, the damage to the common electrode layer 103 is caused, the thickness of the common electrode layer 103 may be non-uniform, and the connection pattern C1 provided on the common electrode layer 103 may reduce the difference in flatness caused by the non-uniform thickness of the common electrode layer 103, thereby ensuring normal display of the display panel.
Optionally, with continuing reference to fig. 1 and fig. 2, the array substrate 11 further includes a data line 102, the data line 102 extends along a second direction Y, and the first direction X intersects with the second direction Y, it should be noted that the present invention does not limit the extending direction of the data line 102 in the same row or two adjacent rows, that is, in the same row, the extending direction of the data line 102 may change or the extending direction of the data line 102 may change in two adjacent rows; the extending direction of the first through portion K1 is the same as the extending direction of the data line 102, the plurality of first through portions K1 are communicated with each other to form the through grooves K11, and the extending direction of the through grooves K11 is the same as the extending direction of the data line 102, but the number of the through grooves K11 is not limited in the present invention, for example, in fig. 2, the number of the through grooves K11 is 1 in the first area a1 between two adjacent pixel electrodes PE, and in other embodiments of the present invention, the number of the through grooves K11 may be 2 or more. Through the fact that the plurality of first penetrating parts K1 are communicated with one another in the first area A1 to form the through groove K11, the first insulating layer 105 is enabled to have a large hollow area, the public electrode in the area with the large area can be exposed, impurity ions remaining on the alignment layer 106 can be led into the public electrode layer 103 through the connecting pattern C1 in a large amount and then led away through the public electrode layer 103, ion accumulation in the box can be reduced to a large extent, ion dissipation in the box is accelerated, and image sticking of the display panel is improved.
Alternatively, as shown in fig. 4 and 5, fig. 4 is another enlarged schematic view of the area of the display panel S of fig. 1, and fig. 5 is a schematic cross-sectional view taken along the sectional line a1-a 1' of fig. 4; along the extending direction of the data line 102, that is, the second direction Y, two adjacent rows of through grooves K11 are isolated from each other, as shown in fig. 4, the through grooves K111 and the through grooves K112 are two adjacent rows of through grooves, the through grooves K111 and the through grooves K112 are isolated from each other, that is, the first insulating layer 105 still exists in the region between the through grooves K111 and the through grooves K112, so that impurity ions remaining on the alignment layer 106 can be led into the common electrode layer 103 through the connection pattern C1 more, and then led away through the common electrode layer 103, under the condition that ions in the box are quickly dissipated, the common electrode layer 103 can be prevented from being damaged by etching in a larger area, thereby reducing the phenomenon that a large amount of gas generated by the organic film layer overflows into the liquid crystal box to a certain extent, and ensuring normal display and reliability of the display panel.
Alternatively, the connection patterns C1 respectively located above two adjacent rows of through grooves K111 and K112 may be isolated, or may be connected together, and the present invention is not limited thereto, for example, in fig. 4, the connection patterns C1 located above two adjacent rows of through grooves K111 and K112 are isolated.
Optionally, with continued reference to fig. 4 and fig. 5, the display panel 1 further includes a supporting pillar 107, and in the above design, in the direction perpendicular to the array substrate 11, the projection of the supporting pillar 107 may be located between two adjacent rows of the through grooves K11, because the first insulating layer 105 still exists in the area between two adjacent rows of the through grooves K11, the area is not etched by the first insulating layer 105, and is flatter than the area of the through grooves K11, and the supporting pillar 107 supports or stands in the area, so that the display panel can be ensured to have good supporting performance.
Optionally, as shown in fig. 6, fig. 6 is another enlarged schematic view of the area of the display panel S of fig. 1; along the extending direction of the data line 102, that is, the second direction Y, two adjacent rows of through grooves K11 have a connecting portion C2, and along the first direction X, the maximum width H1 of the connecting portion C2 is greater than the width H2 of the through groove K11, on one hand, in the extending direction of the data line 102, a whole through groove K11 is etched on the first insulating layer 105, so that the first insulating layer 105 has a larger hollow area, thereby exposing the common electrode in a larger area, so that the impurity ions remaining on the alignment layer 106 can be more introduced into the common electrode layer 103 through the connecting pattern C1, and then are conducted away through the common electrode layer 103, thereby greatly reducing ion accumulation in the box, accelerating ion dissipation in the box, and improving the afterimage of the display panel; on the other hand, in the direction perpendicular to the array substrate 11, since the projection of the connection portion C2 between the two rows of through grooves K11 overlaps the projection portion of the scan line 11, that is, the connection portion C2 is located above the scan line 11, and the scan line 11 is usually covered by the black matrix located on the color filter substrate 12, the maximum width H1 of the connection portion C2 along the first direction is set to be greater than the width H2 of the through groove K11, so that normal display of the display panel is not affected, the hollow area of the first insulating layer 105 can be further increased, and the common electrode with a certain area can be further exposed, so that more impurity ions remaining on the alignment layer 106 can be guided into the common electrode layer 103 through the connection pattern C1 and then guided away through the common electrode layer 103, thereby greatly reducing ion accumulation in the box, accelerating ion dissipation in the box, and on the basis of not affecting display, the afterimage of the display panel is improved to a great extent.
Optionally, with reference to fig. 6, in the direction perpendicular to the array substrate 11, the projection of the connection pattern C1 covers the projection of the connection portion C2, so as to ensure that the portion exposed out of the common electrode layer 103 can be covered by the connection pattern C1, thereby preventing a large amount of gas generated by the organic film layer from overflowing into the liquid crystal cell, and ensuring normal display and reliability of the display panel.
Optionally, referring to fig. 7 and 8, fig. 7 is a further enlarged schematic view of the display panel S area of fig. 1, and fig. 8 is a cross-sectional view taken along the sectional line a2-a 2' of fig. 7; under the above design, in the direction perpendicular to the array substrate 11, the projection of the supporting column 107 can be located within the projections of the through groove K11 and the connecting portion C2, as shown in fig. 7, the supporting column 107 can be set to be longer than the length of the through groove K11 in the extending direction of the through groove K11 in the first direction X, so that the supporting column 107 can be embedded into the recess where the through groove K11 is located, thereby ensuring that the supporting column 107 does not slide under the action of external force, and thus ensuring that the display panel has good support.
Optionally, referring to fig. 3, the plurality of sub-pixel units arranged in an array include a transparent region T1 and a non-transparent region T2, the first through portion K1 may be entirely located in the non-transparent region T2, that is, the first through portion K1 is shielded by the black matrix 121 located on the color filter substrate 12, optionally, the first through portion K1 may be partially located in the non-transparent region T2, and partially located in the transparent region T1, that is, the first through portion K1 extends from the non-transparent region T2 to the transparent region T1, and the black matrix 121 only partially shields the first through portion K1; correspondingly, the connection pattern C1 at least partially covers the first through portion K1, that is, the connection pattern C1 may be entirely located in the non-light-transmitting region T2, partially located in the non-light-transmitting region T2, partially located in the light-transmitting region T1, the connection pattern C1 is partially located in the non-light-transmitting region T2, partially located in the light-transmitting region T1, and the material of the connection pattern C1 may be selected to be a transparent conductive material; as shown in fig. 3, in the direction perpendicular to the array substrate 11, the projection of the first through portion K1 overlaps the projection of the black matrix 121, that is, the first through portion K1 is located in the non-light-transmitting region T2, and the connection pattern C1 extends from the non-light-transmitting region T2 to the light-transmitting region T1, that is, the size of the connection pattern C1 is larger than the size of the first through portion K1, so as to form a better shelter for the first through portion K1, thereby avoiding that the connection pattern C1 cannot completely cover the first through portion K1 when an alignment deviation occurs in the manufacturing process, thereby exposing the common electrode layer 103, avoiding causing an organic film layer to be out-gassed, and effectively ensuring normal display of the display panel.
Optionally, referring to fig. 9 and 10, fig. 9 is another enlarged schematic view of the display panel S region of fig. 1, and fig. 10 is a schematic cross-sectional view of fig. 9 along the sectional line B-B'; in the direction perpendicular to the array substrate 11, the connection pattern C1 coincides with the edge projections of the two opposite sides of the first through portion K1 along the first direction X, that is, the connection pattern C1 is aligned with the edge of the first through portion K1 in the first direction X, optionally, as shown in fig. 8, when the connection pattern C1 is aligned with the edge of the first through portion K1 in the first direction X, the first through portion K1 is located in the projection of the black matrix 121 of the color filter substrate 12, and the connection pattern C1 is also located in the projection of the black matrix 121 of the color filter substrate 12, so as to ensure that the first through portion K1 and the connection pattern C1 are both located in the projection of the non-transmission region, and the connection pattern C1 does not block the transmission region, thereby ensuring the display uniformity in the transmission region; the connection pattern C1 is aligned with the first through portion K1 along the first direction X, so that the connection pattern C1 is effectively isolated from the pixel electrode, thereby preventing the liquid crystal display from being affected.
Optionally, referring to fig. 11 and 12, fig. 11 is a further enlarged schematic view of the display panel S area of fig. 1, and fig. 12 is a cross-sectional view of fig. 11 along a cross-sectional line C-C'; the pixel electrode PE has a plurality of branches PE1, gaps SP are formed between the branches PE1, the first insulating layer 105 has at least one second penetrating portion K2, in the direction perpendicular to the array substrate 11, the projection of the second penetrating portion K2 at least partially overlaps with the projection of the gaps SP, that is, a notch is formed on the first insulating layer 105 at a position corresponding to the gaps SP between the branches PE1 of the pixel electrode PE to form a second penetrating portion K2, the second penetrating portion K2 exposes a portion of the common electrode layer 103, that is, in a region where the second penetrating portion K2 is located, the alignment layer 106 can directly contact the common electrode layer 103; since the liquid crystal display panel rotates the liquid crystal molecules in the liquid crystal layer 13 by the electric field formed between the pixel electrode PE and the common electrode layer 103 to realize display, a larger amount of charges and ions are usually accumulated at the pixel electrode PE than in the region between the pixel electrodes PE, and the second penetrating portion K2 is provided on the first insulating layer 105 at a position corresponding to the gap SP between the branches PE1 of the pixel electrode PE, so that a large amount of charges and ions can be quickly introduced into the common electrode layer 103 through the alignment layer 106 and then be conducted away through the common electrode layer 103, thereby further accelerating reduction of ion accumulation in the cell, accelerating ion dissipation in the cell, and further improving the afterimage of the display panel. Meanwhile, since the size of the gap SP between the branches PE1 of the pixel electrode PE is usually narrow, even if the connection pattern C1 is not added on the second penetrating portion K2 to cover the second penetrating portion K2, the organic film layer in this region will not volatilize a lot of substances, resulting in a lot of gas overflow, and thus the normal display of the display panel will not be affected.
Optionally, referring to fig. 13 to 15, fig. 13 is a schematic top view of another display panel according to an embodiment of the disclosure, fig. 14 is an enlarged schematic view of an area S 'of the display panel of fig. 13, and fig. 15 is a schematic cross-sectional view of fig. 14 along a sectional line D-D'; the display panel 2 has a display area AA and a non-display area NA surrounding the display area AA, as shown in fig. 14, the common electrode layer 103 extends from the display area AA to the non-display area NA, the first insulating layer 105 has at least one third penetrating portion K3 (indicated by a dotted line in fig. 14), a projection of the third penetrating portion K3 overlaps a projection of the common electrode layer 103 located in the non-display area NA in a direction perpendicular to the array substrate 11, and a projection of a connection pattern C1 located at the third penetrating portion K3 covers at least a projection of a third penetrating portion K3, wherein dimensions of the third penetrating portion K3 and the connection pattern C1 may be set according to a size of the common electrode layer 103 expanding from the display area AA to the non-display area NA, only the third penetrating portion K3 is shown as a long through groove in fig. 14, and the long through groove and the connection pattern C1 at least partially surround the display area AA, and in other embodiments of the present invention, the number of the long through groove may be 2 or more, alternatively, a plurality of isolated through-slots may be provided, and the plurality of through-slots at least partially surround the display area AA. The third penetrating portion K3 is disposed on the first insulating layer 105 corresponding to the common electrode layer 103 in the non-display area AA, and the sub-pixel unit P is not disposed in this area, so that a large-area through-opening area can be formed on the first insulating layer 105, thereby exposing the common electrode in a larger area, so that more impurity ions remaining on the alignment layer 106 can be introduced into the common electrode layer 103 through the connection pattern C1 and then guided away through the common electrode layer 103, thereby further reducing ion accumulation in the cell, accelerating ion dissipation in the cell, and improving the image sticking of the display panel.
Optionally, referring to fig. 13 and 16, fig. 16 is another enlarged schematic view of the area S' of the display panel of fig. 13; in the non-display area NA of the display panel 2, which has the shielding electrode SD, and optionally the shielding electrode SD and the common electrode layer 103 are located in the same layer and are made of transparent conductive material, the shielding electrode SD is usually connected to the ground terminal, or connected to the driving circuit chip, and then grounded through the driving circuit chip, the first insulating layer 105 has at least one fourth through portion K4, in the direction perpendicular to the array substrate 11, the projection of the fourth through portion K4 overlaps the projection of the shielding electrode SD, and the projection of the connection pattern C1 located at the fourth through portion K4 at least covers the projection of the fourth through portion K4, wherein the dimensions of the fourth through portion K4 and the connection pattern C1 can be set according to the size of the shielding electrode SD, only the fourth through portion K4 is shown as a long through groove in fig. 16, and the long through groove and the connection pattern C1 at least partially surround the display area AA, in other embodiments of the present invention, the number of the long through grooves may also be 2 or more, and optionally, a plurality of through grooves isolated from each other may also be provided, and the plurality of through grooves at least partially surround the display area AA. The fourth penetrating portion K4 is disposed on the first insulating layer 105 corresponding to the shielding electrode SD in the non-display area AA, and the shielding electrode SD is connected to the ground end, and a large-area through-cut region can be formed on the first insulating layer 105 corresponding to the shielding electrode SD, so that the shielding electrode SD with a larger area can be exposed, and more impurity ions remaining on the alignment layer 106 can be introduced into the shielding electrode SD through the connection pattern C1 and then guided away through the shielding electrode SD, thereby accelerating reduction of ion accumulation in the box, acceleration of ion dissipation in the box, and great improvement of afterimage of the display panel.
Optionally, as shown in fig. 17, fig. 17 is a schematic top view of another display panel according to an embodiment of the present invention; the non-display area NA of the display panel 3 has a shielding electrode SD at least partially surrounding the display area AA, the non-display area NA of the display panel 3 has a first non-display area B1 and a second non-display area B2, i.e., left and right frame areas in fig. 17, which are oppositely disposed along the first direction X, a fourth non-display area B4, i.e., a lower frame area in fig. 17, in which the driving circuit chip IC is located, and a third non-display area B3, i.e., an upper frame area in fig. 17, which is opposite to the fourth non-display area B4, in which the shielding electrode SD is located, the shielding electrode SD is located in the left and right frame areas and the upper frame area, and the first insulating layer 105 corresponding to the shielding electrode SD is provided with a fourth penetrating portion K4 and a corresponding connection pattern C1, which are also located in the left and right frame areas and the upper frame areas.
Optionally, the connection pattern C1 may be a transparent conductive material, and the transparent conductive material has high light transmittance, so that the display panel does not suffer from insufficient light flux due to shielding of the connection pattern C1 with a large area, thereby ensuring the brightness of the display panel; optionally, the connection pattern C1 may be located on the same layer as the pixel electrode PE, and the same mask is used and the same process is performed simultaneously, so that the mask and the process do not need to be increased, which is beneficial to saving the process cost of the display panel.
Optionally, referring to fig. 18 to 19, fig. 18 is another enlarged schematic view of the area S of the display panel of fig. 1, and fig. 19 is another enlarged schematic view of the area S of the display panel of fig. 1; the first through portion K1 can be a through hole K12 (indicated by dotted lines in fig. 18 and 19), the through hole K12 is relatively easier to prepare, and does not cause continuous exposure of the large-area common electrode layer 103, that is, in the first region a1 between two adjacent pixel electrodes PE, the first insulating layer 105 forms a plurality of through holes K12, the common electrode layer 103 is exposed at the through hole K12, and the first insulating layer 105 is further present between two adjacent through holes K12, and part of the common electrode layer 103 is covered by the first insulating layer 105, so that impurity ions remaining on the alignment layer 106 can be relatively quickly introduced into the common electrode layer 103 through the connection pattern C1, and then guided away through the common electrode layer 103, and under the condition that ions in the cell are quickly dissipated, the common electrode layer 103 can be prevented from being damaged by etching with a relatively large area, thereby preventing the organic film layer from generating a large amount of gas to overflow into the liquid crystal cell to a certain extent, thereby ensuring normal display and reliability of the display panel. Correspondingly, as shown in fig. 18, the connection patterns C1 located at two adjacent through holes K12 may be isolated from each other, or, as shown in fig. 19, at least some of the connection patterns C1 located at two adjacent through holes K12 may be connected to each other, which is not limited in the present invention. Alternatively, in the direction perpendicular to the array substrate 11, the projection shape of the through hole K12 may be a circle, an ellipse, a regular polygon, a rectangle, or the like, and correspondingly, the projection shape of the connection pattern C1 located at the through hole K12 may also be one of a circle, an ellipse, a regular polygon, a rectangle, or the like, which is not limited in the present invention.
Alternatively, as shown in fig. 20, fig. 20 is another enlarged schematic view of the region S' of the display panel of fig. 13; for example, in fig. 20, the third penetrating portion K3 and the fourth penetrating portion K4 located in the non-display area NA may also be through holes, and the third penetrating portion K3 located in the non-display area NA is a through hole K32, and the orthographic projection size of the through hole K32 may be larger than the orthographic projection size of the through hole K12 located in the display area AA, and the projection edge of the connection pattern C1 located at the through hole K32 may be aligned with the projection edge of the through hole K32, optionally, the projection of the connection image C1 may also cover the projection of the through hole K32, and the present invention is not limited thereto, and similarly, the fourth penetrating portion K4 and the connection pattern C1 located at the fourth penetrating portion K4 may also be correspondingly configured, and details are not described herein again.
An embodiment of the present invention further provides a display device, where the display device includes a display terminal product such as a smart phone, a flat panel display device, and a notebook display device, as shown in fig. 21, fig. 21 is a schematic view of the display device provided in the embodiment of the present invention, the display device 4 includes the display panel 1, and beneficial effects generated by the display device 4 are also the beneficial effects described in the above embodiment, which are not described again here.
The foregoing description shows and describes several preferred embodiments of the present application, but as aforementioned, it is to be understood that the application is not limited to the forms disclosed herein, but is not to be construed as excluding other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the application, which is to be protected by the claims appended hereto.
Claims (15)
1. A display panel, comprising:
the liquid crystal display panel comprises an array substrate, a color film substrate and a liquid crystal layer, wherein the liquid crystal layer is positioned between the array substrate and the color film substrate;
the array substrate is provided with a substrate, a common electrode layer, a first insulating layer, a pixel electrode layer, a connecting pattern and an alignment layer, wherein the first insulating layer is positioned between the common electrode layer and the pixel electrode layer, the pixel electrode layer is positioned on one side of the common electrode layer, which is far away from the substrate, and the alignment layer is positioned on one side of the pixel electrode layer, which is far away from the substrate;
the array pixel structure comprises a plurality of sub-pixel units arranged in an array, wherein each sub-pixel unit comprises a pixel electrode, a plurality of scanning lines extending along a first direction, and a region between at least two adjacent pixel electrodes along the first direction is a first region;
the first insulating layer is provided with at least one first through part to expose part of the common electrode layer, and the projection of the first through part is positioned in the first area in the direction vertical to the array substrate;
in the direction perpendicular to the array substrate, the projection of the connection pattern at least covers the projection of the first through part, the connection pattern does not overlap with the projection of the pixel electrode, the connection pattern is in contact with the common electrode layer and the alignment layer, and the connection pattern has conductivity.
2. The display panel according to claim 1,
the array substrate comprises data lines, the extending direction of the first penetrating parts is the same as the extending direction of the data lines, the first penetrating parts are communicated with one another to form through grooves, and the extending direction of the through grooves is the same as the extending direction of the data lines.
3. The display panel according to claim 2,
and along the extending direction of the data line, the through grooves in two adjacent rows are isolated from each other.
4. The display panel according to claim 3,
the display panel is provided with a support column, and the projection of the support column is positioned between two adjacent rows of the through grooves in the direction perpendicular to the array substrate.
5. The display panel according to claim 2,
follow the extending direction of data line, adjacent two rows logical groove has connecting portion, and follows first direction, the maximum width of connecting portion is greater than the width that leads to the groove.
6. The display panel according to claim 5,
and in the direction vertical to the array substrate, the projection of the connecting pattern covers the projection of the connecting part.
7. The display panel according to claim 6,
the display panel is provided with a support column, and the projection of the support column is positioned in the projection of the through groove and the connecting part in the direction vertical to the array substrate.
8. The display panel according to claim 1,
in the direction perpendicular to the array substrate, the connection pattern is superposed with the edge projections of two opposite sides of the first through part along the first direction.
9. The display panel according to claim 1,
the pixel electrode is provided with a plurality of branches, gaps are formed among the branches, the first insulating layer is provided with at least one second penetrating part, and the projection of the second penetrating part is overlapped with the gap projection in the direction perpendicular to the array substrate.
10. The display panel according to claim 1,
the display panel is provided with a display area and a non-display area surrounding the display area, and the common electrode layer extends from the display area to the non-display area;
the first insulating layer is provided with at least one third penetrating part, and the projection of the third penetrating part is overlapped with the projection of the common electrode layer in the non-display area in the direction vertical to the array substrate;
in a direction perpendicular to the array substrate, the projection of the connection pattern covers the projection of the third penetrating part.
11. The display panel according to claim 1,
the display panel is provided with a display area and a non-display area surrounding the display area, the display panel is provided with a shielding electrode, the shielding electrode is positioned in the non-display area, and the shielding electrode and the common electrode layer are positioned in the same layer;
the first insulating layer is provided with at least one fourth penetrating part, and the projection of the fourth penetrating part is overlapped with the projection of the shielding electrode in the direction vertical to the array substrate;
in a direction perpendicular to the array substrate, the projection of the connection pattern covers the projection of the fourth penetrating part.
12. The display panel according to claim 1,
the connection pattern is made of transparent conductive material.
13. The display panel according to claim 12,
the connection pattern is in the same layer as the pixel electrode.
14. The display panel according to claim 1,
the first through part is a through hole.
15. A display device comprising the display panel according to any one of claims 1 to 14.
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| US20160161776A1 (en) * | 2014-12-09 | 2016-06-09 | Au Optronics Corporation | Display panel |
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| CN111430373A (en) * | 2020-03-31 | 2020-07-17 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN112258991A (en) * | 2020-11-13 | 2021-01-22 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
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| CN101008754A (en) * | 1996-10-22 | 2007-08-01 | 精工爱普生株式会社 | Liquid crystal panel substrate and liquid crystal panel |
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| US20160161776A1 (en) * | 2014-12-09 | 2016-06-09 | Au Optronics Corporation | Display panel |
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