CN114598423A - Method, device and medium for demodulation and decoding by combining GMSK and LDPC - Google Patents
Method, device and medium for demodulation and decoding by combining GMSK and LDPC Download PDFInfo
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Abstract
The embodiment of the invention discloses a method, a device and a medium for demodulating and decoding by combining GMSK and LDPC; the method can comprise the following steps: performing low-pass filtering and down-sampling processing on a baseband digital signal of a received signal to obtain a filtered digital signal; the receiving signal is subjected to LDPC coding by a transmitting terminal, then modulated according to GMSK, and transmitted to a free space in a time diversity mode; carrying out differential processing on the filtered digital signal to obtain a differential digital signal; diversity combining is carried out on the digital signals after the difference according to pilot frequency data and information data; carrying out frame synchronization and bit synchronization on the digital signals after diversity combination to obtain a synchronization position; based on the synchronous position, demodulating and decoding the diversity-combined digital signal by combining GMSK and LDPC in an internal and external iteration mode to obtain decoded data.
Description
Technical Field
The embodiment of the invention relates to the technical field of wireless communication, in particular to a method, a device and a medium for demodulating and decoding by combining Gaussian Minimum Shift Keying (GMSK) and Low Density Parity Check (LDPC).
Background
A Low Density Parity Check (LDPC) code is a linear block code that can be described by a sparse Check matrix, which was originally proposed by Gallager in 1962 and is also called a Gallager code. The LDPC code has decoding performance which is very close to Shannon (Shannon) limit, and the linear decoding complexity is lower; therefore, the LDPC code has important application value in both theory and practical application. However, when the LDPC decoding algorithm is implemented in real hardware, a certain storage space needs to be consumed to store the relevant check matrix, so that a large hardware resource is required.
The combined Gaussian Filtered Minimum Shift Keying (GMSK) is a continuous phase modulation mode and has a high spectrum utilization rate. According to the modulation scheme, the modulated non-return-to-zero data passes through the Gaussian pulse forming filter firstly, so that side lobes on a frequency spectrum are reduced, the frequency spectrum is more compact, the out-of-band energy radiation is smaller, and the adjacent channel interference is smaller. The conventional receiving-end processing scheme for GMSK is to separate demodulation and decoding, and such processing cannot fully utilize the correlation between received symbols, and thus cannot achieve the best demodulation effect.
With the current increasing requirements for communication capability and communication reliability, a processing scheme with better performance is required to process the GMSK receiving end.
Disclosure of Invention
In view of this, embodiments of the present invention are to provide a method, an apparatus, and a medium for demodulation and decoding combining GMSK and LDPC; the method can realize reliable demodulation and decoding of the signals under the environment with low signal-to-noise ratio, ensure the safety of information transmission, improve the interference tolerance of a communication system and reduce the complexity of the system.
The technical scheme of the embodiment of the invention is realized as follows:
in a first aspect, an embodiment of the present invention provides a demodulation and decoding method combining Gaussian Minimum Shift Keying (GMSK) and Low Density Parity Check (LDPC), where the method is applied to a receiving device, and the method includes:
performing low-pass filtering and down-sampling processing on a baseband digital signal of a received signal to obtain a filtered digital signal; the receiving signal is subjected to LDPC coding by a transmitting terminal, then modulated according to GMSK, and transmitted to a free space in a time diversity mode;
carrying out differential processing on the filtered digital signal to obtain a differential digital signal;
diversity combining is carried out on the digital signals after the difference according to pilot frequency data and information data;
carrying out frame synchronization and bit synchronization on the digital signals after diversity combination to obtain a synchronization position;
based on the synchronous position, demodulating and decoding the diversity-combined digital signal by combining GMSK and LDPC in an internal and external iteration mode to obtain decoded data.
In a second aspect, an embodiment of the present invention provides a demodulation and decoding method combining Gaussian Minimum Shift Keying (GMSK) and Low Density Parity Check (LDPC), where the method is applied to a transmitting end device, and the method includes:
after information data sent by an information source is coded according to an LDPC coding algorithm, the coded information data and pilot frequency data are combined into frame data to be sent of a time diversity structure in a mode of pilot frequency data for multiple times and information data for multiple times;
and performing GMSK modulation on the frame data to be sent, and sending the modulated frame data to be sent to a free space, so that the receiving end device performs demodulation and decoding according to the received signal by using the joint GMSK and LDPC demodulation and decoding method according to the first aspect.
In a third aspect, an embodiment of the present invention provides a receiving end device, where the receiving end device includes: a preprocessing part, a differential processing part, a diversity combining part, a synchronizing part and a joint demodulation decoding part; wherein the content of the first and second substances,
the preprocessing part is configured to perform low-pass filtering and down-sampling processing on a baseband digital signal of a received signal to obtain a filtered digital signal; the receiving signal is subjected to LDPC coding by a transmitting terminal, then modulated according to GMSK, and transmitted to a free space in a time diversity mode;
the differential processing part is configured to perform differential processing on the filtered digital signal to obtain a differential digital signal;
the diversity combining part is configured to perform diversity combining on the differentiated digital signals according to pilot frequency data and information data respectively;
the synchronization part is configured to perform frame synchronization and bit synchronization on the diversity-combined digital signal to obtain a synchronization position;
and the joint demodulation and decoding part is configured to demodulate and decode the diversity-combined digital signal by joint GMSK and LDPC in an internal and external iteration mode based on the synchronous position to obtain decoded data.
In a fourth aspect, an embodiment of the present invention provides a transmitting end device, where the transmitting end device includes: a coding section, a time diversity combining section, a modulation section, and a transmission section; wherein, the first and the second end of the pipe are connected with each other,
the encoding part is configured to encode information data sent by a source according to an LDPC encoding algorithm;
the time diversity combination part is configured to combine the coded information data and the pilot frequency data into frame data to be sent with a time diversity structure according to a mode of multiple times of pilot frequency data and multiple times of information data;
the modulation part is configured to perform GMSK modulation on the frame data to be transmitted;
the transmitting part is configured to transmit the modulated frame data to be transmitted to a free space, so that the receiving end device performs demodulation and decoding according to the received signal by the demodulation and decoding method combining GMSK and LDPC according to the first aspect.
In a fifth aspect, an embodiment of the present invention provides a communication device, where the communication device includes a communication interface, a memory, and a processor; the various components are coupled together by a bus system; wherein the content of the first and second substances,
the communication interface is used for receiving and sending signals in the process of receiving and sending information with other external network elements;
the memory for storing a computer program operable on the processor;
the processor is configured to, when running the computer program, execute the steps of the method for demodulating and decoding joint GMSK and LDPC according to the first aspect or the second aspect.
In a sixth aspect, an embodiment of the present invention provides a computer storage medium, where the computer storage medium stores a demodulation and decoding program combining GMSK and LDPC, and the demodulation and decoding program combining GMSK and LDPC is executed by at least one processor to implement the steps of the demodulation and decoding method combining GMSK and LDPC according to the first aspect or the second aspect.
The embodiment of the invention provides a method, a device and a medium for demodulating and decoding by combining GMSK and LDPC; the demodulation and decoding of GMSK and LDPC under low signal-to-noise ratio of signals are realized through joint iteration, the interference tolerance of a system is improved by adopting a time diversity mode, the influence caused by frequency deviation is reduced by adopting a difference mode, diversity combination is carried out, the complexity of the system is reduced by constructing a quasi-cyclic LDPC matrix, the reliable demodulation of GMSK signals can be realized under low signal-to-noise ratio, and the safety of information transmission is ensured.
Drawings
Fig. 1 is a schematic diagram illustrating a communication system according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a method for a receiving end device to perform demodulation and decoding combining GMSK and LDPC according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating the position and size of a correlation peak after performing sliding correlation by using a matched filter according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a GMSK modulation flow provided in an embodiment of the present invention;
FIG. 5 is a schematic diagram of an LDPC decoding process according to an embodiment of the present invention;
fig. 6 is a schematic diagram illustrating an update flow of a check node according to an embodiment of the present invention;
fig. 7 is a schematic diagram illustrating a variable node processing unit and a decision output unit according to an embodiment of the present invention;
fig. 8 is a schematic flow chart of a joint GMSK demodulation and LDPC decoding scheme provided in an embodiment of the present invention;
fig. 9 is a flowchart illustrating a method for performing demodulation and decoding by combining GMSK and LDPC by a transmitting end device according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a frame structure of time diversity transmission according to an embodiment of the present invention;
FIG. 11 is a diagram of bit error rate performance for joint demodulation iterations under different SNR conditions;
fig. 12 is a schematic diagram illustrating a receiving end device according to an embodiment of the present invention;
fig. 13 is a schematic diagram of a transmitting end device according to an embodiment of the present invention;
fig. 14 is a schematic diagram of a specific hardware structure of a communication device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.
Aiming at the content related in the background technology, the inventor finds that a check matrix of a quasi-cyclic LDPC code (QC-LDPC) has the characteristic of quasi-cycle in the implementation process, can obtain the information of the whole check matrix by using the quasi-cycle characteristic only by storing the shift frequency information of the check matrix according to the characteristic of quasi-cycle, can reduce the storage space, and adopts a block-shaped parallel mode to carry out iterative update in the decoding process, namely, the consumption of hardware resources can be reduced, the time consumed by decoding can also be reduced, and the balance of resource consumption and time consumption is achieved. In addition, because correlated log-likelihood ratio information is generated or needed in both the GMSK demodulation process and the LDPC decoding process, two independent processes, namely the GMSK demodulation process and the LDPC decoding process in the conventional scheme, can be jointly processed to realize the demodulation and decoding of the joint GMSK and LDPC, and the correlated information between all received code elements is fully utilized, so that the error code probability is reduced, reliable demodulation is formed, and the safety of information transmission is ensured.
Based on this, the embodiment of the present invention is intended to provide a demodulation and decoding scheme combining GMSK and LDPC, and for this scheme, referring to fig. 1, a communication system 10 capable of applying the technical solution of the embodiment of the present invention is shown, where this system 10 may include a transmitting end device 11 and a receiving end device 12. In conjunction with fig. 1, the receiving end device 12 may perform a method of joint GMSK and LDPC demodulation and decoding as shown in fig. 2, where the method may include:
s201: performing low-pass filtering and down-sampling processing on a baseband digital signal of a received signal to obtain a filtered digital signal; the receiving signal is subjected to LDPC encoding by the transmitting terminal device 11, modulated according to GMSK, and transmitted to a free space in a time diversity manner;
s202: carrying out differential processing on the filtered digital signal to obtain a differential digital signal;
s203: diversity combining is carried out on the digital signals after the difference according to pilot frequency data and information data;
s204: carrying out frame synchronization and bit synchronization on the digital signals after diversity combination to obtain a synchronization position;
s205: based on the synchronous position, demodulating and decoding the diversity-combined digital signal by combining GMSK and LDPC in an internal and external iteration mode to obtain decoded data.
By the technical scheme shown in fig. 2, demodulation and decoding of GMSK and LDPC under a low signal-to-noise ratio of a signal are realized through joint iteration, a time diversity mode is adopted to improve an interference tolerance of a system, a difference mode is adopted to reduce an influence caused by frequency offset and perform diversity combining, a quasi-cyclic LDPC matrix is constructed to reduce a complexity of the system, reliable demodulation of GMSK signals can be realized under a low signal-to-noise ratio, and safety of information transmission is ensured.
For the technical solution shown in fig. 2, in some possible implementation manners, the performing differential processing on the filtered digital signal to obtain a differential digital signal includes:
and carrying out conjugate multiplication on the current filtered digital signal and the delay signal of the current filtered digital signal to obtain the differential digital signal.
For the above implementation, in particular, since GMSK is a continuous phase modulation scheme, signal receiving errors may be caused due to frequency offset and phase offset, and since the transmitting end apparatus 11 employs a time diversity technique, diversity combining needs to be performed on the received signals of the receiving end apparatus 12. In addition, the received signal cannot be directly subjected to simple signal addition since GMSK transfers information using phase change rather than fixed phaseThe difference processing is required to be performed first. For the differential processing, the detailed process is to perform conjugate multiplication on the delayed received signal and the current received signal, so as to obtain the sine and cosine values of the phase change of the front and rear signals, and the digital baseband signal of the received signal is set as follows: r (k) ═ i (k) + j × q (k); then the differentiated I way data Id(k)And Q data Qd(k)Respectively as follows:
Id(k)＝I(k)I(k-1)+Q(k)Q(k-1)
Qd(k)＝I(k)Q(k-1)-Q(k)I(k-1)。
for the technical solution shown in fig. 2, in some possible implementations, the diversity combining the differentiated digital signals according to pilot data and information data includes:
and respectively carrying out equal gain combination after carrying out time delay on the pilot frequency data and the information data in the digital signals after the difference, and respectively obtaining the combined pilot frequency data and the combined information data.
For the above implementation manner, specifically, the diversity combining scheme adopted in the embodiment of the present invention belongs to equal gain combining, for example, the time diversity transmission manner adopted by the sending end device 11 is set to send three segments of pilot data first and then three segments of information data, and accordingly, the receiving end device 12 needs to combine the information data length and the pilot data length respectively. The receiving end device 12 sets the number of sampling points per chip to be 8, the pilot data length to be 96, and the information data length to be 2880, so that the total length of the pilot data is 96 × 8 — 762, that is, the pilot needs to perform equal gain combining of 762 data length, and the information data needs to perform equal gain combining of 2880 × 8 — 23040 in the same manner.
Based on the foregoing implementation manner, in some examples, the performing frame synchronization and bit synchronization on the diversity-combined digital signal to obtain a synchronization position includes:
matching and filtering the combined pilot frequency data through a matched filter taking waveform data after the difference of the three sections of pilot frequency data as coefficients;
determining a local peak value in the matched and filtered data as a maximum value in correlation values appearing in frame data according to a relative threshold strategy;
and determining the optimal sampling point as the synchronous position according to the maximum value of the frame synchronization and the number of the sampling points.
For the above example, it should be noted that the purpose of synchronization is to find the starting point of information data transmission in each frame and provide an accurate bit synchronization point for the subsequent joint demodulation decoding. The embodiment of the invention adopts a scheme of adopting a matched filter to carry out sliding correlation. In detail, the local pseudo code data used for sliding correlation is correlated with the combined differential signal. For example, the local pseudo code sequence uses the differential complex information after 32 × 3 long PN sequence modulation, and similarly, 8 points per chip sample, that is, the length of the local pseudo code sequence is 3 × 32 × 8, the local pseudo code sequence is divided into three sections, which are respectively used as coefficients of a filter, and a scheme of a matched filter is used to perform sliding correlation, as shown in fig. 3, and finally, 3 modulus values are added to obtain a correlation amplitude.
Specifically, since the transmitting-end device 11 adopts a diversity transmission manner, the correlation peak is not unique, and the position and size of the correlation peak after correlation shown in fig. 3 are referred to continuously. Since the correlation amplitude decreases as the snr deteriorates, the embodiments of the present invention cannot perform frame synchronization using only the absolute threshold method in order to ensure that the captured peak is maximum.
In detail, the specific capturing steps in the frame synchronization process are as follows:
first, the captured current sample point A is guaranteedr(k)The former sample point at the 96 th-8 th-768 position and the latter sample point at the 96 th-8 th-768 position are both smaller than the current sample point Ar(k)Namely, the following conditions are satisfied: a. ther(k)≥λ1Ar(k+768)、……、Ar(k)≥λ1Ar(k-768)Wherein λ is1A coefficient representing a setting;
then, a relative threshold method is adopted, namely the threshold value is added to 2 signals before the current sample point value and 2 signals after the current sample point value, and the sum is multiplied by a set threshold coefficient, namely, A is satisfiedr(k)≥Threshold，Wherein Threshold β (a)r(k-2)+Ar(k-1)+Ar(k+1)+Ar(k+2)) β represents a set coefficient; when the two conditions are met, the current sample value can be considered as a correlation peak value preliminarily.
Finally, it is necessary to ensure that the correlation peak of the current sample value is the maximum of the correlation values present in this frame, i.e. to determine whether a is satisfiedr(k)α max frame, where max frame max (A)r(n)) K-8, i.e. max _ frame is the largest of the correlation peaks before the current chip in the frame, and this value is zeroed again after synchronization is completed. Alpha is a coefficient greater than zero.
When the three conditions are met and the duration is longer than the duration of three sampling points, the peak value is considered to be true, and then the frame synchronization is considered to be completed.
For bit synchronization, the chips are extracted periodically to find the best sampling point of the signal. In the embodiment of the present invention, the number of chip samples is set to 8, that is, the best sample is extracted from 8 samples. The position of the frame sync is used to find the largest correlation peak around it. And performing serial-parallel conversion on the correlation values, and comparing the amplitude of eight correlation values near the frame synchronization position to determine the optimal sampling point of the eight correlation values. The best sampling point thus obtained is then the determined synchronization position.
For the technical solution shown in fig. 2, in some possible implementations, the performing, based on the synchronization position, demodulation and decoding on the diversity-combined digital signal by using a joint GMSK and LDPC in an internal and external iteration manner to obtain decoded data includes:
performing correlation calculation according to the information data in the digital signal after diversity combination and the path information in different states to obtain initial log-likelihood ratio information of the state from the previous state to the current time; and entering external iteration;
updating the forward and backward path metric information based on the initial log-likelihood ratio information and the MAX-LOP-MAP algorithm in the current external iteration process;
obtaining updated log-likelihood ratio information of the current external iteration process according to the initial log-likelihood ratio information, the forward path metric information and the backward path metric information;
taking the updated log-likelihood ratio information of the current external iteration process as the initialized log-likelihood ratio information for LDPC decoding;
circularly and alternately updating information transmitted to the variable nodes by the check nodes and information transmitted to the check nodes by the variable nodes by utilizing the initialized log-likelihood ratio information for LDPC decoding in an internal iteration mode until a set internal iteration number is reached;
when the set internal iteration times are reached, outputting variable node information obtained by updating in the final internal iteration process;
if the current external iteration times are not the set external iteration times, the variable node information obtained by updating in the final internal iteration process is used as initial log-likelihood ratio information for performing the next external iteration process;
and if the current external iteration times are the set external iteration times, outputting the variable node information obtained by updating in the final internal iteration process as decoded data obtained by demodulating and decoding the combination of GMSK and LDPC.
For the above implementation manner, it should be noted that, for the GMSK modulation process, a Max-Log-Map algorithm is used in the embodiment of the present invention, as shown in fig. 4, after the digital signal after diversity combining is obtained, initial path metric information of information data therein may be calculated, that is, a signal to be demodulated is correlated with path information of different states stored in advance by the receiving end device 11, so as to obtain Log likelihood ratio information of a state at the moment reached by a previous state, that is, the initial Log likelihood ratio information is used as the initial path metric information; in this embodiment, the number of states known by GMSK modulation is 16 in total, each of which has 2 state transition paths, and the number of states subjected to the differentiation is 8, each of which has 2 state transition paths. Based on this, initial log-likelihood ratio information λk[ci(e)；I]As shown in the following formula：
Wherein c (e) represents a code word symbol; n is 1,2.. N denotes an nth sample point of the reception symbol at time k,
and
the in-phase component and quadrature component of the locally stored initial state path information,
representing the current sampling point to correspond to the locally stored 16 phase values; transmission symbol is set to
It can be seen that one chip needs to calculate initial likelihood information of 16 paths.
Then, the forward and backward path metric information can be updated by using the above information, and when the forward path metric information is calculated as shown in the following formula, it can be known that the path metric information of the current state is related to the previous state;
wherein the content of the first and second substances,
i.e. the last (k-1) state
State metric information of (2); lambda [ alpha ]k(c (e); I) is selected from
To s-stateInitial path metric information, λk(u (e); I) is likelihood ratio information of the k-th bit channel information, may be likelihood information after GMSK demodulation, or may be returned after LDPC decoding.
The three pieces of transfer information of different paths are added and compared, and the largest one is selected as the likelihood information of the present state, so that the forward path metric information is updated in order.
Similarly, it can be seen that the calculated backward path metric information is as follows:
as can be seen from the above equation, the path metric information of the state at this time is related to the next (k +1 th) state, and therefore, the backward path metric information is updated in the reverse order. When the path metric information is updated, the accumulated value of all the path metric information reaching the state at the moment is calculated, and the maximum value is regarded as the optimal path for storage.
Finally, according to the formula, the initial path metric information, the forward path metric information and the backward path metric information are used for calculating to obtain updated log likelihood ratio information lambdak(u (e); O), when the set number of iterations is reached, the information is regarded as GMSK demodulated signal and output, and when the set number of iterations is not reached, the likelihood information lambda is outputk(u (e); O) is re-used as the initial log-likelihood ratio information lambdak(u (e); I), iteration is performed again.
In addition, it should be noted that, for the LDPC decoding process, the correction minimization sum algorithm is preferably used for LDPC decoding, the correction factor is 0.8, and the flow is shown in fig. 5. Firstly, initializing the variable nodes and the check nodes, namely processing and storing LLR information entering a decoding module. L is(1)(qij) Indicating the information passed from the initialization variable node i to the check node j, L(1)(rji) In order to initialize the information transmitted to the variable node i by the check node j, the specific calculation method is shown as the following formula;
L(1)(rji)＝0,j＝1,2...m,i＝1,2...n
L(1)(qij)＝L(Pi),i＝1,2...n,j＝1,2...m
wherein m is the number of rows of the check matrix, and m is more than 0; n is the code length, and n is more than 0; l (P)i) Is a log likelihood ratio of channel information of an ith bit. Because the LDPC code adopted by the embodiment of the invention is a Quasi-cyclic LDPC code (QC-LDPC, Quasi-Cyslic LDPC), the matrix structure can adopt a Quasi-cyclic structure, so the stored address only needs to set the first non-zero position of the cyclic matrix, other non-zero positions can be obtained according to the Quasi-cyclic characteristic, and other non-zero positions of the check matrix do not need to be stored, thereby greatly reducing the storage resource.
Then, when updating the check node using the variable node information, the xor value of the minimum value, the second minimum value, and the sign bit is obtained from the absolute value of all the obtained information, and then the updated likelihood information can be calculated according to the following formula.
Wherein L is(l-1)(qi'j) The information transmitted from the variable node i to the check node j of the (L-1) th cycle is represented, and the updated L(l)(rji) The information transmitted to the variable node i for the first cyclic check node j; rj represents; and alpha is shown. The updating of the check nodes is illustrated in fig. 6.
Then, the variable nodes are updated by using the check node information as shown in the following formula:
wherein L is(l)(qij) Representing information transmitted from the variable node i to the check node j of the first circulation; l is(l)(rj'i) Information which represents that the ith cyclic check node j transmits to the variable node i; qiRepresents; that is, the variable node information is updated to the sum of the check node information and the initial LLR information associated therewith, in addition to the information of the current check node. In detail, in the implementation process, the variable node processing unit and the decision output unit are as shown in fig. 7.
Then, the cycle times are judged, if the cycle times are not reached, the cycle updating of the check node information and the variable node information is continued, and if the set iteration times are reached, the updated variable node information L is updated(l)(qij) When the variable node information is output as the decision information, it should be noted that the variable node information at this time is represented by the following equation, and should be all check node information and initial log likelihood ratio information L (P) associated therewithi) And (4) summing.
And then, hard decision is carried out on the sign bit according to the positive and negative of the sign bit. If L (Q)i) If > 0, it is judged to be 1, and if L (Q)i) If < 0, the signal is judged to be zero, and if demodulation decoding iteration is needed, the signal can be directly considered to be L (Q)i) Iterations of demodulation are performed for the channel delivery information.
Based on the above GMSK demodulation and LDPC decoding schemes, it can be known that both GMSK demodulation and LDPC decoding algorithms can perform self-circulation, the GMSK demodulation scheme is to continuously input log-likelihood information output by itself for performing external iteration, the LDPC is to continuously update between check nodes and variable nodes for performing internal iteration, and a calculation value output by the LDPC is also likelihood information. Therefore, in order to enable the GMSK demodulation and LDPC decoding scheme to be combined, as shown in fig. 8, in the embodiment of the present invention, it is preferable that the likelihood information calculated in the LDPC decoding process is input to the GMSK demodulation process as the initial likelihood information of the new external iteration number process in the external iteration process, so as to implement iteration between demodulation and decoding.
Through the implementation mode and the content, the decoding information for setting the internal iteration cycle times is output in the external iteration cycle judgment mode, and the decoding information can be sent to the upper computer of the receiving end equipment 11 through the network port of the receiving end equipment 11 to complete the communication of the whole system.
Based on the same inventive concept of the foregoing technical solution, referring to fig. 9, it is shown that the transmitting end device 11 performs a demodulation and decoding method combining GMSK and LDPC, where the method includes:
s901: after information data sent by an information source is coded according to an LDPC coding algorithm, the coded information data and pilot frequency data are combined into frame data to be sent of a time diversity structure in a mode of pilot frequency data for multiple times and information data for multiple times;
s902: and performing GMSK modulation on the frame data to be transmitted, and transmitting the modulated frame data to be transmitted to a free space, so that the receiving end device performs demodulation and decoding according to the received signal by using the joint GMSK and LDPC demodulation and decoding method shown in fig. 2 to 8.
For the technical solution shown in fig. 9, in some examples, the LDPC code performed by the transmitting end device 11 is a quasi-cyclic LDPC code constructed by a PEF algorithm, that is, the information sequence U of 2160 symbols is multiplied by the generator matrix G, and the dimension of the generator matrix is 2160 × 2880, so as to obtain a codeword sequence C of 2880 symbols, that is, C ═ UG ·.
Then, the coded codeword sequence C and the pilot sequence are framed to obtain frame data with a codeword length of 2976 symbols. The retransmission is performed, the number of times of retransmission is 3, and one frame of data after retransmission is changed to the format of fig. 10, that is, 96 pilot data are transmitted three times first, and then information data are transmitted three times:
for the frame structure of time diversity transmission shown in fig. 10. Preferably, two RAMs are utilized to perform ping-pong operation in the FPGA-based hardware implementation process, for example, 32 × 3 long pilot data are stored in the RAM No. 1, 2880 long information data are stored in the RAM No. 2, the pilot data are firstly read out from the RAM No. 1 (the reading times are three times), and the information data are read out from the RAM at high speed and written into the RAM No. 2; then, reading information data from the RAM No. 2 (the reading times are three times); the two steps are then performed alternately until no data needs to be transmitted.
For GMSK modulation of the coded codeword sequence C, the GMSK modulation is only related to the accumulated phase and the instantaneous phase, and
is limited, the GMSK modulation may be implemented using a table lookup, i.e. a fabrication
(as can be appreciated,
symmetrical to) table for storage. During modulation, the corresponding data output in the address reading storage table is generated according to the current state and the next state transition. Setting the BT value of GMSK modulation to 0.25, the correlation length L is equal to 3, and the number of states is 16, and each state has two transition paths, so there are 32 transition paths in total, i.e. there are 32 state transition data. In modulation, the number of sampling points per symbol interval is set to 100, and therefore, 100 × 32, which is 3200 pieces of data in total, is stored in the ROM. Because of the symmetrical relation between the sine value and the cosine value, only the cosine value needs to be stored, which reduces half of the storage amount and effectively saves hardware resources. In the FPGA implementation, every time a code element is input, the waveform address of the output can be calculated according to the code element sequence, the current state and the state transition, and then 100 data are continuously output, namely the modulation of the current code element is completed.
In order to embody the technical effects of the technical solutions, the embodiments of the present invention are embodied by specific simulation experiments, and the simulation conditions are as follows: the information frame length is 2160, the LDPC coding efficiency is 3/4, and a quasi-cyclic LDPC code constructed by the PEF algorithm is adopted. The coded code length is 2880, 5000 frames of information are transmitted altogether, and the modulation mode is adoptedGMSK is adopted, the number of sampling points is 8, and the simulation result is an error rate performance graph of joint demodulation iteration under the condition of different signal-to-noise ratios, as shown in FIG. 11. In fig. 11, each curve represents different numbers of outer iterations of LOP-MAP and inner iterations of LDPC, and it can be seen from this that, after a plurality of iterations, the technical solution of the embodiment of the present invention can be used in a lower signal-to-noise ratio (for example, E) situation (e.g., Eb/N05dB) to a very low bit error rate (10)-7～10-6)。
Based on the same inventive concept of the foregoing technical solution, referring to fig. 12, the receiving end device 12 according to the embodiment of the present invention in fig. 1 may include: a preprocessing section 121, a difference processing section 122, a diversity combining section 123, a synchronization section 124, and a joint demodulation decoding section 125; wherein the content of the first and second substances,
the preprocessing part 121 is configured to perform low-pass filtering and down-sampling on a baseband digital signal of the received signal to obtain a filtered digital signal; the receiving signal is subjected to LDPC coding by a transmitting terminal, then modulated according to GMSK, and transmitted to a free space in a time diversity mode;
the difference processing part 122 is configured to perform difference processing on the filtered digital signal to obtain a differential digital signal;
the diversity combining part 123 is configured to perform diversity combining on the differentiated digital signals according to pilot data and information data, respectively;
the synchronization part 124 is configured to perform frame synchronization and bit synchronization on the diversity-combined digital signal to obtain a synchronization position;
the joint demodulation and decoding part 125 is configured to perform joint GMSK and LDPC demodulation and decoding on the diversity-combined digital signal in an internal and external iteration manner based on the synchronization position to obtain decoded data.
With regard to the above aspects, in some examples, the difference processing section 122 is configured to: and carrying out conjugate multiplication on the current filtered digital signal and the delay signal of the current filtered digital signal to obtain the differential digital signal.
For the above scheme, in some examples, the diversity combining part 123 is configured to: and respectively carrying out equal gain combination after carrying out time delay on the pilot frequency data and the information data in the digital signals after the difference, and respectively obtaining the combined pilot frequency data and the combined information data.
With respect to the above, in some examples, the synchronization portion 124 is configured to:
matching and filtering the combined pilot frequency data through a matched filter taking waveform data after the difference of the three sections of pilot frequency data as coefficients;
determining a local peak value in the matched and filtered data as a maximum value in correlation values appearing in frame data according to a relative threshold strategy;
and determining the optimal sampling point as the synchronous position according to the maximum value of the frame synchronization and the number of the sampling points.
With respect to the above scheme, in some examples, the joint demodulation and decoding portion 125 is configured to:
performing correlation calculation according to the information data in the digital signal after diversity combination and the path information in different states to obtain initial log-likelihood ratio information of the state from the previous state to the current time; and entering external iteration;
updating the forward and backward path metric information based on the initial log-likelihood ratio information and the MAX-LOP-MAP algorithm in the current external iteration process;
obtaining updated log-likelihood ratio information of the current external iteration process according to the initial log-likelihood ratio information, the forward path metric information and the backward path metric information;
taking the updated log-likelihood ratio information of the current external iteration process as the initialized log-likelihood ratio information for LDPC decoding;
circularly and alternately updating information transmitted to the variable nodes by the check nodes and information transmitted to the check nodes by the variable nodes by utilizing the initialized log-likelihood ratio information for LDPC decoding in an internal iteration mode until a set internal iteration number is reached;
when the set internal iteration times are reached, outputting variable node information obtained by updating in the final internal iteration process;
if the current external iteration times are not the set external iteration times, the variable node information obtained by updating in the final internal iteration process is used as initial log-likelihood ratio information for performing the next external iteration process;
and if the current external iteration number is the set external iteration number, outputting the variable node information obtained by updating in the final internal iteration process as decoded data obtained by demodulating and decoding the GMSK and the LDPC in a combined mode.
Further, referring to fig. 13, the transmitting-end apparatus 11 referred to in the foregoing fig. 1 includes: an encoding section 131, a time diversity combining section 132, a modulation section 133, and a transmission section 134; wherein the content of the first and second substances,
the encoding part 131 is configured to encode the information data sent by the source according to an LDPC encoding algorithm;
the time diversity combining part 132 is configured to combine the encoded information data and the pilot data into the frame data to be transmitted in a time diversity structure according to the multiple times of pilot data and the multiple times of information data;
the modulation section 133 configured to perform GMSK modulation on the frame data to be transmitted;
the transmitting part 134 is configured to transmit the modulated frame data to be transmitted to a free space, so that the receiving end device performs demodulation and decoding according to the received signal by the joint GMSK and LDPC demodulation and decoding method of claims 1 to 5.
It is understood that in this embodiment, "part" may be part of a circuit, part of a processor, part of a program or software, etc., and may also be a unit, and may also be a module or a non-modular.
In addition, each component in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit. The integrated unit can be realized in a form of hardware or a form of a software functional module.
Based on the understanding that the technical solution of the present embodiment essentially or a part contributing to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, and include several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the method of the present embodiment. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
Accordingly, the present embodiment provides a computer storage medium storing a joint GMSK and LDPC demodulation and decoding program, which when executed by at least one processor implements the steps of the joint GMSK and LDPC demodulation and decoding method shown in fig. 2 or 9.
Referring to fig. 14, which shows a specific hardware structure of a communication device 140 capable of implementing the transmitting end device 11 or the receiving end device 12 according to the embodiment of the present invention, the communication device 140 may be a wireless device, a mobile or cellular phone (including a so-called smart phone), a Personal Digital Assistant (PDA), a video game console (including a video display, a mobile video game device, and a mobile video conference unit), a laptop computer, a desktop computer, a television set-top box, a tablet computing device, an e-book reader, a fixed or mobile media player, and the like. The communication device 140 includes: a communication interface 1401, a memory 1402, and a processor 1403; the various components are coupled together by a bus system 1404. It is understood that bus system 1404 is used to enable connective communication between these components. The bus system 1404 includes a power bus, a control bus, and a status signal bus in addition to a data bus. The various buses are labeled as bus system 1404 in fig. 14 for the sake of clarity of illustration. Wherein the content of the first and second substances,
the communication interface 1401 is used for receiving and sending signals in the process of receiving and sending information with other external network elements;
the memory 1402 for storing a computer program capable of running on the processor 1403;
the processor 1403 is configured to, when running the computer program, execute the steps of implementing the demodulation and decoding method of joint GMSK and LDPC shown in fig. 2 or fig. 9.
It will be appreciated that the memory 1402 in embodiments of the invention may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash Memory. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of illustration and not limitation, many forms of RAM are available, such as Static random access memory (Static RAM, SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic random access memory (Synchronous DRAM, SDRAM), Double Data Rate Synchronous Dynamic random access memory (ddr Data Rate SDRAM, ddr SDRAM), Enhanced Synchronous SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The memory 1402 of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.
And processor 1403 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method can be performed by hardware integrated logic circuits or instructions in software form in the processor 1403. The Processor 1403 may be a general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in the memory 1402, and the processor 1403 reads the information in the memory 1402 and completes the steps of the above method in combination with the hardware thereof.
It is to be understood that the embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or any combination thereof. For a hardware implementation, the Processing units may be implemented within one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), general purpose processors, controllers, micro-controllers, microprocessors, other electronic units configured to perform the functions described herein, or a combination thereof.
For a software implementation, the techniques described herein may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. The software codes may be stored in a memory and executed by a processor. The memory may be implemented within the processor or external to the processor.
It can be understood that the above exemplary technical solutions of the transmitting end device 11 or the receiving end device 12 and the communication device 140 belong to the same concept as the above technical solution of the demodulation and decoding method combining GMSK and LDPC, and therefore, details of the above technical solutions of the transmitting end device 11 or the receiving end device 12 and the communication device 140 that are not described in detail can be referred to the above description of the technical solution of the demodulation and decoding method combining GMSK and LDPC. The embodiment of the present invention will not be described in detail.
It should be noted that: the technical schemes described in the embodiments of the present invention can be combined arbitrarily without conflict.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A demodulation and decoding method combining Gaussian Minimum Shift Keying (GMSK) and Low Density Parity Check (LDPC), which is applied to receiving end equipment, and comprises the following steps:
performing low-pass filtering and down-sampling processing on a baseband digital signal of a received signal to obtain a filtered digital signal; the receiving signal is subjected to LDPC coding by a transmitting terminal, then modulated according to GMSK, and transmitted to a free space in a time diversity mode;
carrying out differential processing on the filtered digital signal to obtain a differential digital signal;
diversity combining is carried out on the digital signals after the difference according to pilot frequency data and information data;
carrying out frame synchronization and bit synchronization on the digital signals after diversity combination to obtain a synchronization position;
based on the synchronous position, demodulating and decoding the diversity-combined digital signal by combining GMSK and LDPC in an internal and external iteration mode to obtain decoded data.
2. The method of claim 1, wherein the differentiating the filtered digital signal to obtain a differentiated digital signal comprises:
and carrying out conjugate multiplication on the current filtered digital signal and the delay signal of the current filtered digital signal to obtain the differential digital signal.
3. The method of claim 1, wherein diversity combining the differentiated digital signals according to pilot data and information data, respectively, comprises:
and respectively carrying out equal gain combination after carrying out time delay on the pilot frequency data and the information data in the digital signals after the difference, and respectively obtaining the combined pilot frequency data and the combined information data.
4. The method of claim 3, wherein the performing frame synchronization and bit synchronization on the diversity-combined digital signal to obtain a synchronization position comprises:
matching filtering is carried out on the combined pilot frequency data through a matched filter taking waveform data obtained by differentiating the three sections of pilot frequency data as coefficients;
determining a local peak value in the matched and filtered data as a maximum value in correlation values appearing in frame data according to a relative threshold strategy;
and determining the optimal sampling point as the synchronous position according to the maximum value of the frame synchronization and the number of the sampling points.
5. The method of claim 1, wherein the performing, based on the synchronization position, demodulation and decoding on the diversity-combined digital signal by jointly using GMSK and LDPC in an internal and external iteration manner to obtain decoded data comprises:
performing correlation calculation according to the information data in the digital signal after diversity combination and the path information in different states to obtain initial log-likelihood ratio information of the state from the previous state to the current time; and entering external iteration;
updating the forward and backward path metric information based on the initial log-likelihood ratio information and the MAX-LOP-MAP algorithm in the current external iteration process;
obtaining updated log-likelihood ratio information of the current external iteration process according to the initial log-likelihood ratio information, the forward path metric information and the backward path metric information;
taking the updated log-likelihood ratio information of the current external iteration process as the initialized log-likelihood ratio information for LDPC decoding;
circularly and alternately updating information transmitted to the variable nodes by the check nodes and information transmitted to the check nodes by the variable nodes by utilizing the initialized log-likelihood ratio information for LDPC decoding in an internal iteration mode until a set internal iteration number is reached;
when the set internal iteration times are reached, outputting variable node information obtained by updating in the final internal iteration process;
if the current external iteration times are not the set external iteration times, the variable node information obtained by updating in the final internal iteration process is used as initial log-likelihood ratio information for performing the next external iteration process;
and if the current external iteration number is the set external iteration number, outputting the variable node information obtained by updating in the final internal iteration process as decoded data obtained by demodulating and decoding the GMSK and the LDPC in a combined mode.
6. A demodulation and decoding method combining Gaussian Minimum Shift Keying (GMSK) and Low Density Parity Check (LDPC), which is applied to transmitting end equipment, is characterized by comprising the following steps:
after information data sent by an information source is coded according to an LDPC coding algorithm, the coded information data and pilot frequency data are combined into frame data to be sent of a time diversity structure in a mode of pilot frequency data for multiple times and information data for multiple times;
and performing GMSK modulation on the frame data to be transmitted, and transmitting the modulated frame data to be transmitted to a free space, so that the receiving end device performs demodulation and decoding according to the received signal by using the joint GMSK and LDPC demodulation and decoding method according to claims 1 to 5.
7. A sink device, comprising: a preprocessing part, a differential processing part, a diversity combining part, a synchronizing part and a joint demodulation decoding part; wherein the content of the first and second substances,
the preprocessing part is configured to perform low-pass filtering and down-sampling processing on a baseband digital signal of a received signal to obtain a filtered digital signal; the receiving signal is subjected to LDPC coding by a transmitting terminal, then modulated according to GMSK, and transmitted to a free space in a time diversity mode;
the differential processing part is configured to perform differential processing on the filtered digital signal to obtain a differential digital signal;
the diversity combining part is configured to perform diversity combining on the differentiated digital signals according to pilot frequency data and information data respectively;
the synchronization part is configured to perform frame synchronization and bit synchronization on the diversity-combined digital signal to obtain a synchronization position;
and the joint demodulation and decoding part is configured to demodulate and decode the diversity-combined digital signal by joint GMSK and LDPC in an internal and external iteration mode based on the synchronous position to obtain decoded data.
8. A transmitting-end device, characterized in that the transmitting-end device comprises: a coding part, a time diversity combining part, a modulation part and a transmission part; wherein the content of the first and second substances,
the encoding part is configured to encode information data sent by a source according to an LDPC encoding algorithm;
the time diversity combination part is configured to combine the coded information data and the pilot frequency data into frame data to be sent with a time diversity structure according to a mode of multiple times of pilot frequency data and multiple times of information data;
the modulation part is configured to perform GMSK modulation on the frame data to be transmitted;
the transmitting part is configured to transmit the modulated frame data to be transmitted to a free space, so that the receiving end device performs demodulation and decoding according to the received signal by the joint GMSK and LDPC demodulation and decoding method of claims 1 to 5.
9. A communication device, comprising a communication interface, a memory, and a processor; the various components are coupled together by a bus system; wherein the content of the first and second substances,
the communication interface is used for receiving and sending signals in the process of receiving and sending information with other external network elements;
the memory for storing a computer program operable on the processor;
the processor is configured to execute the steps of the method for joint GMSK and LDPC demodulation and decoding according to any one of claims 1 to 5 or claim 6 when the computer program is executed.
10. A computer storage medium, characterized in that the computer storage medium stores a joint GMSK and LDPC demodulation and decoding program, which when executed by at least one processor implements the joint GMSK and LDPC demodulation and decoding method steps of any one of claims 1 to 5 or claim 6.
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