CN114597159A - Preparation method of semiconductor structure and semiconductor structure - Google Patents

Preparation method of semiconductor structure and semiconductor structure Download PDF

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Publication number
CN114597159A
CN114597159A CN202011412421.7A CN202011412421A CN114597159A CN 114597159 A CN114597159 A CN 114597159A CN 202011412421 A CN202011412421 A CN 202011412421A CN 114597159 A CN114597159 A CN 114597159A
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China
Prior art keywords
semiconductor substrate
bpsg film
protective layer
gap
semiconductor structure
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CN202011412421.7A
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Chinese (zh)
Inventor
金志勋
项金娟
李亭亭
刘青
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Application filed by Institute of Microelectronics of CAS, Zhenxin Beijing Semiconductor Co Ltd filed Critical Institute of Microelectronics of CAS
Priority to CN202011412421.7A priority Critical patent/CN114597159A/en
Publication of CN114597159A publication Critical patent/CN114597159A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention discloses a preparation method of a semiconductor structure and the semiconductor structure, and the method comprises the following steps: providing a semiconductor substrate, wherein a gap exists on the semiconductor substrate; forming a protective layer on the semiconductor substrate; depositing a BPSG film on the protective layer to fill a gap on the semiconductor substrate through the BPSG film; and annealing the semiconductor substrate after gap filling to prepare the semiconductor structure. In the above-described embodiment, the gap on the semiconductor substrate is filled with the BPSG film, and the BPSG film has excellent step coverage, so that a narrow gap can be completely filled and a dense thin film can be formed.

Description

Preparation method of semiconductor structure and semiconductor structure
Technical Field
The present invention relates to the field of semiconductors, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.
Background
In the fabrication of semiconductor devices, it is often necessary to fill gaps formed during the fabrication of semiconductor devices. For example, when a memory is manufactured, gaps may exist between bit lines, and the gaps need to be filled in order to ensure the performance of the device.
In the prior art, the gap is usually filled by using a process such as SOD (Spin On Dielectric) and thermal treatment. However, as the size of the semiconductor device is smaller and smaller, the gap size is narrower and narrower, and the SOD between the gaps is difficult to be dense even after heat treatment, which increases the difficulty in implementing the subsequent process.
Disclosure of Invention
The embodiment of the application provides a preparation method of a semiconductor structure and the semiconductor structure, and solves the technical problem that in the prior art, a gap filling process is difficult and easy to compact.
In a first aspect, embodiments of the present description provide a method for fabricating a semiconductor structure, the method including:
providing a semiconductor substrate, wherein a gap exists on the semiconductor substrate;
forming a protective layer on the semiconductor substrate;
depositing a BPSG film on the protective layer to fill a gap on the semiconductor substrate through the BPSG film;
and annealing the semiconductor substrate after gap filling to prepare the semiconductor structure.
Optionally, after the annealing treatment is performed on the gap-filled semiconductor substrate, the method further includes:
forming an oxide layer on the BPSG film;
and carrying out planarization treatment on the oxide layer.
Optionally, the semiconductor structure is a memory, and the gap on the semiconductor structure is a gap between the bit lines generated when the bit line structure is formed on the semiconductor substrate.
Optionally, the material of the protective layer is Si3N4Forming a protective layer on the semiconductor substrate, comprising:
depositing Si on the semiconductor substrate by low pressure chemical vapor deposition3N4To form the protective layer.
Optionally, the depositing a BPSG film on the protective layer comprises:
according to the preset cycle times, sequentially and circularly depositing SiO on the protective layer2Film, step of depositing BSG film and PSG film to form the BPSG film.
Optionally, the thickness of the BPSG film is 0.5-500 angstroms.
Optionally, the process chamber is at a temperature of 50-300 ℃ and a pressure of 0.1-10 Torr during deposition of the BPSG film.
Optionally, the depositing a BPSG film on the protective layer comprises:
depositing the BPSG film on the protective layer using plasma enhanced atomic layer deposition.
In a second aspect, embodiments of the present description provide a semiconductor structure comprising:
a semiconductor substrate including functional units with a gap therebetween;
a protective layer over the semiconductor substrate;
and a BPSG film for filling the gap on the protective layer.
Optionally, the semiconductor structure further comprises:
an oxide layer over the BPSG film.
Optionally, when the semiconductor structure is the memory, the functional units are bit lines, and the gaps between the functional units are gaps between the bit lines.
According to the technical scheme provided by the embodiment of the application, in the process of preparing the semiconductor structure, a protective layer is formed on a semiconductor substrate with even gaps; depositing a BPSG film on the protective layer, and filling a gap on the semiconductor substrate through the BPSG film; and annealing the semiconductor substrate after gap filling to prepare the semiconductor structure. In the above-described scheme, the gap on the semiconductor substrate is filled with the BPSG film, and the BPSG film has excellent step coverage, so that a narrow gap can be completely filled and a dense thin film can be formed.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic cross-sectional view of a semiconductor substrate provided in an embodiment of the present disclosure;
fig. 2 is a schematic cross-sectional view of a semiconductor substrate with a protective layer formed thereon according to an embodiment of the present disclosure;
FIG. 3 is a schematic cross-sectional view of a semiconductor substrate after deposition of a BPSG film provided in an embodiment of the present description;
fig. 4 is a schematic cross-sectional view of a semiconductor substrate with an oxide layer formed thereon according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a cyclic deposition process for forming a BPSG film according to an embodiment of the present disclosure;
fig. 6 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, as shown in fig. 1 to 4, which is a schematic cross-sectional view of a semiconductor structure in a manufacturing process provided in an embodiment of the present disclosure, the method includes the following steps:
providing a semiconductor substrate, wherein a gap exists on the semiconductor substrate;
forming a protective layer on a semiconductor substrate;
depositing a BPSG film on the protective layer to fill the gap on the semiconductor substrate through the BPSG film;
and annealing the semiconductor substrate after gap filling to prepare the semiconductor structure.
In the embodiments of the present disclosure, the semiconductor structure may be configured according to actual needs, such as a memory. During the fabrication of semiconductor structures, gaps exist in the semiconductor substrate of interest. As shown in fig. 1, a semiconductor substrate is provided with a schematic cross-sectional view in which a plurality of functional units are present on the semiconductor substrate with gaps formed therebetween.
In order to fill the gap on the semiconductor substrate, in the embodiment of the present specification, a protective layer is first formed on the semiconductor substrate. The material of the protective layer can be selected according to actual needs, and in one embodiment, the material of the protective layer is Si3N4In practice, a low pressure may be usedChemical Vapor Deposition (LPCVD) for depositing Si on semiconductor substrates3N4To form a protective layer, as shown in fig. 2, a cross-sectional view of the semiconductor substrate on which the protective layer is formed is illustrated.
Further, a BPSG (Boro-phosphate Glass) film is deposited over the protective layer, the gap is filled, and then an annealing process is performed. Since the BPSG film has excellent step coverage, reflow can be caused under high temperature treatment, and the gap can be further reflowed and filled by annealing treatment, ensuring complete filling of the gap without leaving voids. Fig. 3 is a schematic cross-sectional view of a semiconductor substrate after deposition of a BPSG film. Through the steps, the gap can be filled.
In the embodiment of the present specification, when gap filling is performed using a BPSG film, a seam (seam) may occur on a surface, and since BPSG is a thermal treatment process and has fluidity, a seam generated when BPSG is deposited may be removed by the thermal treatment process. Planarization by thermal treatment requires sufficient deposition of a thicker BPSG film. Given the slow rate of deposition of BPSG, it can result in slow production efficiency if planarization is performed with thicker BPSG films deposited. Therefore, the method in the embodiments of the present specification, after depositing BPSG and performing the annealing process, may further include the steps of: forming an oxide layer on the BPSG film; and carrying out planarization treatment on the oxide layer.
In the specific implementation process, the oxide can be specifically SiO2The planarization treatment may be performed by a CMP (Chemical Mechanical Polishing) process. Due to the addition of the oxide layer, the surface can be flattened by polishing and grinding the oxide layer. Therefore, it is not necessary to remove surface irregularities by depositing a thicker BPSG film, thereby improving the efficiency of semiconductor fabrication. Fig. 4 is a schematic cross-sectional view of a semiconductor substrate with an oxide layer formed thereon.
Further, the BPSG film may be deposited by various means, for example, by Chemical Vapor deposition (Chemical Vapor deposition)Deposition, CVD), atomic layer Deposition, plasma enhanced atomic layer Deposition, and the like. For example, in depositing a BPSG film by CVD, a corresponding boron-containing precursor and a phosphorus-containing precursor are once mixed and deposited to form the BPSG film. In the embodiment of the present disclosure, the BPSG film is deposited on the protective layer by plasma enhanced atomic layer deposition, and specifically, the BPSG film may be generated by the following cyclic deposition method: according to the preset cycle times, sequentially and circularly depositing SiO on the protective layer2Film, step of depositing BSG film and PSG film to form BPSG film.
As shown in fig. 5, a schematic diagram of the formation of BPSG film by cyclic deposition is shown. Placing a semiconductor substrate in a process chamber to deposit a BPSG film, wherein the specific process comprises the following steps: first, SiO is formed2Film, SiO2The film may be formed by reacting a silicon-containing precursor, which may be SiH, on a semiconductor substrate4Or other silicon-containing substances; then, in SiO2BSG films are formed on films by a boron-containing precursor, which may be B2H6Or other boron-containing species; further, a PSG film is formed on the BSG film by a phosphorous-containing precursor, which may be at pH3Or other phosphorus-containing species. The above steps are repeatedly performed according to a preset number of cycles to generate a final BPSG film, wherein the preset number of cycles may be specifically set according to the thickness of the generated BPSG film, for example, the preset number of cycles is 5 times, 10 times, and the like, and is not limited herein.
The thickness of each film may be the same or different for each film, and may be set according to the actual situation. On deposition of SiO2When the film, the BSG film and the PSG film are formed, oxygen can be introduced into the process chamber and is used for reacting with each precursor to generate each film, and before the reaction of different types of films is carried out, argon or other inert gases can be introduced into the process chamber to clean the reaction chamber and avoid the interference of impurity gases on the reaction.
In the embodiment of the present disclosure, the temperature of the process chamber is 50 to 300 ℃ during deposition of the BPSG film, for example, the temperature of the process chamber is specifically 100 ℃, 150 ℃, and the like. The pressure of the process chamber is 0.1-10 Torr, for example, the pressure of the process chamber is specifically 5Torr, 8Torr, etc. The thickness of the BPSG film is 0.5-500 angstroms, for example, the thickness of the BPSG film is 1 angstrom, 15 angstrom, 350 angstrom, etc.
When the annealing treatment is performed, the annealing method may be selected according to actual needs, for example, microwave annealing, furnace annealing, or the like.
Further, in the case where the semiconductor structure is a memory, that is, in the process of manufacturing a memory, the gap on the semiconductor structure is a gap between bit lines generated when the bit line structure is formed on the semiconductor substrate. By adopting the method provided by the embodiment of the specification, the gap between the bit lines can be filled, so that the performance of the memory is ensured.
In a second aspect, an embodiment of the present specification provides a semiconductor structure, as shown in fig. 6, which is a schematic diagram of the semiconductor structure provided in the embodiment of the present specification, and includes:
a semiconductor substrate 11 including functional units with a gap therebetween; a protective layer 12 located over the semiconductor substrate 11; a BPSG film 13 for filling the gap is located on the protective layer 12.
Wherein the material of the protective layer 12 may be Si3N4The film can be formed by deposition on the semiconductor substrate 11 by a low pressure chemical vapor deposition method. The BPSG film 13 may be deposited by a plasma enhanced atomic layer deposition method, and specifically, the deposition of SiO may be sequentially performed on the protection layer 12 in a cycle manner according to a preset cycle number2Film, step of depositing BSG film and PSG film to form BPSG film 13.
Optionally, the semiconductor structure further comprises: and an oxide layer 14 over the BPSG film 13. In a specific implementation, the oxide layer 14 may be SiO2The oxide layer 14 is beneficial to achieving the planarization of the CMP process, and the low production efficiency caused by the fact that a large amount of thicker BPSG films are deposited for planarization is avoided.
Alternatively, when the semiconductor structure is a memory, the functional units are bit lines, and the gaps between the functional units are gaps between the bit lines.
With regard to the above semiconductor structure, detailed description has been made in the embodiments of the method for manufacturing a semiconductor structure provided in the embodiments of the present specification, and detailed description will not be made here.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (11)

1. A method of fabricating a semiconductor structure, the method comprising:
providing a semiconductor substrate, wherein a gap exists on the semiconductor substrate;
forming a protective layer on the semiconductor substrate;
depositing a BPSG film on the protective layer to fill a gap on the semiconductor substrate through the BPSG film;
and annealing the semiconductor substrate after gap filling to prepare the semiconductor structure.
2. The method of claim 1, wherein after the annealing the gap-filled semiconductor substrate, the method further comprises:
forming an oxide layer on the BPSG film;
and carrying out planarization treatment on the oxide layer.
3. The method of claim 1, wherein the semiconductor structure is a memory, and wherein the gap on the semiconductor structure is a gap between the bit lines generated when forming a bit line structure on the semiconductor substrate.
4. The method of claim 1, wherein the material of the protective layer is Si3N4Forming a protective layer on the semiconductor substrate, comprising:
depositing Si on the semiconductor substrate by low pressure chemical vapor deposition3N4To form the protective layer.
5. The method of claim 1, wherein depositing a BPSG film on the protective layer comprises:
according to the preset cycle times, sequentially and circularly depositing SiO on the protective layer2Film, step of depositing BSG film and PSG film to form the BPSG film.
6. The method of claim 1, wherein the BPSG film has a thickness of 0.5-500 angstroms.
7. The method of claim 1, wherein the temperature of the process chamber is 50-300 ℃ and the pressure is 0.1-10 Torr in depositing the BPSG film.
8. The method of claim 2, wherein depositing the BPSG film on the protective layer comprises:
depositing the BPSG film on the protective layer using plasma enhanced atomic layer deposition.
9. A semiconductor structure, comprising:
a semiconductor substrate including functional units with a gap therebetween;
a protective layer over the semiconductor substrate;
and a BPSG film for filling the gap, which is located on the protective layer.
10. The semiconductor structure of claim 9, further comprising:
an oxide layer over the BPSG film.
11. The semiconductor structure of claim 9, wherein when the semiconductor structure is a memory, the functional units are bit lines, and the gaps between the functional units are gaps between the bit lines.
CN202011412421.7A 2020-12-04 2020-12-04 Preparation method of semiconductor structure and semiconductor structure Pending CN114597159A (en)

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Application Number Priority Date Filing Date Title
CN202011412421.7A CN114597159A (en) 2020-12-04 2020-12-04 Preparation method of semiconductor structure and semiconductor structure

Publications (1)

Publication Number Publication Date
CN114597159A true CN114597159A (en) 2022-06-07

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