CN114686851A - Plasma enhanced atomic layer deposition method and surface film forming method of groove/hole - Google Patents
Plasma enhanced atomic layer deposition method and surface film forming method of groove/hole Download PDFInfo
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- CN114686851A CN114686851A CN202011566706.6A CN202011566706A CN114686851A CN 114686851 A CN114686851 A CN 114686851A CN 202011566706 A CN202011566706 A CN 202011566706A CN 114686851 A CN114686851 A CN 114686851A
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- 238000000231 atomic layer deposition Methods 0.000 title claims abstract description 16
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
- C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/04—Coating on selected surface areas, e.g. using masks
- C23C16/042—Coating on selected surface areas, e.g. using masks using masks
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/34—Nitrides
- C23C16/345—Silicon nitride
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/401—Oxides containing silicon
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/4401—Means for minimising impurities, e.g. dust, moisture or residual gas, in the reaction chamber
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/52—Controlling or regulating the coating process
Abstract
The invention relates to an improved plasma enhanced atomic layer deposition method and a surface film forming method of a groove/hole. An improved plasma enhanced atomic layer deposition process comprising: at least one vacuum purge is performed after the precursor pulse is turned off or the reactant pulse is turned off during a deposition cycle. A method for forming a film on a surface of a trench/hole includes: providing a semiconductor substrate, wherein a groove or a hole is formed on the semiconductor substrate; and depositing an insulating film in the groove or the hole by adopting the plasma enhanced atomic layer deposition method. The invention can deposit films with better uniformity and less impurity content, and is especially suitable for depositing in deep grooves or holes with high aspect ratio, such as insulating films in DRAM, FLASH and logic devices.
Description
Technical Field
The invention relates to the field of semiconductor production processes, in particular to an improved plasma enhanced atomic layer deposition method and a groove/hole surface film forming method.
Background
With the high integration of semiconductor devices, there is a need for a 2D level of size reduction and high integration of 3D structures. Especially 3D level semiconductor device architectures, require high aspect ratio, thin and uniform films, which are common in DRAM, FLASH and logic device products. Among these devices, an insulating film is often required to be deposited in a deep trench or a hole with a high aspect ratio, and the film deposited by a conventional method (Thermal ALD, PEALD), which is generally shown in fig. 1, has a large thickness at the top and side walls of the trench, and a small thickness at the bottom and corners of the trench, and thus is prone to cause device defects.
Therefore, the invention is especially provided.
Disclosure of Invention
The main object of the present invention is to provide an improved plasma enhanced atomic layer deposition method which can deposit a thin film with better uniformity and less impurity content, especially suitable for deep trench or high aspect ratio hole deposition, such as insulating film, electrolyte film or dielectric film in DRAM, FLASH and logic devices.
In order to achieve the above object, the present invention provides the following technical solutions.
An improved plasma enhanced atomic layer deposition process comprising:
at least one vacuum purge is performed after the precursor pulse is off or the reactant pulse is off during a deposition cycle.
The invention changes the traditional mode of continuously supplying carrier gas flow into a mode of increasing vacuum purging for part of time, and performs vacuum purging at least once after the pulse closing of the precursor or the reactant is closed, thus effectively removing reaction byproducts, redundant precursors or reactants in the deep groove or the hole, ensuring the same amount of the precursors or reactants adsorbed on the surfaces of the deep groove or the hole and further ensuring the uniform thickness of the formed film.
The method is mainly used for structures requiring extremely thin film thickness, such as insulating films in DRAM, FLASH and logic devices, and has remarkable advantages especially for narrow trenches or holes.
A method for forming a film on a surface of a trench/hole, comprising:
providing a semiconductor substrate, wherein a groove or a hole is formed on the semiconductor substrate;
and depositing an insulating film in the groove or the hole by adopting the plasma enhanced atomic layer deposition method.
Compared with the prior art, the invention achieves the following technical effects:
(1) the uniformity of a deposited film in the deep groove or the hole with high depth-to-width ratio is improved;
(2) the content of impurities such as reaction by-products and the like in the deposited film is reduced;
(3) the semiconductor device characteristics are improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
FIG. 1 is a prior art film profile deposited in a deep trench;
FIG. 2 illustrates a conventional PEALD process;
FIG. 3 is a modified PEALD process provided by the present invention;
figure 4 is a profile of a film deposited in a deep trench according to the present invention.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions, layers and their relative sizes, positional relationships are shown in the drawings as examples only, and in practice deviations due to manufacturing tolerances or technical limitations are possible, and a person skilled in the art may additionally design regions/layers with different shapes, sizes, relative positions according to the actual needs.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
The PEALD method is an effective means for preparing high-quality ultra-thin films at low temperature, and comprises the steps of alternately introducing gas-phase precursor pulses into a reaction chamber, and carrying out surface chemisorption reaction on a deposition substrate to form the thin films layer by layer. The chemical adsorption of the precursor on the surface has the characteristics of self-limitation and self-saturation, so that the thickness of the film can be controlled through the cycle number. Conventional PEALD gas flow delivery is illustrated in fig. 2, and requires a carrier gas flow (usually with inert gases such as He, Ne, Ar) all the way through the deposition cycle to carry away excess precursor and byproducts adsorbed on the reaction surface. The supply mode of the material pulse in a unit cycle is shown in figure 2, a precursor pulse is firstly introduced, then the carrier gas flow is flushed, then the reactant pulse is supplied, the pulse and the plasma are accompanied, the reactant is converted into the plasma under the action of the plasma equipment, the plasma is adsorbed to the deposition surface, the plasma reacts with the precursor, and finally the carrier gas flow is flushed, so that a deposition cycle is completed.
Although the conventional PEALD process includes an inert gas purge, it still cannot satisfy the requirement of high aspect ratio trench or hole deposition, the problem of non-uniform film thickness and high impurity content is serious, and therefore, the present invention proposes the following improved PEALD method:
performing at least one vacuum purge after the precursor pulse is turned off or the reactant pulse is turned off during a deposition cycle;
alternatively, a vacuum purge is performed both after the precursor pulse is turned off and after the reactant pulse is turned off.
The improved method increases the vacuum purge process compared to conventional PEALD to increase the cleaning effort, including excess reactants, precursors, and byproducts, to improve film thickness uniformity and reduce impurity levels.
Depositing Si in deep trenches3N4Film as an example, silicon source (including but not limited to SiH4、SiH2Cl2、SiHCl3、SiCl4、Si2H6) I.e. precursor, nitrogen N2For the reactants, the PEALD process of the present invention is used for deposition, the process of which is shown in fig. 3:
vacuum purging may be performed to remove impurities prior to deposition.
Deposition begins with the supply of a precursor pulse for a time t1 during which a flow of inert carrier gas, e.g., Ar, He, etc., is passed.
Then vacuum purging is carried out for t 2; the time of the vacuum purge is controlled to be less than the duration of the precursor pulse, i.e., t2 < t1, in order to efficiently control the film thickness.
Then, inert carrier gas flow t3 is introduced, t3 is preferably less than t1, more preferably t1 is t2+ t3, the duration of each precursor pulse is preferably substantially the same as that of the reactant pulse, i.e., t2 is t3, so that the film deposited in the deep trench has a uniform film thickness, as shown in fig. 4.
Then introducing a reactant pulse for a time t 4; and in the step, plasma pulse can be simultaneously introduced to carry out doping modification.
Then vacuum purging is carried out for t 2; then introducing an inert carrier gas flow t 3;
and (4) entering the next deposition cycle, and performing the cycle until the deposition is finished, and finally performing vacuum purging to improve the cleanliness.
In the actual production process, t1, t2, t3 and t4 can be arbitrarily adjusted.
The deposition of a silicon nitride film is exemplified above, but the scope of applicability of the invention is broad, including but not limited to silicon oxide SiO2Aluminum oxide Al2O3Titanium oxide TiO2The insulating films, and the corresponding precursor and reactant types, vary, and the process of the present invention is particularly applicable to oxygen or nitrogen containing reactants.
The deposition method of the insulating film can be used for the deposition of the insulating film in any semiconductor structure, and particularly has outstanding advantages in high-depth-ratio trenches or holes, wherein the trenches include but are not limited to isolation trenches, and the holes include but are not limited to capacitance holes.
Taking the shallow trench isolation in the DRAM as an example, the deposition of the insulating film is performed as follows.
In a first step, shallow trenches are formed in a semiconductor substrate. The semiconductor substrate may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a silicon germanium substrate, a III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by performing Selective Epitaxial Growth (SEG). A silicon nitride layer may be deposited on a semiconductor substrate and then patterned to form a hard mask. The substrate is then etched to form high aspect ratio trenches between adjacent devices.
In a second step, a modified PEALD process is used to fill silicon oxide in the trenches to form element isolation structures. Specifically, the substrate is placed in a deposition furnace tube, and the groove is subjected to vacuum sweeping to remove impurities; then supply itPrecursor pulses (including but not limited to SiH)4、SiH2Cl2、SiHCl3、SiCl4、Si2H6) At a supply time t1, during which a flow of inert carrier gas, such as Ar, He, etc., is introduced; then vacuum purging is carried out for t 2; then introducing an inert carrier gas flow for a time period t 3; then a pulse of reactant (oxygen O) is introduced2) Supplying time t4, and introducing plasma pulse at the same time to perform doping modification; then vacuum purging is carried out for t 2; and an inert carrier gas stream t3 is introduced. The above is a complete deposition cycle, the time length relation of the introduction of each gas flow is t 1-t 2+ t3, t 2-t 3, the cycle is carried out until the deposition is finished, and finally, vacuum purging can be carried out to improve the cleanliness. The insulating film deposited in the deep trench according to the above method has a uniform film thickness. Taking the capacitor hole in the DRAM as an example, the deposition of the insulating film is performed as follows.
In a first step, a capacitor hole is formed in a semiconductor substrate. The semiconductor substrate may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a silicon germanium substrate, a III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by performing Selective Epitaxial Growth (SEG). An atomic layer deposition process, a chemical vapor deposition process (CVD, ALD, PEALD, LPCVD, etc.), or the like is used to form stacked dielectric layers on the surface of the substrate. A typical stacked dielectric layer includes a support film and a sacrificial film stacked alternately in sequence, and the number of the support film and the number of the sacrificial film may be set as required. And forming a capacitor hole penetrating through the support film and the sacrificial film to expose the electric contact part, wherein the capacitor hole is formed by mainly performing mask etching, photoetching etching and the like, and the etching selection ratio can be changed by doping in the etching process. The shape of the capacitor hole is arbitrarily selected, and the capacitor hole in a miniaturized DRAM and other devices generally has a large aspect ratio.
And secondly, forming a lower electrode in the capacitor hole. The lower electrode may be formed using a deposition process such as a chemical deposition process (SFD, CVD, ALD, PEALD, etc.), a physical vapor deposition process, or a plasma vapor deposition process. The material of the lower electrode mainly adopts metal nitride (including but not limited to TiN, TaN, TiSiN, WN and the like) which is not easy to oxidize.
And thirdly, depositing silicon oxide on the surface of the lower electrode to be used as an insulating film, and depositing the silicon oxide by adopting the same method as the shallow trench isolation, so that the effect of uniform film thickness can be achieved.
And fourthly, forming an upper electrode, patterning the support film, removing the sacrificial film and the like, and finally forming the capacitor.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (10)
1. An improved plasma enhanced atomic layer deposition process, comprising:
at least one vacuum purge is performed after the precursor pulse is off or the reactant pulse is off during a deposition cycle.
2. The method of claim 1 wherein at least one vacuum purge is performed after the precursor pulse is turned off and at least one vacuum purge is performed after the reactant pulse is turned off during a deposition cycle.
3. The method of claim 1, wherein one deposition cycle comprises: introducing carrier gas flow, introducing precursor pulse, and introducing reactant pulse and plasma pulse;
and in one deposition cycle, when the vacuum purge is not turned on, the carrier gas flow is always turned on.
4. The method of claim 2 wherein the reactant pulse is substantially simultaneous with the plasma pulse during a deposition cycle;
the duration of each vacuum purge is less than the duration of the precursor pulse;
the duration of each of the precursor pulses is substantially the same as the duration of the reactant pulse.
5. The method according to any of claims 1 to 4, wherein the precursor is a precursor of a silicon source and the reactant is a nitrogen and/or oxygen containing element or compound.
6. The method of claim 1, comprising: vacuum purging is also performed before the deposition process begins and after the deposition process ends, respectively.
7. Use of the plasma-enhanced atomic layer deposition method according to any of claims 1 to 6 for depositing an insulating film in a semiconductor structure.
8. A method for forming a film on a surface of a trench/hole, comprising:
providing a semiconductor substrate, wherein a groove or a hole is formed on the semiconductor substrate;
depositing an insulating film in the trench or the hole by using the plasma enhanced atomic layer deposition method according to any one of claims 1 to 6.
9. The surface film forming method according to claim 8, wherein the semiconductor base is a semiconductor substrate with an additional layer, and the groove or the hole is formed in the additional layer.
10. The surface film forming method according to claim 8, wherein the trench is a shallow trench isolation trench, and the hole is a capacitor hole.
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CN105506581A (en) * | 2015-12-15 | 2016-04-20 | 北京七星华创电子股份有限公司 | Realization method for film preparation by applying atomic layer deposition technology |
CN109273402A (en) * | 2018-09-13 | 2019-01-25 | 德淮半导体有限公司 | The production method of metal barrier, metal interconnection structure and preparation method thereof |
CN110724931A (en) * | 2019-11-27 | 2020-01-24 | 上海纳米技术及应用国家工程研究中心有限公司 | Method for preparing rhenium disulfide film by atomic layer deposition |
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CN105506581A (en) * | 2015-12-15 | 2016-04-20 | 北京七星华创电子股份有限公司 | Realization method for film preparation by applying atomic layer deposition technology |
CN109273402A (en) * | 2018-09-13 | 2019-01-25 | 德淮半导体有限公司 | The production method of metal barrier, metal interconnection structure and preparation method thereof |
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