CN114597137A - Bump packaging structure and preparation method thereof - Google Patents

Abstract

The embodiment of the invention provides a bump packaging structure and a preparation method thereof, relating to the technical field of semiconductor packaging. Simultaneously, through setting up first recess for in the electrically conductive combined layer extends to first recess, thereby promoted the cohesion between electrically conductive combined layer and the first buffer layer by a wide margin, and then promoted the cohesion between electrically conductive lug and the chip you, the problem of avoiding appearing electrically conductive lug and dropping has guaranteed the reliability of structure.

Description

Bump packaging structure and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductor packaging, in particular to a bump packaging structure and a preparation method of the bump packaging structure.

Background

With the rapid development of the semiconductor industry, the flip chip package structure is widely applied to the flip chip package in the semiconductor industry, and the bumps are used for electrically connecting the chip and the substrate. The bump comprises a copper column, a metal layer (UBM), a protective layer (Polyimide) and a tin Cap (Sn Cap), and with the reduction of the opening of the protective layer, the opening of the metal layer UBM layer formed on the aluminum pad inside the bump is reduced, so that the bonding force between the side wall of the bump and the metal layer UBM is poor, and the problem that the copper column bump falls off when a bump chip is subjected to a reliability test is solved. That is to say, the metal layer on the surface of the protective layer at the bottom of the metal column has poor bonding force, which easily causes performance problems such as falling of the metal column. In addition, the problem of stress relief at the bottom of the metal bump is difficult to solve during welding, and welding falling is easily caused.

Disclosure of Invention

The invention provides a bump package structure and a method for manufacturing the same, which can improve the bonding force between a metal pillar and a chip, avoid the problems of falling of the metal pillar and the like, buffer the welding stress, avoid stress concentration and reduce the probability of welding falling.

Embodiments of the invention may be implemented as follows:

in a first aspect, the present invention provides a bump package structure, including:

a chip having a pad provided on one side thereof;

the first buffer layer is arranged on one side of the chip and at least partially coats the bonding pad;

the first protective layer is arranged on the first buffer layer, a first conductive opening corresponding to the bonding pad is arranged on the first protective layer, and the first conductive opening penetrates through the first protective layer and the first buffer layer and exposes the bonding pad;

a conductive combination layer disposed within the first conductive opening and electrically connected to the pad;

and a conductive bump disposed on the conductive combination layer;

the first buffer layer extends towards the first conductive opening, a first step structure connected with the first protection layer and the bonding pad is formed in the first conductive opening, a first groove is further formed in the first step structure, and the conductive combination layer extends into the first groove.

In an alternative embodiment, the first groove penetrates the first buffer layer, so that the conductive combination layer contacts the pad through the first groove.

In an optional embodiment, the conductive combination layer includes a conductive adhesive layer, a conductive barrier layer and a conductive wetting layer, the conductive adhesive layer is disposed in the first conductive opening and covers the pad, the first buffer layer and the first protection layer at local positions, the conductive adhesive layer extends to the first groove, the conductive barrier layer is disposed on the conductive adhesive layer, the conductive wetting layer is disposed on the conductive barrier layer, and the conductive bump is disposed on the conductive wetting layer.

In an optional embodiment, the conductive combination layer includes a conductive wiring layer, a conductive adhesive layer, a conductive barrier layer and a conductive wetting layer, the conductive wiring layer is disposed in the first conductive opening and partially covers the surface of the first protection layer, the conductive wiring layer extends to the first groove, a second buffer layer at least partially covering the conductive wiring layer is further disposed on the surface of the first protection layer, a second protection layer is further covered on the surface of the second buffer layer, a second conductive opening is disposed on the second protection layer, the second conductive opening penetrates through the second protection layer and the second buffer layer and exposes the conductive wiring layer, the conductive adhesive layer is disposed in the second conductive opening and simultaneously covers the conductive wiring layer, the second buffer layer and a local position of the second protection layer, the conductive barrier layer is disposed on the conductive adhesive layer, the conductive wetting layer is disposed on the conductive barrier layer, and the conductive bump is disposed on the conductive wetting layer.

In an optional embodiment, the second buffer layer extends towards the second conductive opening, and a second step structure connected to the second protective layer and the pad is formed in the second conductive opening, and the second step structure is further provided with a second groove, and the conductive adhesive layer extends to the second groove.

In an optional embodiment, the conductive bump includes a conductive convex pillar, a conductive anti-expansion layer, and a conductive welding cap, the conductive convex pillar is disposed on the conductive combination layer, the conductive welding cap is disposed at an end of the conductive convex pillar away from the chip, and the conductive anti-expansion layer is disposed between the conductive welding cap and the conductive convex pillar for preventing mutual diffusion between the conductive welding cap and the conductive convex pillar.

In an alternative embodiment, the conductive bump further includes a anti-wetting-out layer disposed between the conductive anti-wetting-out layer and the conductive solder cap.

In an alternative embodiment, the first buffer layer has a thermal expansion coefficient smaller than that of the first protective layer.

In an alternative embodiment, the first buffer layer is made of a photosensitive material, and the first protection layer is made of a photoresist material.

In an alternative embodiment, the first buffer layer is made of a conductive metal material, and the first buffer layer is electrically connected to the conductive combination layer and the pad at the same time.

In an alternative embodiment, the edge of the chip is provided with a plating opening, the first buffer layer extends to the plating opening, and the side wall of the first buffer layer is exposed to the plating opening, and the plating opening is used for forming a plating lead.

In an optional embodiment, a third groove is further formed on the first buffer layer, the third groove is spaced apart from the first conductive opening, and the first protection layer extends to the third groove.

In an optional embodiment, an edge of the first buffer layer is spaced from an edge of the chip, and the first protection layer extends to an edge region of the chip, so that a scribe line of the chip is far away from the first buffer layer.

In a second aspect, the present invention provides a method for manufacturing a bump package structure, for manufacturing the bump package structure according to any one of the foregoing embodiments, including:

providing a chip with a bonding pad;

forming a first buffer layer at least partially wrapping the bonding pad on one side of the chip;

arranging a first protective layer on the first buffer layer;

sequentially forming holes in the first protective layer and the first buffer layer by using an exposure and development process to form a first conductive opening, wherein the first conductive opening penetrates through the first protective layer and the first buffer layer and exposes the bonding pad;

forming a conductive combination layer in the first conductive opening;

forming a conductive bump on the conductive combination layer;

the first buffer layer extends towards the first conductive opening, a first step structure connected with the first protection layer and the bonding pad is formed in the first conductive opening, a first groove is further formed in the first step structure, and the conductive combination layer extends to the first groove.

In an alternative embodiment, the step of sequentially opening the openings in the first protective layer and the first buffer layer by using an exposure and development process includes:

exposing the preset hole positions on the protective layer corresponding to the bonding pads for one time by using a photomask;

removing the exposed area by using a developing solution to form a first transition opening with a top opening W2, a bottom opening W1 and a slope S1;

performing secondary exposure on the preset hole positions on the protective layer corresponding to the bonding pads by using a photomask;

removing the exposed area by using a developing solution to form a second transition opening with a top opening W4, a bottom opening W3 and a slope S2;

opening a hole at a preset hole opening position corresponding to the bonding pad on the buffer layer by utilizing a photoetching process;

wherein S2 is more than S1, and W1 is more than W3 is more than W2 is more than W4.

The beneficial effects of the embodiment of the invention include, for example:

the invention provides a bump packaging structure, which is characterized in that a first buffer layer and a first protective layer are sequentially arranged on one side of a chip, a conductive combination layer is arranged in a first conductive opening, and finally, the manufacture of a conductive bump is completed on the conductive combination layer, wherein the first buffer layer extends towards the first conductive opening, a first step structure connected with the first protective layer and a bonding pad is formed in the first conductive opening, a first groove is also formed in the first step structure, and the conductive combination layer extends into the first groove. Through setting up first buffer layer, can cushion the electrically conductive combined layer effectively, can help the release of welding stress on the electrically conductive lug when the welding, avoided stress concentration phenomenon, reduce the welding probability of droing. Simultaneously, through set up first recess on the first step structure that first buffer layer formed for electrically conductive combination layer extends to in the first recess, thereby has promoted the cohesion between electrically conductive combination layer and the first buffer layer by a wide margin, and then has promoted the cohesion between electrically conductive lug and the chip you, avoids appearing the problem that electrically conductive lug dropped, has guaranteed the reliability of structure.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 is a schematic view of a bump package structure according to a first embodiment of the invention;

FIG. 2 is an enlarged partial view of II in FIG. 1;

fig. 3 is a schematic view of a bump package structure according to a second embodiment of the invention;

FIG. 4 is a partially enlarged view of IV in FIG. 3;

FIG. 5 is a partial enlarged view of V in FIG. 3;

fig. 6 is a schematic view of a bump package structure according to a third embodiment of the invention;

fig. 7 is a schematic view of a bump package structure according to a fourth embodiment of the invention;

FIG. 8 is an enlarged partial view of VIII in FIG. 7;

fig. 9 is a schematic diagram of a bump package structure according to a fifth embodiment of the invention;

fig. 10 to 15 are process flow diagrams of a method for manufacturing a bump package structure according to a fifth embodiment of the invention.

Icon: 100-bump package structure; 110-chip; 111-pads; 113-electroplating the opening; 120-a first buffer layer; 121 — a first conductive opening; 123-a first groove; 125-third groove; 130-a first protective layer; 140-a conductive combination layer; 141-a conductive adhesive layer; 143-a conductive barrier layer; 145-an electrically conductive wetting layer; 147-a conductive routing layer; 150-conductive bumps; 151-conductive studs; 153-conductive anti-spreading layer; 155-conductive solder caps; 157-anti-diffusion wetting layer; 160-a second buffer layer; 161-a second conductive opening; 163-second recess; 170-second protective layer.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.

Furthermore, the appearances of the terms "first," "second," and the like, if any, are only used to distinguish one description from another and are not to be construed as indicating or implying relative importance.

As disclosed in the background art, in the prior art, the bottom of the copper pillar bump is poor in combination, and is easy to fall off during reliability test, which affects welding reliability, and meanwhile, during welding, the problem of stress release at the bottom of the copper pillar bump is difficult to solve, which easily causes stress concentration, and further causes welding fall off or failure.

In addition, in the prior art, after the metal layer UBM is manufactured, the excess metal layer needs to be etched and removed, and since the polyimide material of the protective layer is very easy to absorb water, etching solution residues are easily formed on the side wall of the UBM at the bottom of the metal column, so that an over-corrosion undercut opening exists at the bottom of the copper column bump, and the copper column bump falls off during reliability test, and the welding quality is affected.

And, with the reduction of the opening of the protection layer, the opening of the metal layer formed on the aluminum pad inside the protection layer is smaller, which results in poor bonding force between the metal layer and the aluminum pad, and between the metal layer and the side wall of the protection layer. In order to solve the problem, there is a scheme of increasing the roughness of the aluminum pad or the protective layer by plasma bombardment in the prior art, however, the roughness improvement effect is poor. Particularly, when the protective layer is made of silicon nitride or the like, the bonding force between the metal layer and the protective layer is poor, and performance problems such as falling of the metal column are more likely to occur.

In order to solve the above problems, the present invention provides a bump package structure and a method for manufacturing the bump package structure, and it should be noted that, in a non-conflicting manner, features in the embodiments of the present invention may be combined with each other.

First embodiment

Referring to fig. 1 and 2, the present embodiment provides a bump package structure 100, which can improve the bonding force between a metal pillar and a chip 110, avoid the problems of dropping the metal pillar, and meanwhile can buffer the welding stress, avoid stress concentration, and reduce the probability of welding dropping.

The bump package structure 100 provided by this embodiment includes a chip 110, a first buffer layer 120, a first protection layer 130, a conductive combination layer 140 and a conductive bump 150, wherein the chip 110 is provided with a pad 111 on one side, the first buffer layer 120 is disposed on one side of the chip 110 and at least partially covers the pad 111, the first protection layer 130 is disposed on the first buffer layer 120, a first conductive opening 121 corresponding to the pad 111 is disposed on the first protection layer 130, and the first conductive opening 121 penetrates through the first protection layer 130 and the first buffer layer 120 and exposes the pad 111. The conductive combination layer 140 is disposed in the first conductive opening 121 and electrically connected to the pad 111, and the conductive bump 150 is disposed on the conductive combination layer 140 and protrudes from the first protection layer 130. The first buffer layer 120 extends towards the first conductive opening 121, and a first step structure connected to the first protection layer 130 and the bonding pad 111 is formed in the first conductive opening 121, the first step structure is further provided with a first groove 123, and the conductive combination layer 140 extends into the first groove 123.

In this embodiment, during actual manufacturing, the first buffer layer 120 is first formed on the chip 110 by coating, then the first protection layer 130 is formed by coating again, then the groove is formed on the first protection layer 130 at the position corresponding to the pad, and the groove is completed by the secondary exposure process, so that the roughness of the opening on the first protection layer 130 is more uniform, which is beneficial to the combination with the conductive combination layer 140. Then, a trench is formed in the first buffer layer 120, the size of the opening in the first buffer layer 120 is smaller than that of the opening in the first protection layer 130, and after conduction, a first conductive opening 121 is formed, and a first step structure is formed at the same time. When slotting on the first buffer layer 120, a first groove 123 can be formed in the lump, the first groove 123 is located on the formed first step structure, the first groove 123 is arranged on the first step structure formed by the first buffer layer 120, so that the conductive combination layer 140 extends into the first groove 123, the bonding force between the conductive combination layer 140 and the first buffer layer 120 is greatly improved, the bonding force between the conductive bump 150 and the chip 110 is further improved, the problem that the conductive bump 150 drops is avoided, and the reliability of the structure is ensured.

In other preferred embodiments of the present invention, a single exposure process may be used, wherein the materials of the first buffer layer 120 and the first protection layer 130 are limited, for example, the first buffer layer 120 is made of a photosensitive material, and the first protection layer 130 is made of a photoresist material.

It should be noted that the chip 110 in this embodiment may be a silicon wafer with wires, and the front surface of the silicon wafer is provided with pads 111 made of aluminum, and the chip 110 is a conventional chip 110, and the specific structure thereof will not be described in detail here. Here, the thickness of the first buffer layer 120 should be greater than that of the pad 111 so that it can cover the pad 111 when the first buffer layer 120 is formed by coating.

In this embodiment, the thermal expansion coefficient of the first buffer layer 120 is smaller than that of the first protection layer 130. Specifically, by laying the first protection layer 130 after the first buffer layer 120 is disposed, and directly contacting the conductive combination layer 140 with the first buffer layer 120, the first buffer layer 120 can play a certain buffering role during actual welding, and can effectively buffer the conductive combination layer 140, thereby facilitating the release of welding stress on the conductive bump 150 during welding, avoiding the stress concentration phenomenon, and reducing the welding falling probability.

In the present embodiment, the first groove 123 penetrates the first buffer layer 120, so that the conductive combination layer 140 contacts the pad 111 through the first groove 123. Specifically, when the first buffer layer 120 is grooved, the first conductive opening 121 and the first groove 123 may be formed simultaneously, and both the first conductive opening 121 and the first groove 123 penetrate through the first buffer layer 120. It should be noted that, here, the first groove 123 may be opened at a position corresponding to the pad 111, and the first groove 123 penetrates through the pad 111, and the conductive combination layer 140 extends into the first groove 123 and contacts the pad 111, so as to improve the electrical connection characteristic thereof.

The conductive combination layer 140 includes a conductive adhesive layer 141, a conductive barrier layer 143, and a conductive wetting layer 145, the conductive adhesive layer 141 is disposed in the first conductive opening 121 while covering partial positions of the pad 111, the first buffer layer 120, and the first protection layer 130, the conductive adhesive layer 141 extends to the first groove 123, the conductive barrier layer 143 is disposed on the conductive adhesive layer 141, the conductive wetting layer 145 is disposed on the conductive barrier layer 143, and the conductive bump 150 is disposed on the conductive wetting layer 145. Specifically, the conductive adhesive layer 141 may be a titanium layer with a thickness of 4 μm to 6 μm, and the titanium layer has an extremely high metal adhesion property, and may improve the adhesion between adjacent layers, i.e., the adhesion between the conductive barrier layer 143 and the pad 111 and the first protective layer 130. The conductive barrier layer 143 may be made of nickel, vanadium, chromium, etc., and has a thickness of 4 μm to 6 μm, which can function as a conductive barrier to prevent atomic diffusion in adjacent layers. The conductive wetting layer may be a copper layer with a thickness of 2 μm to 4 μm, and can play a role of transitionally wetting the conductive bump 150 on the upper layer, so as to improve the bondability of the bottom of the conductive bump 150.

It should be noted that, when actually preparing the conductive combination layer 140, a layer of photoresist may be first coated on the first protection layer 130, and a groove is formed at a predetermined position to expose the first conductive opening 121, and the conductive adhesion layer 141, the conductive barrier layer 143, and the conductive wetting layer 145 may be sequentially formed by electroplating, and by covering the surrounding area with the photoresist, the excess metal layer is not etched away by using an etching process, thereby avoiding the problems of over-etching and undercut.

In the present embodiment, the conductive bump 150 includes a conductive pillar 151, a conductive anti-expansion layer 153 and a conductive solder cap 155, the conductive pillar 151 is disposed on the conductive combination layer 140, the conductive solder cap 155 is disposed at an end of the conductive pillar 151 away from the chip 110, and the conductive anti-expansion layer 153 is disposed between the conductive solder cap 155 and the conductive pillar 151 for preventing mutual diffusion between the conductive solder cap 155 and the conductive pillar 151. Specifically, the conductive stud 151 is a copper stud, and during the manufacturing process, a copper layer may be electroplated on the conductive wetting layer 145 to form the conductive stud 151, and then an electroplating process is performed to form the conductive anti-spreading layer 153, and finally the conductive solder cap 155 is formed through a ball-planting or printing process. The conductive anti-spreading layer 153 may be an alloy of electroplated nickel and vanadium, and can function as a barrier layer to prevent atomic diffusion between the conductive solder cap 155 and the conductive stud 151 at the top end.

In this embodiment, the conductive bump 150 further includes a anti-wetting-out layer 157, and the anti-wetting-out layer 157 is disposed between the conductive anti-spreading layer 153 and the conductive solder cap 155. Specifically, by providing the anti-wetting layer 157, it is possible to function to promote the bonding force between the conductive anti-wetting layer 153 and the conductive solder cap 155. The anti-wetting layer 157 may also be a titanium layer, and the titanium layer is used to improve the bonding force.

In summary, the present embodiment provides a bump package structure 100, in which a first buffer layer 120 and a first protection layer 130 are sequentially disposed on one side of a chip 110, a conductive combination layer 140 is disposed in a first conductive opening 121, and finally a conductive bump 150 is formed on the conductive combination layer 140, wherein the first buffer layer 120 extends toward the first conductive opening 121, a first step structure connected to the first protection layer 130 and a bonding pad 111 is formed in the first conductive opening 121, a first groove 123 is further disposed on the first step structure, and the conductive combination layer 140 extends into the first groove 123. Through the arrangement of the first buffer layer 120, the conductive combination layer 140 can be effectively buffered, and the release of welding stress on the conductive bump 150 can be facilitated during welding, so that the stress concentration phenomenon is avoided, and the welding falling probability is reduced. Meanwhile, the first groove 123 is formed in the first step structure formed by the first buffer layer 120, so that the conductive combination layer 140 extends into the first groove 123, the bonding force between the conductive combination layer 140 and the first buffer layer 120 is greatly improved, the bonding force between the conductive bump 150 and the chip 110 is further improved, the problem that the conductive bump 150 falls off is avoided, and the reliability of the structure is ensured.

Second embodiment

Referring to fig. 3 to fig. 5, the basic structure and principle of the bump package structure 100 and the resulting technical effects are the same as those of the first embodiment, and for the sake of brief description, reference may be made to corresponding contents in the first embodiment for parts not mentioned in this embodiment.

In this embodiment, the bump package structure 100 includes a chip 110, a first buffer layer 120, a first protection layer 130, a conductive combination layer 140, a conductive bump 150, a second buffer layer 160, and a second protection layer 170, wherein the chip 110 is provided with a pad 111 on one side, the first buffer layer 120 is disposed on one side of the chip 110 and at least partially covers the pad 111, the first protection layer 130 is disposed on the first buffer layer 120, and the first protection layer 130 is provided with a first conductive opening 121 corresponding to the pad 111, and the first conductive opening 121 penetrates through the first protection layer 130 and the first buffer layer 120 and exposes the pad 111. The conductive combination layer 140 is disposed in the first conductive opening 121 and electrically connected to the pad 111, and the conductive bump 150 is disposed on the conductive combination layer 140 and protrudes from the first protection layer 130. The first buffer layer 120 extends towards the first conductive opening 121, and a first step structure connected to the first protection layer 130 and the bonding pad 111 is formed in the first conductive opening 121, the first step structure is further provided with a first groove 123, and the conductive combination layer 140 extends into the first groove 123. The second buffer layer 160 is disposed on the first protective layer 130, and the second protective layer 170 covers the second buffer layer 160.

In the present embodiment, the conductive combination layer 140 includes a conductive wiring layer 147, a conductive adhesive layer 141, a conductive barrier layer 143, and a conductive wetting layer 145, the conductive wiring layer 147 is disposed in the first conductive opening 121 and partially covers the surface of the first protective layer 130, the conductive wiring layer 147 extends to the first groove 123, the surface of the first protective layer 130 is further provided with a second buffer layer 160 at least partially covering the conductive wiring layer 147, the surface of the second buffer layer 160 is further covered with a second protective layer 170, the second protective layer 170 is provided with a second conductive opening 161, the second conductive opening 161 penetrates through the second protective layer 170 and the second buffer layer 160 and exposes the conductive wiring layer 147, the conductive adhesive layer 141 is disposed in the second conductive opening 161 and simultaneously covers the conductive wiring layer 147, the second buffer layer 160, and the second protective layer 170, the conductive barrier layer 143 is disposed on the conductive adhesive layer 141, the conductive wetting layer 145 is disposed on the conductive barrier layer 143, and the conductive bump 150 is disposed on the conductive wetting layer 145.

It should be noted that, in this embodiment, a double-layer buffer layer structure is adopted, so that a better buffering effect can be achieved, and stress balance is ensured. In addition, the conductive wiring layer 147 can implement the wiring operation on the front surface of the chip 110, and the specific wiring process is consistent with the conventional wiring layer, which is not described herein too much.

In this embodiment, the second buffer layer 160 partially extends toward the second conductive opening 161, and a second step structure connected to the second protective layer 170 and the pad 111 is formed in the second conductive opening 161, the second step structure is further provided with a second groove 163, and the conductive adhesive layer 141 extends to the second groove 163. Specifically, the second conductive opening 161 is disposed offset from the first conductive opening 121, and the second step structure is formed in a similar process to the first step structure, which will not be described in detail herein.

In the bump package structure 100 provided in this embodiment, the first buffer layer 120 is provided with the first groove 123, the conductive wiring layer 147 extends into the first groove 123, and the first groove 123 can improve the bonding force between the conductive wiring layer 147 and the underlying structure. And be provided with second recess 163 on second buffer layer 160, electrically conductive adhesive linkage 141 extends into second recess 163, can promote the cohesion of electrically conductive adhesive linkage 141 with the below structure through setting up second recess 163, and then makes whole structure more firm, and intensity is higher. And by arranging two layers of buffer materials, the buffer effect can be further realized.

Third embodiment

Referring to fig. 6, the basic structure and principle of the bump package structure 100 and the technical effects thereof are the same as those of the first embodiment, and for the sake of brief description, reference may be made to the corresponding contents of the first embodiment for the sake of brevity.

In this embodiment, the bump package structure 100 includes a chip 110, a first buffer layer 120, a first protection layer 130, a conductive combination layer 140 and a conductive bump 150, wherein the chip 110 is provided with a pad 111 on one side, the first buffer layer 120 is disposed on one side of the chip 110 and at least partially covers the pad 111, the first protection layer 130 is disposed on the first buffer layer 120, a first conductive opening 121 corresponding to the pad 111 is disposed on the first protection layer 130, and the first conductive opening 121 penetrates through the first protection layer 130 and the first buffer layer 120 and exposes the pad 111. The conductive combination layer 140 is disposed in the first conductive opening 121 and electrically connected to the pad 111, and the conductive bump 150 is disposed on the conductive combination layer 140 and protrudes from the first protection layer 130. The first buffer layer 120 extends towards the first conductive opening 121, and a first step structure connected to the first protection layer 130 and the bonding pad 111 is formed in the first conductive opening 121, the first step structure is further provided with a first groove 123, and the conductive combination layer 140 extends into the first groove 123.

In this embodiment, the thermal expansion coefficient of the first buffer layer 120 is smaller than the thermal expansion coefficient of the first protection layer 130, the edge of the first buffer layer 120 and the edge of the chip 110 are disposed at an interval, and the first protection layer 130 extends to the edge region of the chip 110, so that the scribe line of the chip 110 is far away from the first buffer layer 120. Specifically, the size range of the first buffer layer 120 is smaller than the size range of the front surface of the chip 110 and larger than the size range of the pad 111, so that the first buffer layer 120 is shrunk to the center of the chip 110 while covering the pad 111, and the first protection layer 130 completely covers the whole front surface of the chip 110. By the arrangement mode, the unknown structural strength of the edge of the chip 110 can be effectively improved.

It should be noted that, in this embodiment, when the bump package structure 100 is manufactured, after the conductive solder caps 155 are manufactured, cutting needs to be performed, and the cutting streets may be located on the first protection layer 130 and spaced apart from the first buffer layer 120, so that there is no buffer material around the cutting streets, which is more favorable for cutting and separating the chips 110. The first buffer layer 120 can buffer the cutting stress when the chip 110 is cut and separated, and reduce the corner chipping problem of the cut edge of the chip 110.

In the bump package structure 100 provided in this embodiment, the coverage of the first buffer layer 120 is limited, so that the structural strength of the edge of the chip 110 is ensured, and the cutting street can be away from the first buffer layer 120 to avoid the problem of edge corner chipping during cutting.

Fourth embodiment

Referring to fig. 7 and fig. 8, the present embodiment provides a bump package structure 100, the basic structure and principle and the generated technical effect are the same as those of the first embodiment or the second embodiment, and for the sake of brief description, the corresponding contents in the first embodiment or the second embodiment may be referred to where not mentioned in part in the present embodiment.

The bump package structure 100 in this embodiment includes a chip 110, a first buffer layer 120, a first protection layer 130, a conductive combination layer 140, and a conductive bump 150, where the chip 110 is provided with a pad 111 on one side, the first buffer layer 120 is provided on one side of the chip 110 and at least partially covers the pad 111, the first protection layer 130 is provided on the first buffer layer 120, and a first conductive opening 121 corresponding to the pad 111 is provided on the first protection layer 130, and the first conductive opening 121 penetrates through the first protection layer 130 and the first buffer layer 120 and exposes the pad 111. The conductive combination layer 140 is disposed in the first conductive opening 121 and electrically connected to the pad 111, and the conductive bump 150 is disposed on the conductive combination layer 140 and protrudes from the first protection layer 130. The first buffer layer 120 extends towards the first conductive opening 121, and a first step structure connected to the first protection layer 130 and the bonding pad 111 is formed in the first conductive opening 121, the first step structure is further provided with a first groove 123, and the conductive combination layer 140 extends into the first groove 123. In this embodiment, the edge of the first buffer layer 120 and the edge of the chip 110 are disposed at an interval, and the first protection layer 130 extends to the edge region of the chip 110, so that the scribe line of the chip 110 is far away from the first buffer layer 120.

In this embodiment, the first buffer layer 120 is further formed with a third groove 125, the third groove 125 is spaced apart from the first conductive opening 121, and the first protection layer 130 extends to the third groove 125. Specifically, the third grooves 125 are multiple, each of the third grooves 125 penetrates through the first buffer layer 120, and the first protection layer 130 covers the multiple third grooves 125 and extends into the third grooves 125, so that the bonding force between the first protection layer 130 and the chip 110 can be improved.

It should be noted that in the present embodiment, the third groove 125 is located at a position offset from the conductive bump 150, for example, around the pad 111, and the first protection layer 130 can directly contact with the surface of the chip 110 through the third groove 125, so as to further improve the bonding force therebetween.

Fifth embodiment

Referring to fig. 9, the basic structure and principle of the bump package structure 100 and the technical effects thereof are the same as those of the first embodiment, and for the sake of brief description, reference may be made to the corresponding contents of the first embodiment for the parts not mentioned in this embodiment.

In this embodiment, the bump package structure 100 includes a chip 110, a first buffer layer 120, a first protection layer 130, a conductive combination layer 140 and a conductive bump 150, wherein the chip 110 is provided with a pad 111 on one side, the first buffer layer 120 is disposed on one side of the chip 110 and at least partially covers the pad 111, the first protection layer 130 is disposed on the first buffer layer 120, a first conductive opening 121 corresponding to the pad 111 is disposed on the first protection layer 130, and the first conductive opening 121 penetrates through the first protection layer 130 and the first buffer layer 120 and exposes the pad 111. The conductive combination layer 140 is disposed in the first conductive opening 121 and electrically connected to the pad 111, and the conductive bump 150 is disposed on the conductive combination layer 140 and protrudes from the first protection layer 130. The first buffer layer 120 extends towards the first conductive opening 121, and a first step structure connected to the first protection layer 130 and the bonding pad 111 is formed in the first conductive opening 121, the first step structure is further provided with a first groove 123, and the conductive combination layer 140 extends into the first groove 123.

In this embodiment, the first buffer layer 120 may be made of a conductive metal material, and the first buffer layer 120 is electrically connected to the conductive combination layer 140 and the pad 111 at the same time, and the number of the conductive bumps 150 is plural. For example, the first buffer layer 120 may be made of titanium, tungsten, or the like, which can improve the bonding force between the first buffer layer 120 and the bonding pad 111, and can be used as an electroplating lead.

In the present embodiment, the edge of the chip 110 is provided with a plating opening 113, the first buffer layer 120 extends to the plating opening 113, and the sidewall of the first buffer layer 120 is exposed to the plating opening 113, and the plating opening 113 is used to form a plating lead. Specifically, the plating lead may be formed within the plating opening 113, the conductive combination layer 140 may be conveniently prepared, and an undercut phenomenon may not occur.

In actual manufacturing, the first buffer layer 120 may be coated on the entire surface of the chip 110, and then, when the first protection layer 130 is coated, the edge region of the chip 110 may be exposed, so that the region of the first buffer layer 120 is not completely covered, and when the conductive combination layer 140 is formed after the pad opening, the first buffer layer 120 may be used as a plating lead to connect all the conductive combination layers 140, thereby achieving more uniform plated metal layer.

After the manufacturing process is completed, the edge plating opening portion may be cut by using a cutting process, or the edge plating opening portion may not be cut.

It should be noted that, in the embodiment, the first buffer layer 120 is made of a conductive metal material, so that when the groove is formed in the first protection layer 130, the groove does not need to be formed in the first buffer layer 120 to expose the pad 111.

In the bump package structure 100 provided in this embodiment, the first buffer layer 120 is made of a conductive metal material and is designed in the first protection layer 130, and the plating opening functions as a plating lead, so as to avoid an undercut phenomenon caused by the need of micro-etching to remove the plating lead after the plating lead is disposed on the protection layer in the conventional process.

Sixth embodiment

The present embodiment provides a method for manufacturing a bump package structure 100, which is used to manufacture the bump package structure 100 provided in the first, second, third or fourth embodiments.

The preparation method provided by the embodiment comprises the following steps:

s1: a chip 110 with pads 111 is provided.

Specifically, a chip 110 with a bonding pad is provided, wherein the bonding pad can be an aluminum bonding pad, and the chip 110 can be prepared in advance. Further, the chip 110 may be a silicon wafer having a wiring structure completed.

S2: a first buffer layer 120 at least partially covering the pad 111 is formed at one side of the chip 110.

Specifically, referring to fig. 10, a liquid buffer layer is uniformly coated on the surface of the chip 110 by spin coating using a coater, and then soft-baked to form a film via a hot plate, so as to form the first buffer layer 120.

S3: the first protective layer 130 is disposed on the first buffer layer 120.

Specifically, referring to fig. 11 in combination, after the first buffer layer 120 is formed, the liquid protective layer is uniformly coated on the first buffer layer 120 again by using a spin coating method using a coater, and is soft-baked and shaped again using a hot plate to form the first protective layer 130.

S3: the first protective layer 130 and the first buffer layer 120 are sequentially opened by an exposure and development process to form a first conductive opening 121.

Referring to fig. 12 to 14 in combination, specifically, the first conductive opening 121 penetrates the first protective layer 130 and the first buffer layer 120, and exposes the pad 111. In actual manufacturing, a secondary exposure technique may be adopted, specifically, a mask is used to expose a predetermined opening position on the protective layer corresponding to the pad 111 for one time, and then the exposed area is removed by a developing solution to form a first transition opening with a top opening W2, a bottom opening W1 and a slope S1, as shown in fig. 11. The predetermined opening positions on the protective layer corresponding to the pads 111 are exposed again by the mask, and then the exposed regions are removed by the developer to form second transition openings with top openings W4, bottom openings W3 and slopes S2, as shown in fig. 12. Finally, a photolithography process is used to open a predetermined opening position on the buffer layer corresponding to the pad 111, thereby forming a first conductive opening 121, as shown in fig. 13. Wherein S2 is more than S1, and W1 is more than W3 is more than W2 is more than W4.

It should be noted that, when the first protection layer 130 is grooved, the specific process is as follows: first, the exposure machine is used to expose the position of the predetermined opening of the first passivation layer 130 (Polyimide) by a mask in a Proximity method, then the first passivation layer 120 is removed by a developing method by spraying a developing solution to form a slope, then the Oven (Oven) is used to heat the first passivation layer 130 to a stable state of complete curing, and the plasma photoresist remover (Descum) is used to remove the organic contaminants on the surface of the passivation layer or the residues in the opening, as shown in fig. 11. Then, the exposure machine is passed again, the mask is used to expose the predetermined opening position of the first passivation layer 130 by the function of the exposure machine in a proximity method, then the developing method is used again to remove the exposed area by spraying (Spray) the first buffer layer 120 and form a slope, then the oven is used to heat the first passivation layer 130 to accelerate the curing to a stable state of complete curing, and finally the plasma photoresist remover (Descum) is used to remove the organic contaminants on the surface of the first passivation layer 130 or the residues in the opening. Wherein the first exposure opening forms a W2 top opening and a W1 bottom opening, a slope S1, when the second exposure opening is performed, a W4 top opening and a W3 bottom opening are formed, a slope S2, which forms the opening on the final first protection layer 130 by the second exposure, more precisely controls the sizes of the W4 top opening and the W3 bottom opening of the protection layer opening S2 slope, and the roughness of the inner wall of the opening is more uniform. Compared with the opening formed by the traditional one-time exposure, the exposure light source has diffraction and scattering, so that the slope roughness and the side wall roughness of the opening are poor, the opening size is not uniform, and the like, and the bonding performance of the metal material and the side wall of the protective material in the opening is poor. The secondary exposure process adopted in this embodiment can improve the bonding force between materials of each part in the first conductive opening 121, thereby preventing the delamination problem.

It should be noted that, in this embodiment, the size of the second transition opening is slightly larger than that of the first transition opening, that is, a smaller opening is formed during the first exposure, and a larger opening is formed during the second exposure, so that the roughness in the opening is better through the second exposure process, which is beneficial to the combination of subsequent materials. Meanwhile, during preparation, when a groove is formed in the first protective layer 130, the first buffer layer 120 covers the bonding pad 111, so that the bonding pad 111 can be protected, and the over-etching phenomenon of the bonding pad 111 is avoided.

In other preferred embodiments of the present invention, the roughness in the opening can be more uniform by using materials with different characteristics. Specifically, the first buffer layer 120 and the first protection layer 130 may be made of materials with opposite material characteristics, for example, the first buffer layer 120 is made of a photosensitive material, and the first protection layer 130 is made of a photoresist material. When the first protection layer 130 is subjected to plasma etching, the material on the first protection layer 130 corresponding to the bonding pad 111 can be directly removed, and the first buffer layer 120 leaks out, because the material with the opposite material characteristic is adopted, the first buffer layer 120 cannot be influenced by penetration of light after exposure and development, then the first buffer layer 120 is removed by carrying out exposure and development again, and because the material characteristic is opposite, the first protection layer 130 cannot be influenced by diffraction and scattering of light, and the problem of overlarge opening is avoided. For the specific materials of the first buffer layer 120 and the first protection layer 130, for example, the first protection layer 130 is made of a silicon-containing photoresist, which is spin-coated in a thicker layer of polymer material (often called an Underlayer), and is insensitive to light. After the exposure development, the first buffer layer 120 may be exposed using oxygen plasma etching. Meanwhile, the first buffer layer 120 is made of a material containing an azidoquinone compound, and after being irradiated by light, the material can undergo a photolysis reaction, and changes from oil solubility to water solubility, so that a positive photoresist can be prepared, and the positive photoresist does not shield the place where the exposure and development opening is needed, but shields other places. Finally, the plasma photoresist stripper (Descum) is used again to remove the excess photoresist and leak the first buffer layer 120, thereby avoiding the problem of etching the bonding pad 111 caused by the conventional process.

It should be noted that, when the first buffer layer 120 is grooved, the groove size of the first buffer layer is smaller than that of the first protection layer 130, and the first groove 123 needs to be formed at the same time, so that the first buffer layer 120 extends toward the first conductive opening 121 after molding, and a first step structure connected to the first protection layer 130 and the pad 111 is formed in the first conductive opening 121, and the first groove 123 is formed on the first step structure.

S4: a conductive combination layer 140 is formed within the first conductive opening 121.

Referring to fig. 15 in combination, specifically, after the first conductive opening 121 is formed, a conductive adhesive layer 141, a conductive barrier layer 143, and a conductive wetting layer 145 may be sequentially formed by electroplating in the first conductive opening 121, wherein the conductive adhesive layer 141 may be a titanium layer having a thickness of 4 μm to 6 μm, and the titanium layer has an extremely high metal adhesion property, which may improve the adhesion of adjacent layers, i.e., the adhesion between the conductive barrier layer 143 and the pad 111 and the first protective layer 130. The conductive barrier layer 143 may be made of nickel, vanadium, chromium, etc., and has a thickness of 4 μm to 6 μm, which can function as a conductive barrier to prevent atomic diffusion in adjacent layers. The conductive wetting layer may be a copper layer with a thickness of 2 μm to 4 μm, and can play a role of transitionally wetting the conductive bump 150 on the upper layer, so as to improve the bondability of the bottom of the conductive bump 150.

It should be noted that, when the conductive adhesive layer 141 is formed by electroplating, it extends to the first groove 123, so that the bonding force between the conductive combination layer 140 and the first buffer layer 120 can be improved.

S5: a conductive bump 150 is formed on the conductive combination layer 140.

Referring to fig. 1, after the conductive combination layer 140 is formed, a copper layer may be further electroplated on the conductive wetting layer 145 to form a conductive pillar 151, and then a conductive anti-spreading layer 153 and an anti-spreading wetting layer 157 are sequentially formed on the conductive pillar 151, and finally a conductive solder cap 155 is formed through a ball-bonding or soldering process.

It should be noted that after the conductive stud 151 is formed, an opening may be formed by coating a photoresist and forming a groove, then the conductive anti-diffusion layer 153 and the anti-wetting layer 157 are sequentially formed in the opening, finally, the solder is filled into the opening by using an electroplating process or a printing process again, the filling of the solder material is completed by controlling electroplating parameters or a printing thickness, the excess photoresist is removed by using a plasma resist remover (Descum) again to form a copper pillar with the solder, and after reflow is performed again, the solder forms a conductive solder ball, thereby completing the process.

In the method for manufacturing the bump package structure 100 provided in this embodiment, the first buffer layer 120 and the first protection layer 130 are sequentially disposed on one side of the chip 110, the conductive combination layer 140 is disposed in the first conductive opening 121, and finally the conductive bump 150 is manufactured on the conductive combination layer 140, wherein the first buffer layer 120 extends toward the first conductive opening 121, a first step structure connected to the first protection layer 130 and the pad 111 is formed in the first conductive opening 121, the first step structure is further provided with a first groove 123, and the conductive combination layer 140 extends into the first groove 123. Through the arrangement of the first buffer layer 120, the conductive combination layer 140 can be effectively buffered, and the release of welding stress on the conductive bump 150 can be facilitated during welding, so that the stress concentration phenomenon is avoided, and the welding falling probability is reduced. Meanwhile, the first groove 123 is formed in the first step structure formed by the first buffer layer 120, so that the conductive combination layer 140 extends into the first groove 123, the bonding force between the conductive combination layer 140 and the first buffer layer 120 is greatly improved, the bonding force between the conductive bump 150 and the chip 110 is further improved, the problem that the conductive bump 150 drops is avoided, and the reliability of the structure is ensured. In addition, in the embodiment, the opening is formed on the first protection layer 130 by the second exposure, so that the roughness in the opening is better, which is beneficial to the combination between the conductive combination layer 140 and the first protection layer 130.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (15)

1. A bump package structure, comprising:

a chip having a pad provided on one side thereof;

the first buffer layer is arranged on one side of the chip and at least partially coats the bonding pad;

the first protective layer is arranged on the first buffer layer, a first conductive opening corresponding to the bonding pad is arranged on the first protective layer, and the first conductive opening penetrates through the first protective layer and the first buffer layer and exposes the bonding pad;

a conductive combination layer disposed within the first conductive opening and electrically connected to the pad;

and a conductive bump disposed on the conductive combination layer;

the first buffer layer extends towards the first conductive opening, a first step structure connected with the first protection layer and the bonding pad is formed in the first conductive opening, a first groove is further formed in the first step structure, and the conductive combination layer extends into the first groove.

2. The bump package structure according to claim 1, wherein the first groove penetrates the first buffer layer, so that the conductive combination layer contacts the pad through the first groove.

3. The bump package structure according to claim 2, wherein the conductive combination layer includes a conductive adhesive layer, a conductive barrier layer and a conductive wetting layer, the conductive adhesive layer is disposed in the first conductive opening and covers local positions of the pad, the first buffer layer and the first protection layer, the conductive adhesive layer extends to the first recess, the conductive barrier layer is disposed on the conductive adhesive layer, the conductive wetting layer is disposed on the conductive barrier layer, and the conductive bump is disposed on the conductive wetting layer.

4. The bump package structure according to claim 2, wherein the conductive combination layer includes a conductive wiring layer, a conductive adhesive layer, a conductive blocking layer and a conductive wetting layer, the conductive wiring layer is disposed in the first conductive opening and partially covers the surface of the first protection layer, the conductive wiring layer extends to the first groove, a second buffer layer at least partially covers the conductive wiring layer is further disposed on the surface of the first protection layer, a second protection layer is further covered on the surface of the second buffer layer, a second conductive opening is disposed on the second protection layer, the second conductive opening penetrates through the second protection layer and the second buffer layer and exposes the conductive wiring layer, the conductive adhesive layer is disposed in the second conductive opening and simultaneously covers the conductive wiring layer, the second buffer layer and the second protection layer at a partial position, the conductive barrier layer is disposed on the conductive adhesive layer, the conductive wetting layer is disposed on the conductive barrier layer, and the conductive bump is disposed on the conductive wetting layer.

5. The bump package structure according to claim 4, wherein the second buffer layer partially extends toward the second conductive opening, and a second step structure is formed in the second conductive opening and connected to the second passivation layer and the bonding pad, and a second groove is further formed on the second step structure, and the conductive adhesive layer extends to the second groove.

6. The bump package structure according to claim 1, wherein the conductive bump includes a conductive pillar disposed on the conductive combination layer, a conductive anti-expansion layer disposed at an end of the conductive pillar away from the chip, and a conductive solder cap disposed between the conductive solder cap and the conductive pillar for preventing mutual diffusion between the conductive solder cap and the conductive pillar.

7. The bump package structure of claim 6, wherein the conductive bump further comprises an anti-wetting-out layer disposed between the conductive anti-wetting-out layer and the conductive solder cap.

8. The bump package structure of claim 1, wherein a coefficient of thermal expansion of the first buffer layer is less than a coefficient of thermal expansion of the first protection layer.

9. The bump package structure according to claim 1, wherein the first buffer layer is made of a photosensitive material, and the first protection layer is made of a photoresist material.

10. The bump package structure according to claim 1, wherein the first buffer layer is made of a conductive metal material, and the first buffer layer is electrically connected to the conductive combination layer and the bonding pad at the same time.

11. The bump package structure according to claim 10, wherein an edge of the chip is provided with a plating opening, the first buffer layer extends to the plating opening, and a sidewall of the first buffer layer is exposed to the plating opening, and the plating opening is used for forming a plating lead.

12. The bump package structure of any one of claims 1-8, wherein a third groove is further formed on the first buffer layer, the third groove is spaced apart from the first conductive opening, and the first protection layer extends to the third groove.

13. The bump package structure of any one of claims 1 to 8, wherein an edge of the first buffer layer is spaced apart from an edge of the chip, and the first protection layer extends to an edge region of the chip to separate the scribe line of the chip from the first buffer layer.

14. A method for manufacturing a bump package structure according to any one of claims 1 to 13, comprising:

providing a chip with a bonding pad;

forming a first buffer layer at least partially wrapping the bonding pad on one side of the chip;

arranging a first protective layer on the first buffer layer;

sequentially forming holes in the first protective layer and the first buffer layer by using an exposure and development process to form a first conductive opening, wherein the first conductive opening penetrates through the first protective layer and the first buffer layer and exposes the bonding pad;

forming a conductive combination layer in the first conductive opening;

forming a conductive bump on the conductive combination layer;

the first buffer layer extends towards the first conductive opening, a first step structure connected with the first protection layer and the bonding pad is formed in the first conductive opening, a first groove is further formed in the first step structure, and the conductive combination layer extends to the first groove.

15. The method for manufacturing a bump package structure according to claim 14, wherein the step of sequentially opening the openings on the first protection layer and the first buffer layer by using an exposure and development process includes:

exposing the preset hole positions on the protective layer corresponding to the bonding pads for one time by using a photomask;

removing the exposed region with a developer to form a first transition opening having a top opening width of W2, a bottom opening width of W1, and a slope of S1;

performing secondary exposure on the preset hole positions on the protective layer corresponding to the bonding pads by using a photomask;

removing the exposed area with a developing solution to form a second transition opening with a top opening width of W4, a bottom opening width of W3, and a slope of S2;

opening a hole at a preset opening position on the buffer layer corresponding to the bonding pad by utilizing a photoetching process;

wherein S2 is more than S1, and W1 is more than W3 is more than W2 is more than W4.

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