CN114594820B - Source follower and method for driving source follower - Google Patents
Source follower and method for driving source follower Download PDFInfo
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Abstract
The application provides a source follower and a driving method of the source follower, wherein a signal input end in the source follower is connected with a third grid-source voltage regulating module, a power input end is connected with the third grid-source voltage regulating module and a first constant current module, the third grid-source voltage regulating module is also connected with a first grid-source voltage regulating module and a fourth grid-source voltage regulating module, the first constant current module is also connected with a first grid-source voltage regulating module and a second grid-source voltage regulating module, the first grid-source voltage regulating module is also connected with the fourth grid-source voltage regulating module, the second grid-source voltage regulating module and a second constant current module, the fourth grid-source voltage regulating module, the second constant current module and the second grid-source voltage regulating module are connected with each other and are connected with a power output end, and the first constant current module, the first grid-source voltage regulating module and the second grid-source voltage regulating module are connected with each other and are connected with a signal output end. Thus, the accuracy of signal detection can be improved, and the stability of heavy load can be ensured.
Description
Technical Field
The present disclosure relates to integrated circuit technologies, and in particular, to a source follower and a method for driving the source follower.
Background
A Source Follower (Source Follower) is widely applied to signal detection, driving of a large circuit load, and the like as a circuit structure having high input resistance, low output resistance, and a large swing characteristic.
In practical applications, there are some other source follower configurations besides a source follower consisting of a single transistor and a constant current source. For example: super Source Follower (Super Source Follower), flip Voltage Follower (Flipped Voltage Follower), etc. To reduce the output resistance and supply voltage of the source follower.
However, in some heavy duty designs, for example: since the output current of a Low Dropout Regulator (LDO) can reach several hundred milliamperes or even amperes, the size of a power tube in the LDO needs to be increased in order to drive the LDO. And the too large size of the power tube can push the pole of the output end of the error amplifier in the LDO to a low frequency, so that the stability of the LDO is reduced. Moreover, the large swing of the source follower causes a deviation between the detection value and the actual value during signal detection, thereby reducing the accuracy of signal detection.
Disclosure of Invention
An object of the embodiments of the present application is to provide a source follower and a driving method of the source follower, which further reduce an output resistance of the source follower and make an input voltage of the source follower generate an offset, so as to ensure stability of an LDO and improve detection accuracy of a signal.
In order to solve the above technical problem, an embodiment of the present application provides the following technical solutions:
a first aspect of the present application provides a source follower, the source follower comprising: the grid-source voltage regulation circuit comprises a signal input end, a signal output end, a power input end, a power output end, a first constant current module, a second constant current module, a first grid-source voltage regulation module, a second grid-source voltage regulation module, a third grid-source voltage regulation module and a fourth grid-source voltage regulation module; the signal input end is connected with the third grid-source voltage regulating module; the power supply input end is respectively connected with the third grid-source voltage regulating module and the first constant current module; the third gate-source voltage regulating module is also respectively connected with the first gate-source voltage regulating module and the fourth gate-source voltage regulating module; the first constant current module is also connected with the first grid-source voltage regulating module and the second grid-source voltage regulating module; the first grid-source voltage regulating module is also connected with the fourth grid-source voltage regulating module, the second grid-source voltage regulating module and the second constant current module; the fourth gate-source voltage regulating module and the second constant current module are connected with each other and the second gate-source voltage regulating module is connected with the power output end; the first constant current module, the first grid-source voltage regulating module and the second grid-source voltage regulating module are connected with each other and connected with the signal output end.
A second aspect of the present application provides a driving method of a source follower, which is applied to the source follower in the first aspect; the driving method includes: the signal input end receives an input signal after the negative/positive incremental signal is superposed; the third grid-source voltage regulating module carries out displacement of grid-source voltage on the input signal on which the negative/positive incremental signal is superposed, and reduces/increases the grid-source voltage of the third grid-source voltage regulating module based on the displaced input signal; the first grid-source voltage regulating module increases/decreases the grid-source voltage of the first grid-source voltage regulating module based on the decreased/increased grid-source voltage of the third grid-source voltage regulating module; the fourth gate-source voltage regulating module increases/decreases the gate-source voltage of the fourth gate-source voltage regulating module based on the increased/decreased gate-source voltage of the first gate-source voltage regulating module; the first grid-source voltage regulating module further increases/decreases the grid-source voltage of the first grid-source voltage regulating module based on the increased/decreased grid-source voltage of the fourth grid-source voltage regulating module; the second grid-source voltage regulating module increases/decreases the grid-source voltage of the second grid-source voltage regulating module based on the further increased/decreased grid-source voltage of the first grid-source voltage regulating module, so that the input signal superposed with the negative/positive incremental signal is decreased/increased, and the decreased/increased output signal is obtained; the signal output terminal outputs the decreased/increased output signal.
Compared with the prior art, the source follower provided in the first aspect of the present application adds two gate-source voltage adjusting modules, that is, a third gate-source voltage adjusting module and a fourth gate-source voltage adjusting module, to an existing source follower (that is, a super source follower), so that the third gate-source voltage adjusting module can generate a Vgs offset for an input signal, and further reduce a difference between the input signal and an output signal. And a negative feedback is formed between the fourth gate-source voltage regulating module and the first gate-source voltage regulating module, so that the value of the output signal is further reduced, and the output resistance of the source follower is further reduced. Finally, the pole of the output end of the error amplifier in the heavy load using the source follower can be pushed to a high frequency, the stability of the heavy load is ensured, the difference between a signal detection value and a signal actual value can be reduced in the process of using the source follower to detect signals, and the accuracy of signal detection is improved.
The driving method of the source follower provided by the second aspect of the present application has the same or similar beneficial effects as the source follower provided by the first aspect.
Drawings
The above and other objects, features and advantages of exemplary embodiments of the present application will become readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings. Several embodiments of the present application are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:
fig. 1 is a schematic structural diagram of a conventional source follower;
FIG. 2 is a first schematic diagram illustrating a source follower according to an embodiment of the present disclosure;
FIG. 3 is a second schematic structural diagram of a source follower in the embodiment of the present application;
FIG. 4 is a schematic diagram of an input/output curve of the source follower in FIG. 1;
FIG. 5 is a schematic diagram of an input/output curve of the source follower in FIG. 3;
fig. 6 is a flowchart illustrating a driving method of a source follower according to an embodiment of the present disclosure.
Detailed Description
Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
It is to be noted that, unless otherwise specified, technical or scientific terms used herein shall have the ordinary meaning as understood by those skilled in the art to which this application belongs.
Currently, in order to drive a heavy load, it is necessary to increase the size of a power tube in the heavy load. And the large-size power tube can push the pole of the output end of the error amplifier in the heavy load to the low frequency, so that the stability of the heavy load is reduced. In addition, when the source follower is applied to signal detection, the large swing of the source follower can also reduce the accuracy of signal detection.
The inventor finds that when the heavy load is driven, the key point of ensuring the stability of the heavy load is to push the pole of the output end of the error amplifier in the heavy load to a high frequency, so that the output resistance of the source follower can be further reduced, and the pole of the output end of the error amplifier in the heavy load is pushed to the high frequency by the source follower further reducing the output resistance, so that the stability of the heavy load is ensured. In addition, when a signal in the circuit is detected, the key for ensuring the detection precision lies in adjusting the swing amplitude of the source follower, so that the swing amplitude of the source follower can be adjusted by offsetting the input voltage of the source follower to a certain degree, and the precision of signal detection is improved.
In view of this, embodiments of the present disclosure provide a source follower and a driving method of the source follower, in which two gate-source voltage adjusting modules are added on the basis of an existing source follower, one of the gate-source voltage adjusting modules is used to offset an input voltage of the source follower, and the other gate-source voltage adjusting module is used to form a negative feedback with the gate-source voltage adjusting module in the existing source follower, so as to further reduce an output resistance of the source follower. The source follower which further reduces the output resistance pushes the pole of the output end of the error amplifier in the heavy load to high frequency, and the input voltage of the source follower generates offset, so that the stability of the heavy load and the accuracy of signal detection are ensured.
Fig. 1 is a schematic structural diagram of a conventional source follower, and referring to fig. 1, the source follower at least includes: the power supply comprises a signal input end, a signal output end, a power input end, a power output end, a first current source I1, a second current source I2, a first field effect transistor MP1 and a second field effect transistor MN1.
The signal input end is used for receiving an input signal Vin. The signal output terminal is used for outputting an output signal Vout. Generally, the input signal Vin and the output signal Vout may refer to analog voltage signals. The power input end is connected with a power supply VDD, and the power output end is connected with a ground potential VSS.
In the source follower, the connection relationship of each component may specifically be: the signal input end is connected with the grid electrode of the first field effect transistor MP 1. The power input terminal is connected to a first terminal of a first current source I1. The second end of the first current source I1 is connected to the source of the first fet MP1 and the drain of the second fet MN1, respectively. The drain of the first fet MP1 is connected to the gate of the second fet MN1 and the first terminal of the second current source I2, respectively. The second end of the second current source I2 and the source of the second fet MN1 are connected to each other and to the power output terminal. The second end of the first current source I1, the source of the first field effect transistor MP1 and the drain of the second field effect transistor MN1 are connected to each other and to the signal output terminal.
The output resistance of the more conventional single-tube source follower is not very small compared to the source follower in fig. 1. In the conventional source follower, since the second fet MN1 shown in fig. 1 is not provided, the output resistance is
Where gm is the transconductance of the conventional unipolar input transistor (i.e., the first fet MP1 in fig. 1). Compared with the conventional source follower, the source follower in fig. 1 has the second field effect transistor MN1 added. The output resistance of the second field effect transistor MN1 is reduced to
Wherein gmp1 is transconductance of the first field effect transistor MP1, gmn1 is transconductance of the second field effect transistor MN1, and ro1 is output resistance of the second field effect transistor MN1. It can be seen that the source follower in fig. 1 has been able to reduce its output resistance to some extent.
The following is a detailed description of why the source follower in fig. 1 has a small output resistance.
When the source follower works, the power supply input end is connected with a power supply VDD, and the power supply output end is connected withThe ground potential VSS. The first field effect transistor MP1 and the second field effect transistor MN1 are both in a conducting state, i.e., both operate in a saturation region. After a negative incremental signal Δ V is superimposed on the input signal Vin (i.e., the input signal Vin is decreased) and sent to the signal input terminal, the absolute value of Vgs (which is the voltage of the gate of the fet with respect to the source, and is expressed by Vgs) of the first fet MP1 increases (since the actual value of Vgs of the first fet MP1 is a p-type fet, which is generally a negative value, and the input signal Vin decreases, the actual value of Vgs of the first fet MP1 is smaller, so the absolute value thereof increases), and the leakage current Imp1 flowing through the first fet MP1 increases. Due to the negative feedback effect of the second field effect transistor MN1, the current of the node a is increased, which further causes the voltage of the node a to increase, and further increases the absolute value of Vgs of the second field effect transistor MN1 (since the second field effect transistor MN1 is generally an n-type field effect transistor, the actual value of Vgs is a positive value, and the voltage of the node a increases, the actual value of Vgs of the second field effect transistor MN1 is larger, so the absolute value thereof increases), and further increases the leakage current Imn1 flowing through the second field effect transistor MN1, and finally rapidly decreases the output signal Vout (the first current source I1 is unchanged, the leakage current Imn1 of the second field effect transistor MN1 is increased, for the signal output end, the input charge amount is unchanged, the output charge amount is increased, and the charge amount is decreased as a whole, so the voltage thereof decreases). And the second current source I2 plays a role in stabilizing the current in the circuit as a whole. Therefore, the output resistance of the source follower is lowered as viewed from the direction of the signal output terminal toward the inside of the source follower
Output resistance compared to conventional source follower
The output resistance of the source follower in fig. 1 is reduced to some extent.
Although the output resistance of the source follower in fig. 1 is reduced to some extent, the reduction of the output resistance still cannot ensure that the pole of the output end of the error amplifier in the heavy load can be pushed to a high frequency, and thus the stability of the heavy load cannot be ensured. And the input voltage cannot be shifted, and the detection accuracy of the signal cannot be ensured. Therefore, it is also necessary to further reduce the output resistance of the source follower in fig. 1 and to offset the input voltage of the source follower in fig. 1.
Next, on the basis of fig. 1, a detailed description is given of a source follower provided in an embodiment of the present application.
Fig. 2 is a schematic structural diagram of a source follower in an embodiment of the present application, and referring to fig. 2, the source follower at least includes: the grid-source voltage regulation circuit comprises a signal input end, a signal output end, a power input end, a power output end, a first constant current module, a second constant current module, a first grid-source voltage regulation module, a second grid-source voltage regulation module, a third grid-source voltage regulation module and a fourth grid-source voltage regulation module.
The signal input end is used for receiving an input signal Vin. The signal output terminal is used for outputting an output signal Vout. Generally, the input signal Vin and the output signal Vout may refer to analog voltage signals. The power input end is connected with a power supply VDD, and the power output end is connected with a ground potential VSS.
In the source follower, the connection relationship of each component may specifically be: the signal input end is connected with the third grid-source voltage regulating module. The power supply input end is respectively connected with the third grid-source voltage regulating module and the first constant current module. The third grid-source voltage regulating module is also respectively connected with the first grid-source voltage regulating module and the fourth grid-source voltage regulating module. The first constant current module is also connected with the first grid-source voltage regulating module and the second grid-source voltage regulating module. The first grid-source voltage regulating module is also connected with the fourth grid-source voltage regulating module, the second grid-source voltage regulating module and the second constant current module. The fourth grid-source voltage regulating module and the second constant current module are connected with each other and connected with the power output end. The first constant current module, the first grid-source voltage regulating module and the second grid-source voltage regulating module are mutually connected and connected with the signal output end.
When the source follower works, the power supply input end is connected with a power supply VDD, and the power supply output end is connected with a ground potential VSS. The first grid-source voltage regulating module, the second grid-source voltage regulating module, the third grid-source voltage regulating module and the fourth grid-source voltage regulating module are all in working states. When the input signal is Vin, the voltage at the point B is Vin-Vgsmn2, and Vgsmn2 is Vgs of the third gate-source voltage regulating module. Then, the output signal output by the first gate-source voltage regulating module is Vout = Vin-Vgsmn2+ Vgsmp1, and Vgsmp1 is Vgs of the first gate-source voltage regulating module. After the output signal Vout = Vin-Vgsmn2+ Vgsmp1 is obtained, vout is equal to Vin if Vgsmn2 is substantially equal to Vgsmp 1. It can be seen that the third gate-source voltage regulating module added in the source follower shifts the input voltage Vin by a Vgs voltage.
Therefore, a gate-source voltage adjusting module, namely a third gate-source voltage adjusting module, is added behind a signal input end of the source follower, so that Vgs offset can be carried out on input voltage input into the source follower, and then difference between the input voltage and output voltage in the source follower is reduced, so that the amplitude of oscillation of the source follower is reduced.
The third gate-source voltage regulating module can not only shift the input signal Vin by one Vgs, but also ensure that the source follower has low output resistance. Next, a specific operation principle thereof will be explained.
When the source follower works, after a negative incremental signal Δ V is superimposed on the input signal Vin (that is, the input signal Vin is reduced) and is sent to the signal input end, the absolute value of Vgs of the third gate-source voltage regulating module is reduced (since the third gate-source voltage regulating module is generally an n-type gate-source voltage regulating module, the actual value of Vgs is a positive value, the input signal Vin is reduced, the actual value of Vgs of the third gate-source voltage regulating module is reduced, and thus the absolute value of Vgs is also reduced), and further, the leakage current Imn2 flowing through the third gate-source voltage regulating module is also reduced. Since the leakage current Imn2 of the third gate-source voltage regulating module is smaller than the leakage current Imn3 of the fourth gate-source voltage regulating module after being reduced, the voltage of the node B is reduced (the input current is reduced, which is equivalent to the input charge amount is reduced, while the output current and the charge amount are unchanged, and the charge amount of the node B is reduced as a whole, so the voltage of the node B is reduced), and further, the absolute value of Vgs of the first gate-source voltage regulating module is increased (the first gate-source voltage regulating module is generally a p-type gate-source voltage regulating module, the actual value of Vgs of the first gate-source voltage regulating module is a negative value, the voltage of the node B is reduced, the actual value of Vgs of the first gate-source voltage regulating module is smaller, and further, the absolute value of the Vgs of the first gate-source voltage regulating module is larger), and further, the leakage current Imp1 of the first gate-source voltage regulating module is increased. Due to the negative feedback effect of the second gate-source voltage regulating module, the current of the node a is increased, so that the voltage of the node a is increased, and further, the absolute value of Vgs of the second gate-source voltage regulating module is increased (since the second gate-source voltage regulating module is generally an n-type gate-source voltage regulating module, the actual value of Vgs is a positive value, and the voltage of the node a is increased, the actual value of Vgs of the second gate-source voltage regulating module is larger, so that the absolute value of Vgs is increased), so that the leakage current Imn1 flowing through the second gate-source voltage regulating module is also increased, and finally, the output signal Vout is rapidly decreased (the first constant current module is unchanged, the leakage current Imn1 of the second gate-source voltage regulating module is increased, for the signal output end, the input charge amount is unchanged, the output charge amount is increased, and the voltage of the output end is decreased as seen as a whole). And the second constant current module plays a role in stabilizing the current in the circuit in the whole circuit. Therefore, the output resistance of the source follower is reduced due to the third gate-source voltage regulating module when the source follower looks inside from the direction of the signal output end.
Therefore, after the third grid-source voltage regulating module is added in the source follower, the output signal Vout can be reduced, the output resistance of the source follower is reduced, and the heavy load can be driven stably on the basis that the size of a power tube of the source follower is not increased.
When the third grid-source voltage adjusting module is added, a grid-source voltage adjusting module, namely the fourth grid-source voltage adjusting module, can be added, and then a negative feedback is formed with the first grid-source voltage adjusting module, so that the output resistance of the source follower is further reduced. The operation principle thereof will be explained in detail below.
When the source follower works, after a negative incremental signal delta V is superposed on an input signal Vin and sent to a signal input end, the absolute value of Vgs of the third gate-source voltage regulating module is reduced, and further, the leakage current Imn2 flowing through the third gate-source voltage regulating module is also reduced. Since the leakage current Imn2 of the third gate-source voltage regulating module is smaller than the leakage current Imn3 of the fourth gate-source voltage regulating module after being reduced, the voltage of the node B is reduced, so that the absolute value of Vgs of the first gate-source voltage regulating module is increased, and further the leakage current Imp1 of the first gate-source voltage regulating module is increased. Due to the negative feedback action of the fourth gate-source voltage regulating module, when the leakage current Imp1 of the first gate-source voltage regulating module increases, the voltage of the node a increases in view of the fact that the current of the second constant current module does not change (the input current increases, equivalent to the input charge amount increases, while the output current and the charge amount do not change, the charge amount at the node a increases as a whole, and thus the voltage of the node a increases). The voltage of the node A rises, so that the value of Vgs of the fourth gate-source voltage regulating module is increased, and further, the leakage current Imn3 of the fourth gate-source voltage regulating module is increased. Since the leakage current Imn2 flowing through the third gate-source voltage regulating block decreases and the leakage current Imn3 flowing through the fourth gate-source voltage regulating block increases, that is, the input charge amount decreases and the output charge amount increases, the charge amount of the node B as a whole decreases, and thus the voltage of the node B further decreases. Further reduction of the voltage of the node B further increases the absolute value of Vgs of the first gate-source voltage regulator module, further increases the leakage current Imp1 of the first gate-source voltage regulator module, and finally further reduces the output signal Vout (the change of parameters of each component in a loop formed by the first gate-source voltage regulator module, the node a, the second gate-source voltage regulator module, and the signal output end is consistent with the foregoing description, and is not described herein again), and the output resistance of the source follower is further reduced when the source follower is seen from the direction of the signal output end.
Therefore, the fourth gate-source voltage regulating module is added in the source follower, the output signal Vout can be further reduced through the working mechanism, and then the output signal Vout is seen from the direction of the signal output end to the inside of the source follower, so that the output resistance of the source follower is further reduced, the pole of the output end of the error amplifier in the heavy load can be further pushed to the high frequency, and the stability of the heavy load can be further ensured.
As can be seen from the above, in the source follower provided in the embodiment of the present application, two gate-source voltage adjusting modules, that is, a third gate-source voltage adjusting module and a fourth gate-source voltage adjusting module, are added in an existing source follower (that is, a super source follower), so that the third gate-source voltage adjusting module can generate a Vgs offset for an input signal, and further, a difference between the input signal and an output signal is reduced. And a negative feedback is formed between the fourth grid-source voltage regulating module and the first grid-source voltage regulating module, so that the value of the output signal is further reduced, and the output resistance of the source follower is further reduced. Finally, the pole of the output end of the error amplifier in the heavy load using the source follower can be pushed to high frequency, the stability of the heavy load is ensured, the difference between a signal detection value and a signal actual value can be reduced in the process of using the source follower to detect signals, and the accuracy of signal detection is improved.
In practical applications, the first gate-source voltage regulating module may be a first field effect transistor. The second gate-source voltage regulating module may be a second field effect transistor. The third gate-source voltage regulating module may be a third field effect transistor. The fourth gate-source voltage regulating module may be a fourth field effect transistor. The first constant current module may be a first current source, and the second constant current module may be a second current source.
For the first field effect transistor, the grid electrode of the first field effect transistor is respectively connected with the third grid-source voltage regulating module and the fourth grid-source voltage regulating module, the source electrode of the first field effect transistor is respectively connected with the first constant current module, the second grid-source voltage regulating module and the signal output end, and the drain electrode of the first field effect transistor is respectively connected with the fourth grid-source voltage regulating module, the second constant current module and the second grid-source voltage regulating module.
For the second field effect tube, the grid electrode of the second field effect tube is respectively connected with the first grid source voltage regulating module, the fourth grid source voltage regulating module and the second constant current module, the drain electrode of the second field effect tube is respectively connected with the first constant current module, the first grid source voltage regulating module and the signal output end, and the source electrode of the second field effect tube is respectively connected with the second constant current module, the fourth grid source voltage regulating module and the power output end.
For the third field effect transistor, the gate of the third field effect transistor is connected to the signal input terminal, the drain of the third field effect transistor is connected to the power input terminal and the first constant current module, and the source of the third field effect transistor is connected to the first gate-source voltage regulating module and the fourth gate-source voltage regulating module.
For the fourth field effect transistor, the drain electrode of the fourth field effect transistor is respectively connected with the third gate-source voltage regulating module and the first gate-source voltage regulating module, the source electrode of the fourth field effect transistor is respectively connected with the power output end, the second constant current module and the second gate-source voltage regulating module, and the grid electrode of the fourth field effect transistor is respectively connected with the first gate-source voltage regulating module, the second gate-source voltage regulating module and the second constant current module.
For the first current source, the first end of the first current source is connected to the power input end and the third gate-source voltage adjusting module respectively, and the second end of the first current source is connected to the first gate-source voltage adjusting module, the second gate-source voltage adjusting module and the signal output end respectively.
For the second current source, a first end of the second current source is connected to the first gate-source voltage regulation module, the second gate-source voltage regulation module and the fourth gate-source voltage regulation module respectively, and a second end of the second current source is connected to the second gate-source voltage regulation module, the fourth gate-source voltage regulation module and the power output end respectively.
More specifically, the first field effect transistor may be a P-type metal-oxide semiconductor field effect transistor. The second field effect transistor may be an N-type metal-oxide semiconductor field effect transistor. The third field effect transistor may be an N-type metal-oxide semiconductor field effect transistor. The fourth field effect transistor may be an N-type metal-oxide semiconductor field effect transistor.
The Metal-Oxide Semiconductor field effect transistor is generally called Metal Oxide Semiconductor (MOS) in English. Because the MOS tube adopts voltage control, the control mode is more convenient. And the MOS pipe has advantages such as small, light in weight, longe-lived, input resistance is high, the noise is low, thermal stability is good, the interference killing feature is strong, the low power dissipation, consequently, each field effect transistor in the source follower of this application embodiment adopts the MOS pipe, can further promote each item performance of source follower to and make the source follower be convenient for control.
Next, the source follower provided in the embodiments of the present application is described in detail with reference to a specific first field effect transistor, a specific second field effect transistor, a specific third field effect transistor, a specific fourth field effect transistor, a specific first current source, and a specific second current source.
Fig. 3 is a second schematic structural diagram of a source follower in an embodiment of the present application, and referring to fig. 3, the source follower at least includes: the power supply comprises a signal input end, a signal output end, a power input end, a power output end, a first current source I1, a second current source I2, a first field-effect tube MP1, a second field-effect tube MN1, a third field-effect tube MN2 and a fourth field-effect tube MN3.
The signal input end is used for receiving an input signal Vin. The signal output terminal is used for outputting an output signal Vout. Generally, the input signal Vin and the output signal Vout may refer to analog voltage signals. The power input end is connected with a power supply VDD, and the power output end is connected with a ground potential VSS.
In the source follower, the connection relationship of each component may specifically be: the signal input end is connected with the grid electrode of the third field effect transistor MN 2. The power input end is respectively connected with the drain electrode of the third field effect transistor MN2 and the first end of the first current source I1. The source electrode of the third field effect transistor MN2 is connected to the gate electrode of the first field effect transistor MP1 and the drain electrode of the fourth field effect transistor MN3, respectively. The second end of the first current source I1 is connected to the source of the first fet MP1 and the drain of the second fet MN1, respectively. The grid electrode of the first field effect transistor MP1 is further connected to the drain electrode of the fourth field effect transistor MN3, and the drain electrode of the first field effect transistor MP1, the grid electrode of the fourth field effect transistor MN3, the grid electrode of the second field effect transistor MN1 and the first end of the second current source I2 are connected to each other. The source electrode of the fourth field effect transistor MN3, the second end of the second current source I2 and the source electrode of the second field effect transistor MN1 are mutually connected and are connected with the power supply output end. The second terminal of the first current source I1, the source of the first fet MP1, and the drain of the second fet MN1 are connected to each other and to the signal output terminal.
When the source follower works, the power input end is connected with a power supply VDD, and the power output end is connected with a ground potential VSS. The first field effect tube MP1, the second field effect tube MN1, the third field effect tube MN2, and the fourth field effect tube MN3 are all in a conducting state, i.e., all work in a saturation region. When the input signal is Vin, the voltage at the point B is Vin-Vgsmn2, and Vgsmn2 is Vgs of the third field effect transistor MN 2. Then, the output signal outputted through the first fet MP1 is Vout = Vin-Vgsmn2+ Vgsmp1, and Vgsmp1 is Vgs of the first fet MP 1. It should be noted here that Vgs described in the embodiment of the present application is an absolute value. After the output signal Vout = Vin-Vgsmn2+ Vgsmp1, vout is equal to Vin if Vgsmn2 is substantially equal to Vgsmp 1. It can be seen that the third fet MN2, which is increased in the source follower, shifts the input voltage Vin by a Vgs voltage.
Fig. 4 is a diagram illustrating an input/output curve of the source follower in fig. 1, and referring to fig. 3, an abscissa Vin represents an input voltage of the source follower, and an ordinate Vout represents an output voltage of the source follower.
The dotted line is the input voltage and the solid line is the output voltage. It can be seen that the output voltage of the source follower has a voltage rise of one Vgs relative to the input voltage, thereby increasing the difference between the input voltage and the output voltage of the random follower, and reducing the detection accuracy of the signal in the signal detection to which the source follower is applied.
Fig. 5 is a schematic diagram of the input/output curve of the source follower in fig. 3, and referring to fig. 5, the abscissa Vin represents the input voltage of the source follower, and the ordinate Vout represents the output voltage of the source follower. The dotted line is the input voltage and the solid line is the output voltage. It can be seen that after the input voltage Vin is shifted by one Vgs voltage by the third field effect transistor MN2, the output voltage of the source follower is raised by one Vgs voltage with respect to the input voltage only in the case where the input voltage is lower than one threshold voltage Vth. Whereas the output voltage of the source follower almost completely overlaps the input voltage except for the case where the input voltage is lower than a threshold voltage Vth. Thus, a voltage difference Vgs between the input and output voltages of the source follower is almost eliminated, and thus, in signal detection, a deviation between a signal detection value and a signal actual value caused by the voltage difference between the input and output of the source follower can be avoided, thereby improving the detection accuracy of the signal.
Therefore, by adding a field effect transistor, namely the third field effect transistor MN2, behind the signal input end of the source follower, vgs deviation can be carried out on input voltage input into the source follower, so that the difference between the input voltage and the output voltage in the source follower is reduced, the swing of the source follower is reduced, and when the source follower is applied to signal detection, the deviation between a signal detection value and a signal actual value can be reduced, and the detection precision of the signal is improved.
The third fet MN2 not only can shift the input signal Vin by one Vgs, but also can ensure that the source follower has a low output resistance. Next, a specific operation principle thereof will be explained.
When the source follower works, the power input end is connected with a power supply VDD, and the power output end is connected with a ground potential VSS. The first field effect transistor MP1, the second field effect transistor MN1, the third field effect transistor MN2, and the fourth field effect transistor MN3 are all in a conducting state, that is, all work in a saturation region. After a negative incremental signal Δ V is superimposed on the input signal Vin (i.e., the input signal Vin is decreased) and sent to the signal input terminal, the absolute value of Vgs of the third field-effect transistor MN2 is decreased (since the third field-effect transistor MN2 is generally an n-type field-effect transistor, the actual value of Vgs is a positive value, the input signal Vin is decreased, the actual value of Vgs of the third field-effect transistor MN2 is decreased, and thus the absolute value thereof is also decreased), and further, the leakage current Imn2 flowing through the third field-effect transistor MN2 is also decreased. Since the leakage current Imn2 of the third fet MN2 is smaller than the leakage current Imn3 of the fourth fet MN3 after being reduced, the voltage of the node B is reduced (the input current is reduced, which is equivalent to the input charge amount being reduced, and the output current and the charge amount are unchanged, and the charge amount of the node B is reduced as a whole, so the voltage of the node B is reduced), and further the absolute value of Vgs of the first fet MP1 is increased (the first fet MP1 is generally a p-type fet, and the actual value of Vgs is a negative value, the voltage of the node B is reduced, the actual value of Vgs of the first fet MP1 is smaller, and the absolute value thereof is larger), and further the leakage current Imp1 of the first fet MP1 is increased. Due to the negative feedback effect of the second field effect transistor MN1, the current of the node a is increased, which further causes the voltage of the node a to increase, and further increases the absolute value of Vgs of the second field effect transistor MN1 (since the second field effect transistor MN1 is generally an n-type field effect transistor, the actual value of Vgs is a positive value, and the voltage of the node a increases, the actual value of Vgs of the second field effect transistor MN1 is larger, so the absolute value thereof increases), and further increases the leakage current Imn1 flowing through the second field effect transistor MN1, and finally rapidly decreases the output signal Vout (the first current source I1 is unchanged, the leakage current Imn1 of the second field effect transistor MN1 is increased, for the signal output terminal, the input charge amount is unchanged, the output charge amount is increased, and the charge amount of the output terminal is decreased as a whole, so the voltage thereof decreases). And the second current source I2 plays a role in stabilizing the current in the circuit as a whole. Therefore, the output resistance of the source follower is lowered by the third fet MN2, as viewed from the direction of the signal output terminal toward the inside of the source follower.
Therefore, after the third field-effect tube MN2 is added in the source follower, the output signal Vout can be ensured to be reduced, and the output resistance of the source follower is further ensured to be reduced, so that the source follower can be driven stably under heavy load on the basis of not increasing the size of a power tube of the source follower.
The above details show that the addition of the third field effect transistor MN2 in the source follower not only can cause the input signal Vin to generate a Vgs offset, reduce the difference between the input signal and the output signal, and improve the detection accuracy of the signal, but also can ensure that the output resistance of the source follower is reduced, so that when the source follower is applied to a heavy load, the stability of the heavy load can be ensured. And another field effect transistor added in the source follower, namely a fourth field effect transistor MN3, can form a negative feedback with the first field effect transistor MP1 again, so that the output resistance of the source follower is further reduced. The operation principle thereof will be explained in detail below.
When the source follower works, the power input end is connected with a power supply VDD, and the power output end is connected with a ground potential VSS. The first field effect transistor MP1, the second field effect transistor MN1, the third field effect transistor MN2, and the fourth field effect transistor MN3 are all in a conducting state, i.e., all work in a saturation region. After the negative incremental signal Δ V is superimposed on the input signal Vin (i.e., the input signal Vin is decreased), and the input signal Vin is sent to the signal input end, the absolute value of Vgs of the third fet MN2 is decreased (since the third fet MN2 is generally an n-type fet and the actual value of Vgs of the third fet is a positive value, the input signal Vin is decreased, the actual value of Vgs of the third fet MN2 is decreased, and thus the absolute value of Vgs of the third fet is also decreased), and the leakage current Imn2 flowing through the third fet MN2 is also decreased. Since the leakage current Imn2 of the third fet MN2 is smaller than the leakage current Imn3 of the fourth fet MN3 after being reduced, the voltage of the node B is reduced (the input current is reduced, which is equivalent to the input charge amount is reduced, while the output current and the charge amount are unchanged, and the charge amount at the node B is reduced as a whole, so the voltage of the node B is reduced), and further the absolute value of Vgs of the first fet MP1 is increased (the first fet MP1 is generally a p-type fet, and the actual value of Vgs is negative, the voltage of the node B is reduced, the actual value of Vgs of the first fet MP1 is smaller, and the absolute value thereof is larger), and further the leakage current Imp1 of the first fet MP1 is increased. Due to the negative feedback action of the fourth fet MN3, when the leakage current Imp1 of the first fet MP1 increases, the voltage of the node a increases because the current of the second current source I2 does not change (the input current increases, the amount of charge increases, while the output current and the amount of charge do not change, and the amount of charge increases at the node a as a whole, so the voltage of the node a increases). The voltage of the node A is increased, so that the value of Vgs of the fourth field effect transistor MN3 is increased, and further, the leakage current Imn3 of the fourth field effect transistor MN3 is increased. Since the leakage current Imn2 flowing through the third fet MN2 decreases and the leakage current Imn3 flowing through the fourth fet MN3 increases, that is, the input charge amount decreases and the output charge amount increases, and the charge amount of the node B as a whole decreases, the voltage at the node B further decreases. Further decrease of the voltage of the node B further increases the absolute value of Vgs of the first field-effect transistor MP1, further increases the leakage current Imp1 of the first field-effect transistor MP1, and finally further decreases the output signal Vout (the change of parameters of each component in a loop formed by the first field-effect transistor MP1, the node a, the second field-effect transistor MN1, and the signal output end is consistent with the foregoing description, and is not described herein again), and the output resistance of the source follower is further decreased when the source follower is seen from the direction of the signal output end.
Therefore, the fourth field effect transistor MN3 is added to the source follower, and by the above-mentioned working mechanism, the output signal Vout can be further lowered, and further, the output resistance of the source follower is further lowered when the source follower is seen from the direction of the signal output terminal, so that the pole of the output terminal of the error amplifier in the heavy load can be further ensured to be pushed to the high frequency, and the stability of the heavy load can be further ensured.
The working principle of further reducing the output resistance of the source follower is described in the case of superimposing a negative incremental signal Δ V on the input signal Vin (i.e., reducing the input signal Vin), and conversely, if superimposing a positive incremental signal Δ V on the input signal Vin (i.e., increasing the input signal Vin), it can also be described that the output resistance of the source follower can be further reduced after the fourth field-effect transistor MN3 is added to the source follower. Next, the operation principle of the source follower will be explained by taking an example of superimposing a positive incremental signal Δ V on the input signal Vin.
When the source follower works, the power input end is connected with a power supply VDD, and the power output end is connected with a ground potential VSS. The first field effect transistor MP1, the second field effect transistor MN1, the third field effect transistor MN2, and the fourth field effect transistor MN3 are all in a conducting state, i.e., all work in a saturation region. After a positive incremental signal Δ V is superimposed on the input signal Vin (i.e., the input signal Vin is increased) and sent to the signal input terminal, the absolute value of Vgs of the third fet MN2 is increased, and the leakage current Imn2 flowing through the third fet MN2 is increased. Since the drain current Imn2 of the third fet MN2 is greater than the drain current Imn3 of the fourth fet MN3 after increasing, the voltage at the node B increases, and thus the absolute value of Vgs of the first fet MP1 decreases, and the drain current Imp1 flowing through the first fet MP1 decreases. Due to the fact that the leakage current Imp1 flowing through the first field effect transistor MP1 is reduced and the negative feedback effect of the fourth field effect transistor MN3 is achieved, the voltage of the node A is reduced, the absolute value of Vgs of the fourth field effect transistor MN3 is reduced, the leakage current Imn3 of the fourth field effect transistor MN3 is reduced, and the voltage of the node B is increased. The voltage increase of the node B in turn further decreases Vgs of the first field effect transistor MP1, and further decreases the leakage current Imp1 of the first field effect transistor MP1, and finally further increases the output signal Vout.
It can be seen that even if the input signal Vin at the signal input terminal is raised, the output signal Vout at the signal output terminal is further raised by adding the working mechanisms in the source followers of the third fet MN2 and the fourth fet MN3. The output resistance of the source follower is still further reduced when the source follower is seen from the direction of the signal output end, and the pole of the output end of the error amplifier in the heavy load can be pushed to high frequency, so that the stability of the heavy load is ensured.
The source follower provided by the embodiment of the application can be applied to the following two scenarios.
Scene one: and the LDO is driven by a heavy-duty low dropout regulator (LDO).
In a heavy LDO, the source follower provided by the embodiment of the present application may act as a buffer. That is, in the LDO, an error amplifier, a source follower, and a power tube are connected in this order. Due to the characteristic of low output resistance of the source follower, the source follower can push the pole of the output end of the error amplifier in the LDO to high frequency, so that the stability of heavy load is ensured.
Specifically, the signal input terminal of the source follower needs to be connected with the output terminal of the error amplifier in the LDO. The signal output end of the source follower needs to be connected with the input end of a power tube in the LDO. Therefore, the source follower can push the pole of the output end of the error amplifier in the LDO to high frequency, and the stability of heavy load is ensured.
Scene two: and (5) signal detection.
The source follower provided by the embodiment of the application is applied to the detection circuit, namely, the detection circuit detects the signal of the detection node through the source follower, and the influence of the detection circuit on the signal in the detection node can be isolated.
Specifically, a signal input terminal of the source follower needs to be connected to the detection node, a signal output terminal of the source follower needs to be connected to the detection circuit, and the detection circuit is used for detecting a signal of the detection node. In this way, the influence of the detection circuit on the signal in the detection node can be eliminated by the source follower.
Based on the same inventive concept, as an implementation of the source follower, the embodiment of the present application further provides a driving method of the source follower. The driving method is applied to the source follower. Fig. 6 is a schematic flowchart of a driving method of a source follower in an embodiment of the present application, and referring to fig. 6, the driving method may include:
s601: the signal input end receives an input signal after the negative/positive incremental signal is superposed;
s602: the third grid-source voltage regulating module carries out displacement of grid-source voltage on the input signal on which the negative/positive incremental signal is superposed, and reduces/increases the grid-source voltage of the third grid-source voltage regulating module based on the displaced input signal;
s603: the first grid-source voltage regulating module increases/decreases the grid-source voltage of the first grid-source voltage regulating module based on the decreased/increased grid-source voltage of the third grid-source voltage regulating module;
s604: the fourth grid-source voltage regulating module increases/decreases the grid-source voltage of the fourth grid-source voltage regulating module based on the increased/decreased grid-source voltage of the first grid-source voltage regulating module;
s605: the first grid-source voltage regulating module further increases/decreases the grid-source voltage of the first grid-source voltage regulating module based on the increased/decreased grid-source voltage of the fourth grid-source voltage regulating module;
s606: the second grid-source voltage regulating module increases/decreases the grid-source voltage of the second grid-source voltage regulating module based on the further increased/decreased grid-source voltage of the first grid-source voltage regulating module, so that the input signal superposed with the negative/positive incremental signal is decreased/increased, and the decreased/increased output signal is obtained;
s607: the signal output terminal outputs the decreased/increased output signal.
Further, the signal input end receives a signal output by the output end of the error amplifier in the low dropout linear regulator, and the signal output end sends the processed signal to the input end of the power tube in the low dropout linear regulator.
Furthermore, the signal input end receives the signal output by the detection node, and the signal output end sends the processed signal to the detection circuit.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Finally, it is also noted that the terms "comprises" and "comprising," and any variations thereof, in the description and claims of this application and in the description of the above figures, are intended to cover non-exclusive inclusions.
In the description of the embodiments of the present application, the technical terms "first", "second", and the like are used only for distinguishing different objects, and are not to be construed as indicating or implying relative importance or implicitly indicating the number, specific order, or primary-secondary relationship of the technical features indicated. In the description of the embodiments of the present application, "a plurality" means two or more unless specifically defined otherwise.
Reference herein to "an embodiment" means that a particular feature or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
In the description of the embodiments of the present application, the term "and/or" is only one kind of association relationship describing an associated object, and means that three relationships may exist, for example, a and/or B, and may mean: there are three cases of A, both A and B, and B. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
In the description of the embodiments of the present application, the term "plurality" refers to two or more (including two), and similarly, "plural sets" refers to two or more (including two), and "plural pieces" refers to two or more (including two).
In the description of the embodiments of the present application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", and the like, indicate the directions or positional relationships indicated in the drawings, and are only for convenience of description of the embodiments of the present application and for simplicity of description, but do not indicate or imply that the referred device or element must have a specific direction, be constructed and operated in a specific direction, and thus, should not be construed as limiting the embodiments of the present application.
In the description of the embodiments of the present application, unless otherwise explicitly stated or limited, the terms "mounted," "connected," "fixed," and the like are used in a broad sense, and for example, may be fixedly connected, detachably connected, or integrated; mechanical connection or electrical connection is also possible; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the embodiments of the present application can be understood by those of ordinary skill in the art according to specific situations.
Claims (6)
1. A source follower, the source follower comprising: the grid-source voltage regulation circuit comprises a signal input end, a signal output end, a power input end, a power output end, a first constant current module, a second constant current module, a first grid-source voltage regulation module, a second grid-source voltage regulation module, a third grid-source voltage regulation module and a fourth grid-source voltage regulation module;
the first gate-source voltage regulating module is a first field effect transistor, the second gate-source voltage regulating module is a second field effect transistor, the third gate-source voltage regulating module is a third field effect transistor, and the fourth gate-source voltage regulating module is a fourth field effect transistor;
the signal input end is connected with the grid electrode of the third field effect transistor;
the power supply input end is respectively connected with the drain electrode of the third field effect transistor and the first end of the first constant current module;
the source electrode of the third field effect transistor is also respectively connected with the grid electrode of the first field effect transistor and the drain electrode of the fourth field effect transistor;
the second end of the first constant current module is also connected with the source electrode of the first field effect transistor and the drain electrode of the second field effect transistor;
the drain electrode of the first field effect transistor is also connected with the grid electrode of the fourth field effect transistor, the grid electrode of the second field effect transistor and the first end of the second constant current module;
the source electrode of the fourth field effect transistor and the second end of the second constant current module are connected with each other and the source electrode of the second field effect transistor is connected with the power supply output end;
and the second end of the first constant current module, the source electrode of the first field effect transistor and the drain electrode of the second field effect transistor are mutually connected and are connected with the signal output end.
2. The source follower of claim 1, wherein the first constant current module is a first current source and the second constant current module is a second current source;
a first end of the first current source is connected with the power supply input end and the drain electrode of the third field effect transistor respectively, and a second end of the first current source is connected with the source electrode of the first field effect transistor, the drain electrode of the second field effect transistor and the signal output end respectively;
the first end of the second current source is connected with the drain electrode of the first field effect transistor, the grid electrode of the second field effect transistor and the grid electrode of the fourth field effect transistor respectively, and the second end of the second current source is connected with the source electrode of the second field effect transistor, the source electrode of the fourth field effect transistor and the power output end respectively.
3. The source follower of claim 1, wherein the first fet is a P-type metal-oxide semiconductor fet; alternatively, the first and second electrodes may be,
the second field effect transistor is an N-type metal-oxide semiconductor field effect transistor; alternatively, the first and second electrodes may be,
the third field effect transistor is an N-type metal-oxide semiconductor field effect transistor; alternatively, the first and second electrodes may be,
the fourth field effect transistor is an N-type metal-oxide semiconductor field effect transistor.
4. The source follower of claim 1, wherein the signal input terminal is connected to an output terminal of an error amplifier of a low dropout regulator, and the signal output terminal is connected to an input terminal of a power transistor of the low dropout regulator.
5. The source follower according to any of claims 1 to 4, wherein the signal input terminal is connected to a detection node, and the signal output terminal is connected to a detection circuit for detecting a signal of the detection node.
6. A driving method of a source follower, wherein the driving method is applied to the source follower of any one of claims 1 to 5; the driving method includes:
the signal input end receives an input signal after the negative/positive incremental signal is superposed;
the third grid-source voltage regulating module carries out displacement of grid-source voltage on the input signal on which the negative/positive incremental signal is superposed, and reduces/increases the grid-source voltage of the third grid-source voltage regulating module based on the displaced input signal;
the first grid-source voltage regulating module increases/decreases the grid-source voltage of the first grid-source voltage regulating module based on the decreased/increased grid-source voltage of the third grid-source voltage regulating module;
the fourth gate-source voltage regulating module increases/decreases the gate-source voltage of the fourth gate-source voltage regulating module based on the increased/decreased gate-source voltage of the first gate-source voltage regulating module;
the first grid-source voltage regulating module further increases/decreases the grid-source voltage of the first grid-source voltage regulating module based on the increased/decreased grid-source voltage of the fourth grid-source voltage regulating module;
the second grid-source voltage regulating module increases/decreases the grid-source voltage of the second grid-source voltage regulating module based on the further increased/decreased grid-source voltage of the first grid-source voltage regulating module, so that the input signal superposed with the negative/positive incremental signal is decreased/increased, and the decreased/increased output signal is obtained;
the signal output terminal outputs the decreased/increased output signal.
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