CN114582864A

CN114582864A - Power semiconductor device and electronic equipment

Info

Publication number: CN114582864A
Application number: CN202011379684.2A
Authority: CN
Inventors: 王怀锋; 张栋梁; 杨成军; 胡善柏
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-11-30
Filing date: 2020-11-30
Publication date: 2022-06-03
Also published as: WO2022111484A1; JP2023552153A

Abstract

The application provides a power semiconductor device and electronic equipment, and the power semiconductor device includes epitaxial layer and two field effect transistors, and the epitaxial layer is provided with a slot, two field effect transistors mirror symmetry. Each field effect transistor includes a first MOS structure and a second MOS structure in series. The first channel of the first MOS structure and the second channel of the second MOS structure are arranged at intervals along the depth direction of the groove; the first grid of the first MOS structure and the second grid of the second MOS structure are arranged at intervals along the depth direction of the groove. In the technical scheme, the first grid and the second grid are longitudinally arranged along the depth direction of the groove, so that the transverse occupied size of the field effect transistor is reduced. The first MOS structure and the second MOS structure share the drift region, so that the resistance of the drift region is reduced, and the characteristic on-resistance of the power semiconductor device in unit area is reduced by symmetrically connecting two identical field effect transistors back to back in parallel.

Description

Power semiconductor device and electronic equipment

Technical Field

The present disclosure relates to circuit technologies, and particularly to a power semiconductor device and an electronic apparatus.

Background

As power integrated circuits and devices are developed toward miniaturization, power semiconductor devices also exhibit high integration, miniaturization, high performance, and low cost as one of core electronics of the power integrated circuits. For example, as a core element of a battery management and charging system protection circuit in an electronic device, a power semiconductor device can effectively protect a battery and a charging load from over-discharge, over-overshoot, and over-current, and realize output short-circuit protection.

The power Semiconductor device in the battery management and charging system protection circuit is a switching device mainly comprising a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) made of silicon material. In addition, the field effect transistor applied in the battery management and charging system protection circuit needs to have bidirectional blocking and bidirectional conducting functions to perform bidirectional protection on the lithium battery and the load circuit, and the common scheme in the industry is to symmetrically connect two MOSFETs with the same structure in series with common drain electrodes to form a common drain type power semiconductor device. Fig. 1 is a semiconductor device in which two vertical MOSFETs are connected in series with a common drain, and a main structure of the power semiconductor device includes a substrate 4 and an epitaxial layer 3 disposed on the substrate 4, where the substrate 4 is a silicon substrate and the epitaxial layer 3 is a silicon epitaxial layer. Each MOSFET structure comprises a gate 1 and a source 2 disposed on the surface of an epitaxial layer 3, and a channel (not shown) located within epitaxial layer 3. The bottom of the substrate is provided with a back metal which is used as a common drain electrode of the two MOSFETs. A drift region (not shown) corresponding to each MOSFET is provided in the epitaxial layer 3. The two sources 2 are respectively used as the input end and the output end of the power semiconductor device, and the two gates 1 respectively control the on or off of the input end MOSFET and the output end MOSFET.

In the off condition, the gate of the output (or input) MOSFET is at a high level, the input (or output) MOSFET is on, but the gate of the input (or output) MOSFET is at a low level, and the input (or output) MOS structure is off, so that a bidirectional blocking withstand voltage from the source of one MOSFET (output) to the source of the other MOSFET (input) is realized. Under the condition of conduction, the grids of the MOSFET at the input end and the MOSFET at the output end are simultaneously in high level, and the MOSFET at the input end and the MOSFET at the output end are simultaneously turned on. As shown in fig. 1 by the arrowed lines indicating the direction of current flow, current flows from the source 2 of one MOSFET through the channel, the drift region (located within the epitaxial layer 3, not shown), through the substrate 4, through the drift region and the channel of the other MOSFET and to the source 2.

Under the condition that the power semiconductor device is conducted, current flows through a drift region and a primary substrate 4 in an epitaxial layer 3 passing through a circuit twice, the drift region resistance of the epitaxial layer 3 and the substrate resistance of the substrate 4 increase the on-resistance of the whole power semiconductor device, and along with the continuous reduction of the process size of a metal oxide semiconductor field effect transistor, the proportion of the resistance of the drift region and the resistance of the substrate in the total resistance is increased, in addition, structures such as a grid electrode 1 and a source electrode 2 are arranged on the surface of the epitaxial layer and are transversely distributed, the waste of the chip area of the power semiconductor device is caused, the characteristic conduction of the unit area and the cost of the unit area of the device are further increased, the miniaturization of the power semiconductor device is difficult, under the same device area, the loss and the temperature rise of a battery management and charging system protection circuit are increased, and the charging efficiency is reduced.

Disclosure of Invention

The application provides a power semiconductor device and electronic equipment, which are used for improving the characteristic on-resistance of a unit area of the device under the condition of meeting a certain voltage withstanding requirement of the power semiconductor device, so that the power semiconductor device is developed towards miniaturization.

In a first aspect, a power semiconductor device is provided, which includes a first doping type epitaxial layer and two common-drain type metal oxide semiconductor field effect transistors; the first doping type epitaxial layer is provided with a groove; and two common-drain type metal oxide semiconductor field effect transistors are symmetrically connected in parallel back to form a unit cell. Each common-drain type metal oxide semiconductor field effect transistor comprises a first metal oxide semiconductor structure and a second metal oxide semiconductor structure which are arranged along the depth direction of the groove, and the first metal oxide semiconductor structure and the second metal oxide semiconductor structure are connected in series in a common-drain mode. The first metal oxide semiconductor structure comprises a first source electrode, a first channel and a first grid electrode. The first channel is arranged in the first doping type epitaxial layer, the first source electrode is connected with the first channel, and the first source electrode and the first channel are located on the same side of the groove. The first channel is a second doping type area arranged in the first doping type epitaxial layer. The first grid is arranged in the groove and used for controlling the conduction of the first channel. The second metal oxide semiconductor structure comprises a second source electrode, a second channel and a second grid electrode. The second source electrode is positioned at the bottom of the groove, and the second channel is positioned in the first doping type epitaxial layer and connected with the second channel. The second channel is a second doping type region arranged in the first doping type epitaxial layer. The second gate is disposed in the trench and is used to control the second channel to conduct. When the structure is specifically arranged, the first channel and the second channel are longitudinally arranged at intervals along the depth direction of the groove, part of the first doping type epitaxial layer between the first channel and the second channel is a drift region, and the drift region and the first channel are positioned on the same side of the groove and are longitudinally and vertically arranged with the first channel. The second grid and the first grid are arranged at intervals along the depth direction of the groove in the longitudinal direction. When the first gate and the second gate respectively control the conduction of the first channel and the second channel, current flows along the arrangement direction or the opposite direction of the first source, the first channel, and a part of the first doping type epitaxial layer (drift region) between the first channel and the second channel, and the second source. In addition, when two common-drain type metal oxide semiconductor field effect transistors are specifically arranged, the second sources of the two common-drain type metal oxide semiconductor field effect transistors are shared, and two first channels of the two common-drain type metal oxide semiconductor field effect transistors are respectively arranged on two opposite sides of the groove; the two first source electrodes are respectively arranged on two opposite sides of the groove. In the technical scheme, the first grid and the second grid are longitudinally arranged along the depth direction of the groove, so that the size occupied in the transverse direction of the common-drain metal oxide field effect transistor is reduced.

In a specific embodiment, each of the common drain type mosfets further includes: a first gate oxide layer isolating the first channel from the first gate; and a second gate oxide layer isolating the second channel from the second gate, wherein the first gate oxide layer and the second gate oxide layer have substantially the same thickness. The first grid oxide layer and the second grid oxide layer reduce grid electric leakage, improve grid voltage endurance capability and improve grid driving capability.

In one specific implementation, the first gate oxide layer and the second gate oxide layer are disposed on sidewalls of the trench. And forming a first gate structure arranged along the depth of the groove by the first gate oxide layer arranged on the side wall of the groove, so that the transverse size of the power semiconductor device is reduced.

In a specific embodiment, the trench is filled with a filling layer that wraps the first gate, the second gate and the second source. The first grid, the second grid and the second source are isolated by the filling layer.

In a specific embodiment, the second source electrode is exposed outside the filling layer, and the part of the second source electrode exposed outside the filling layer is used as a connecting terminal. And the connection with an external circuit is convenient.

In a specific possible embodiment, the first source electrode is partially exposed on the first doping type epitaxial layer, and the part of the first source electrode exposed on the first doping type epitaxial layer serves as a connection terminal. And the connection with an external circuit is convenient.

In a specific embodiment, a first source contact region is disposed within the first doping type epitaxial layer, and the first channel is connected to the first source through the first source contact region. The contact effect of the first source electrode and the first channel is improved through the arranged first source electrode contact region.

In a specific embodiment, the first source contact region includes a heavily doped region of the first doping type and a heavily doped region of the second doping type.

In a specific embodiment, a second source contact region is disposed within the first doping type epitaxial layer, and the second channel is connected to the second source through the second source contact region. The contact effect of the second source electrode and the second channel is improved through the arranged second source electrode contact region.

In a specific possible embodiment, the second source contact region includes a heavily doped region of the first doping type and a heavily doped region of the second doping type.

In a specific embodiment, the heavily doped region of the second doping type of the second source contact region is located below the bottom of the second source, and the heavily doped region of the first doping type of the second source contact region is located at one side of the second source.

In a specific possible embodiment, the groove is a straight groove; the first grid and the second grid are longitudinally arranged along the depth direction of the groove. The size of the common-drain type metal oxide semiconductor field effect transistor is reduced, and the arrangement density of the devices is improved.

In a specific embodiment, the first gate and the second gate are offset along the depth direction of the trench. The first grid oxide layer, the second grid oxide layer, the first grid and the second grid are convenient to arrange.

In a specific embodiment, the trench is a T-shaped trench; the second grid electrode is arranged at the bottom of the T-shaped groove; the first grid is arranged on the step surface of the T-shaped groove. The first grid and the second grid are convenient to arrange.

In a second aspect, an electronic device is provided, which includes a battery and a charge protection circuit connected to the battery, wherein the charge protection circuit includes any one of the power semiconductor devices described above. In the above technical solution, the drift region, the first gate and the second gate are longitudinally arranged along the depth direction of the trench, so as to reduce the size occupied in the transverse direction of the common-drain mosfet.

Drawings

Fig. 1 is a schematic structural diagram of a power semiconductor device in the prior art;

fig. 2 is a schematic view of an application scenario of a power semiconductor device according to an embodiment of the present disclosure;

fig. 3 is a cross-sectional view of a power semiconductor device provided in an embodiment of the present application;

fig. 4 is a top view of a power semiconductor device provided in an embodiment of the present application;

fig. 5 is a schematic current diagram of a power semiconductor device provided in an embodiment of the present application;

fig. 6 is a schematic view of an application scenario of a power semiconductor device according to an embodiment of the present application;

fig. 7 is a schematic diagram of a simulation structure of a power semiconductor device according to an embodiment of the present application;

fig. 8a shows the breakdown characteristics of the second MOS structure to the first MOS structure according to an embodiment of the present application;

fig. 8b shows the breakdown characteristics of the first MOS structure to the second MOS structure according to the embodiment of the present application;

fig. 9a is a diagram illustrating transfer switching characteristics from a second MOS structure to a first MOS structure according to an embodiment of the present application;

fig. 9b is a diagram illustrating a transfer switching characteristic from a first MOS structure to a second MOS structure according to an embodiment of the present application;

fig. 10 is a cross-sectional view of a power semiconductor device provided in an embodiment of the present application;

fig. 11 is a top view of a power semiconductor device provided in an embodiment of the present application;

fig. 12 is a schematic current diagram of a power semiconductor device according to an embodiment of the present application;

fig. 13 is a schematic diagram of a simulation structure of a power semiconductor device according to an embodiment of the present application;

fig. 14a shows the breakdown characteristics of the second MOS structure to the first MOS structure according to an embodiment of the present application;

fig. 14b shows the breakdown characteristics of the first MOS structure to the second MOS structure according to the embodiment of the present application;

fig. 15a shows a transfer switching characteristic of the second MOS structure to the first MOS structure according to an embodiment of the present application;

fig. 15b shows a transfer switching characteristic from the first MOS structure to the second MOS structure according to an embodiment of the present application.

Detailed Description

The embodiments of the present application will be further described with reference to the accompanying drawings.

To facilitate understanding of the power semiconductor device used in the embodiments of the present application, an application scenario of the power semiconductor device provided in the embodiments of the present application is first described, and the power semiconductor device provided in the embodiments of the present application may be applied to a battery management and charging protection system of a portable electronic device such as a smart phone, a smart watch, a tablet computer, or may also be applied to different scenarios of protecting a current conversion system, a power IC, and the like. In the scenario of a battery protection system as shown in fig. 2, a battery 5 is used to supply power to a load 6, and a protection circuit is provided between the battery 5 and a charge 6. The protection circuit consists of a power semiconductor device 7 and a control chip 8, wherein the power semiconductor device 7 consists of two MOS structures 9 which are connected in series. In use, the two MOS structures 9 can be controlled to be turned on by the control chip 4008. The power semiconductor device 7 described above can effectively protect the battery from being over-discharged, over-charged, and over-current (current beyond the range of design). However, the power semiconductor device in the prior art has the problems of overlarge size and larger characteristic on-resistance per unit area. Therefore, the embodiment of the application provides the power semiconductor device, so that the miniaturization of the power semiconductor device is facilitated and the characteristic on-resistance per unit area is improved by reasonably improving the structure and the layout of the power semiconductor device. The details are described below with reference to the specific drawings and examples.

To facilitate understanding of the power semiconductor devices provided in the embodiments of the present application, the following terms related to the present application will be first described.

PN junction: different doping processes are adopted, a P-type semiconductor and an N-type semiconductor are manufactured on the same semiconductor (usually silicon or germanium) substrate through diffusion, a space charge region called a PN junction (PN junction) is formed at the interface of the P-type semiconductor and the N-type semiconductor, and the PN junction has unidirectional conductivity.

Channel: refers to a thin semiconductor layer between a source region and a drain region in a field power semiconductor device.

A drift region: refers to a high resistance region with a very small number of charge carriers under the dual influence of drift motion and diffusion in a power semiconductor device.

Epitaxial layer: refers to a semiconductor layer epitaxially grown on a substrate.

On-resistance: refers to the resistance value of the power semiconductor device operating in the linear region.

Threshold voltage: generally, in a transfer characteristic curve of a power semiconductor device, an input voltage corresponding to a midpoint of a transition region where an output current sharply changes with a change in an input voltage is referred to as a threshold voltage.

The first doping type and the second doping type related in the embodiment of the present application are P type and N type, respectively, for example, if the power semiconductor device is an electronic conduction type, the first doping type is N type, and the second doping type is P type; if the power semiconductor device is of a hole conduction type, the first doping type is of a P type, and the second doping type is of an N type. In the following examples of the present application, the first doping type is N-type, and the second doping type is P-type. The same applies to the description of the examples of the present application when the first doping type is P-type and the second doping type is N-type.

To facilitate understanding of the power semiconductor device provided in the embodiments of the present application, a lateral direction and a longitudinal direction are defined. The longitudinal direction refers to a stacking direction of a layer structure of the power semiconductor device, and may also be referred to as a thickness direction of the power semiconductor device. The lateral direction refers to a direction perpendicular to the longitudinal direction and parallel to the arrangement direction of the two common drain type metal oxide semiconductor field effect transistors in the power semiconductor device.

Referring to fig. 3, fig. 3 shows a cross-sectional view of a power semiconductor device. The power semiconductor device at least comprises a substrate 11 and an epitaxial layer 12 arranged on the substrate 11, wherein the substrate 11 and the epitaxial layer 12 are two main layer structures of the power semiconductor device stack. The power semiconductor device provided by the embodiment of the application can further comprise other conventionally arranged layer structures (such as a passivation layer, an interconnection metal, a back metal layer and the like), and other layer structures are omitted in the application for convenience in describing the structure of the power semiconductor device.

The substrate 11 and the epitaxial layer 12 are arranged along a longitudinal direction, wherein the substrate 11 is a first doping type substrate, and the epitaxial layer 12 is a first doping type epitaxial layer. The epitaxial layer 12 is provided with trenches 31, the depth of the trenches 31 extending in the longitudinal direction (thickness direction of the power semiconductor device). The substrate 11 and the epitaxial layer 12 form a device body of the power semiconductor device, and the epitaxial layer 12 serves as a main structural member for carrying the power semiconductor device.

According to the functional division, the power semiconductor device provided by the embodiment of the present application includes two common-drain metal oxide semiconductor field effect transistors (referred to as field effect transistors for short), which are respectively named as a first field effect transistor 100 and a second field effect transistor 101 for convenience of description. As an example, when the first field effect transistor 100 and the second field effect transistor 101 are arranged, the first field effect transistor 100 and the second field effect transistor 101 are symmetrically disposed along a center line of the trench 31, and the first field effect transistor 100 and the second field effect transistor 101 are connected in parallel to form a cell (not labeled in fig. 3) structure of the power semiconductor device. It should be understood that, although only one cell structure is shown in fig. 3, the power semiconductor device provided in the embodiment of the present application may include a plurality of cells, and the plurality of cells may be periodically arranged. In the embodiments of the present application, only one cell is taken as an example for explanation.

The first field effect transistor 100 and the second field effect transistor 101 according to the embodiment of the present application are of a quasi-symmetric structure, and thus the first field effect transistor 100 is described as an example.

Referring to fig. 3, the field effect transistor 100 includes a first metal oxide semiconductor structure (1)^stA Metal-Oxide-semiconductor Structure (first MOS Structure for short) and a second MOS Structure (2)^ndA Metal-Oxide-semiconductor Structure, referred to as a second MOS Structure for short), and the first MOS Structure 10 and the second MOS Structure 20 are connected in series. When the first MOS structure 10 and the second MOS structure 20 are disposed, the first MOS structure 10 and the second MOS structure 20 are arranged in a longitudinal direction, and a portion of the first doping type epitaxial layer is spaced between the first MOS structure 10 and the second MOS structure 20, and serves as a drift region 30, and is shared by the first MOS structure 10 and the second MOS structure 20.

The first MOS structure 10 includes a first gate 51, a first source 61, and a first channel 21; the first gate 51 serves as a control component for turning on the first MOS structure 10, and is used for connecting to a control chip. The first gate 51 is used for controlling the first channel 21 to be turned on and off under the control of the control chip.

The first source 61 of the first MOS structure 10 is used as a connection terminal of the first MOS structure 10, and can be made of metal or metalloid (such as TiN, silicide, etc.). When provided, the first source electrode 61 may be provided on the surface of the epitaxial layer 12, or may be partially embedded or entirely embedded in the epitaxial layer 12. Fig. 3 illustrates a schematic structure in which only the first source 61 is completely embedded in the epitaxial layer 12, and other modes are not illustrated one by one here. When the first source electrode 61 is entirely buried in the epitaxial layer 12, a surface of the first source electrode 61 is exposed outside the epitaxial layer 12, and this surface serves as a connection surface for the first source electrode 61 for connection to another metal layer or an interconnection metal (not shown in fig. 3).

The first channel 21 is disposed within the epitaxial layer 12 and the first channel 21 and the first source 61 are disposed on the same side of the trench 31 as the first source 61 and the first source 61. Wherein the first channel 21 is close to the sidewall of the trench 31, and the first source 61 is far from the sidewall of the trench 31.

The first channel 21 is a second doping type region. In forming the first channel 21, a doped region of the second doping type is provided in the epitaxial layer 12 at the side wall of the trench 31 to form the first channel 21. The first channel 21 extends longitudinally along the sidewalls of the trench 31 and contacts the drift region 30. Since the first channel 21 is the second doping type region and the drift region 30 is the first doping type region, the drift region 30 and the first channel 21 may form a PN junction. When no voltage is applied to the first gate 51, or a voltage of 0 or a negative voltage is applied with respect to the first source 61, the PN junction between the first channel 21 and the drift region 30 is not turned on, so that the conduction path from the first source 61 to the first channel 21 to the drift region 30 is closed. Under the action of the voltage applied by the first gate 51, a portion of the first channel 21 near the sidewall of the trench 31 forms an inversion layer, which can be converted from the second doping type to the first doping type, so that the conduction path from the first channel 21 to the drift region 30 is conducted. At this time, the first source 61, the first channel 21 and the drift region 30 are turned on.

The first gate 51 is disposed in the trench 31 and opposite to the first channel 21. When a voltage is applied to the first gate 51, the conduction of the first channel 21 can be controlled.

As an optional solution, the first MOS structure 10 further includes a first gate oxide layer 41 isolating the first channel 21 from the first gate 51. The first gate oxide layer 41 is disposed on the sidewall of the trench 31 and between the first gate 51 and the first channel 21. The first gate oxide layer 41 can suppress an increase in leakage between the first channel 21 and the first gate 51, thereby improving the gate withstand voltage.

As an alternative, a first source contact region (not shown) is further disposed in the epitaxial layer 12, and the first source 61 is connected to the first channel 21 through the first source contact region. The first source contact region includes a heavily doped region 13 of the first doping type and a heavily doped region 23 of the second doping type.

A heavily doped region 13 of the first doping type is provided in the epitaxial layer 12 between the first source 61 and the trench 31 and between the first source 61 and the first channel 21. The heavily doped region 13 of the first doping type is in contact with the first source 61 and the first channel 21, respectively, and forms a conductive channel composed of the first source 61, the heavily doped region 13 of the first doping type, the first channel 21, and the drift region 30. The doping concentration of the heavily doped region 13 of the first doping type is typically at least an order of magnitude higher than the doping concentration of the other doped regions (e.g., the epitaxial layer 12) so that the resistance of the metal in contact with the semiconductor can be improved. When the heavily doped region 13 of the first doping type is connected to the first source 61 and the first channel 21, respectively, ohmic contact resistance between the first source 61 and the epitaxial layer 12 may be reduced by the heavily doped region 13 of the first doping type.

A heavily doped region 23 of the second doping type is in the epitaxial layer 12 and is located between the first source 61 and the first channel 21 and is not in contact with the trench 31, the heavily doped region 23 of the second doping type being in contact with the first source 61 and the first channel 21, respectively. The doping concentration of the heavily doped region 23 of the second doping type is typically at least an order of magnitude higher than the doping concentration of the other doped regions, such as the first channel 21. The contact between the first source 61 and the first channel 21 may be improved by the heavily doped region 23 of the second doping type.

The second MOS structure 20 is arranged in the longitudinal direction with the first MOS structure 10. Second MOS structure 20 includes a second gate 52, a second source 62, and a second channel 22. The second gate 52 is used as a control component for turning on the second MOS structure 20, and is used for controlling the second channel. The second gate 52 is used for controlling the second channel 22 to be turned on and off under the control of the control chip.

The second source 62 of the second MOS structure 20 is used as a terminal of the second MOS structure 20 and can be made of metal or metal-like material. When the second source electrode 62 is provided, the second source electrode 62 is disposed within the trench 31 and extends along the bottom of the trench 31 to outside the trench 31 to be exposed at the surface of the epitaxial layer 12. The second source 62 extends to the surface of the epitaxial layer 12 as a connecting surface for the second source 62.

The second channel 22 is a second doping type region. When forming the second channel 22, a doped region of the second doping type is provided in the epitaxial layer 12 below the bottom of the trench 31, forming the second channel 22. Since the second channel 22 is the second doping type region and the drift region 30 is the first doping type region, the drift region 30 and the second channel 22 may form a PN junction. When no voltage is applied to the second gate 52 or a voltage of 0 or a negative voltage is applied with respect to the second source 62, the PN junction between the second channel 22 and the drift region 30 is not turned on, so that the conduction path from the second source 62 to the second channel 22 to the drift region 30 is closed. Under the action of the voltage applied by the second gate 52, an inversion layer is formed in a portion of the second channel 22 near the bottom and sidewalls of the trench 31, which can be converted from the second doping type to the first doping type, so that the conduction path from the second source 62 to the second channel 22 to the drift region 30 is conducted. In combination with the first channel 21 in the first MOS structure 10 when conducting. When the first gate 51 controls the first channel 21 to be turned on and the second gate 52 controls the second channel 22 to be turned on, a conductive channel of the first source 61, the first channel 21, the drift region 30, the second channel 22 and the second source 62 is formed.

A second gate 52 is disposed within the trench 31 and opposite the second channel 22. Conduction of the second channel 22 may be controlled when a voltage is applied to the second gate 52.

As an optional solution, the second MOS structure 20 further includes a second gate oxide layer 43 isolating the second channel 22 from the second gate 52. The second gate oxide layer 43 is disposed on the sidewalls and bottom of the trench 31 and between the second gate 52 and the second channel 22. The second gate oxide layer 42 can suppress the leakage between the second channel 22 and the second gate 52 from increasing, and improve the gate withstand voltage.

As an alternative, a second source contact region (not shown) is further disposed in the epitaxial layer 12, and the second source 62 is connected to the second channel 22 through the second source contact region. The second source contact region comprises a heavily doped region 14 of the first doping type and a heavily doped region 24 of the second doping type.

A heavily doped region 14 of the first doping type is provided in the epitaxial layer 12 at the bottom of the trench 31 and on one side of the second source 62. The heavily doped region 14 of the first doping type is in contact with the second source 62 and the second channel 22, respectively, and forms a conductive channel composed of the second source 62, the heavily doped region 14 of the first doping type, the second channel 22, and the drift region 30. The heavily doped region 14 of the first doping type is typically doped at least an order of magnitude higher than other doped regions (e.g., the epitaxial layer 12) to improve the resistance of the metal to semiconductor junction. When the heavily doped region 14 of the first doping type is connected to the second source 62 and the second channel 22, respectively, the ohmic contact resistance between the second source 62 and the epitaxial layer 12 may be reduced by the heavily doped region 14 of the first doping type.

A heavily doped region 24 of the second doping type of the second source contact region is disposed below the bottom of the second source 62, the heavily doped region 24 of the second doping type being in contact with the second source 62 and the second channel 22, respectively. The doping concentration of the heavily doped region 24 of the second doping type is typically at least an order of magnitude higher than the doping concentration of the other doped regions, such as the second channel 22. The contact between the second source 62 and the second channel 22 may be improved by the heavily doped region 24 of the second doping type.

As an alternative, the trench 31 is filled with a filling layer 42 that wraps the first gate 51, the second gate 52 and the second source 62 to isolate and protect the above components. It should be understood that with fill layer 42, second source 62 is exposed outside the fill layer to facilitate connection to other circuitry.

Referring to fig. 3, it can be seen that, when the first MOS structure 10 and the second MOS structure 20 are specifically arranged, the first MOS structure 10 and the second MOS structure 20 are arranged in a longitudinal manner, so that the lateral size of the field effect transistor can be reduced. In addition, the first gate 51 and the second gate 52 are arranged longitudinally along the depth direction of the trench 31, so that the first MOS structure 10 and the second MOS structure 20 can share the longitudinally arranged drift region 30. In addition, the drift region 30 is located between the first channel 21 and the second channel 22, and does not occupy the lateral dimension of the power semiconductor device, so that the size of the power semiconductor device can be further reduced, and the arrangement density of the devices can be improved.

The structure of the second field effect transistor 101 is the same as that of the first field effect transistor 100, and the two first channels of the two common drain type metal oxide semiconductor field effect transistors are respectively arranged at two opposite sides of the trench; the two first source electrodes are arranged on two opposite sides of the groove respectively. As an alternative, in order to reduce the device arrangement, a part of components are shared between the first field effect transistor 100 and the second field effect transistor 101. As shown in fig. 3, the second source 62 is shared by the two field effect transistors. The second channels 22 of the two first field effect transistors 100 may communicate with each other, but are controlled independently by the two different second gates 52.

Referring to fig. 4, fig. 4 shows a top view of the power semiconductor device. As can be seen from fig. 3 and 4, the components of the power semiconductor device are arranged laterally, and adjacent first field effect transistor 100 and second field effect transistor 200 have mirror symmetry (along the center line of the trench). On the surface of the epitaxial layer 12, along the lateral direction, a first source 61, a heavily doped region 13 of the first doping type, a first gate oxide layer 41, a filling layer 42 and a second source 62 are sequentially distributed. Two adjacent field effect transistors form a unit cell in mirror symmetry. When the number of the unit cells is plural, the plural unit cells may be arranged periodically and repeatedly in the lateral direction.

Referring to fig. 5, fig. 5 shows a current schematic diagram of a power semiconductor device provided by an embodiment of the present application. The reference numerals in fig. 5 may refer to the same reference numerals in fig. 3. The first gate 51 and the second gate 52 are control ports of the power semiconductor device, the first source 61 is an output port of the power semiconductor device, and the second source 62 is an input port of the power semiconductor device. When a positive voltage is applied to the first gate 51 and the second gate 52, the levels of the first gate 51 and the second gate 52 are high with respect to the levels of the first source 61 and the second source 62, and both the first channel 21 and the second channel 22 are turned on. As shown by the dotted arrows in fig. 5, the current may flow along a first path, which is a path sequentially passing through the first source 61, the first channel 21, the drift region between the first channel 21 and the second channel 22, and the second source 62; alternatively, as shown by solid arrows in fig. 5, the current flows along a second path, which is a path passing through the second source 62, the second channel 22, the drift region between the first channel 21 and the second channel 22, the first channel 21, and the first source 61 in this order. When the first gate 51 is not applied with a positive voltage, the level of the first gate 51 is low with respect to the first source 61, and the first channel 21 is closed; when the second gate 52 is not applied with a positive voltage, the level of the second gate 52 is low with respect to the first source 61, and the second channel 22 is turned off.

As can be seen from the above description, in the power semiconductor device provided in the embodiment of the present application, the first MOS structure 10 and the second MOS structure 20 are structures sharing a drift region, and the two second doping type implanted body regions (the first channel 21 and the second channel 22) and the drift region of the middle first doping type may form a P-N-P common-cathode back-to-back diode, so that the first MOS structure 10 and the second MOS structure 20 constitute a common-drain mosfet, and a bidirectional withstand voltage can be achieved. The power semiconductor device provided by the embodiment of the application adopts a structural design that the longitudinal drift region and the two gates are vertically arranged up and down, so that the transverse occupied size of the field effect transistor is reduced. In addition, the first MOS structure 10 and the second MOS structure 20 adopt a shared longitudinal drift region, so that current does not pass through the substrate when flowing, and therefore the power semiconductor device has smaller channel resistance and no substrate resistance when being conducted, and the resistance of the power semiconductor device is reduced.

Referring to fig. 6, fig. 6 shows an application scenario schematic diagram of a power semiconductor device provided in an embodiment of the present application. The cathode of the battery 300 is connected to the load 300 through a battery management and charge protection circuit. The power semiconductor device provided in the embodiment of the present application is provided on a circuit as a structure for protecting the battery 300. The first field effect transistor 100 and the second field effect transistor 101 of the power semiconductor device are connected in parallel in a circuit, and the first MOS structure 10 and the second MOS structure 20 of the first field effect transistor 100 are connected in series. The first MOS structure 10 and the second MOS structure 20 are both controlled by the control chip 400. The control chip 400 controls the levels of the first gate and the second gate to control the on and off of the first MOS structure 10 and the second MOS structure 20.

In addition, the planar device structure (as shown in fig. 4) adopted by the power Semiconductor device provided in the embodiment of the present application, and the second MOS structure 20 may adopt a structural design of an LDMOS (Laterally Diffused Metal Oxide Semiconductor) to implement WLCSP (Wafer Level Chip Scale Packaging).

In order to verify the technical effect of the power semiconductor device provided by the embodiment of the present application, the power semiconductor device provided by the embodiment of the present application is simulated by using a semiconductor TCAD (Technology Computer aid Design).

Taking an N-type conductive common-drain field effect transistor with a bidirectional blocking voltage of 15V as an example, the field effect transistor is simulated, and the structure parameters of the field effect transistor are shown in table 1 and fig. 7: the lateral size of a single common drain type effect transistor is 1 bit 0.5um, namely the cell size of the power semiconductor device is 1um, and the concentration is 1.8e19cm^-3An N-type substrate with a thickness of 1um and a doping concentration of 1.3e17cm^-3And the N-type epitaxial layer with the thickness of 3um forms the body of the power semiconductor device. Trenches with the depth 12 and the half width 13 of 1um and 0.35um are formed on the surface of the field effect transistor body respectively. Forming a first P-type channel (first channel) with a potential well depth 4 of 0.28um and a potential well width 6 of 0.16um on the surface of the device body by P-type ion implantation with an implant dose of 1.35e13cm^-3. Forming an N-type heavily doped region with the depth 8 of 0.15um and the width 10 of 0.1um by N-type ion implantation and etching processes; and forming a P type heavily doped region with the depth 9 of 0.15um and the width 11 of 0.1um through P type ion implantation and etching processes. Forming a second P-type channel (second channel) with a potential well depth 5 of 0.45um, a potential well half width 13 of about 0.35um and a channel length 7 of 0.18um at the bottom of the trench by P-type ion implantation with an implant dose of 1.2e13cm^-3And 6e13cm^-3. The inner side wall of the groove is provided with a thickness (which is not marked in figure 7 and is positioned between G1/G2 and the side wall of the groove) of

A gate oxide layer of (a); filling polysilicon with the depth 14 of 0.35um, the width 16 of 0.18um, and the depth 15 of 0.18um and the width 10 of 0.18um to respectively form a gate G1 (first gate) and a gate G2 (second gate); the gate G1 and the gate G2 are isolated by a filling layer with the thickness 17 of 0.3 um. The threshold voltage of a power field effect transistor, i.e. a power semiconductor device, depends on the gate oxide thickness and the concentration of the P-channel. Breakdown voltage and on-state current of power field effect transistor, i.e. power semiconductor deviceThe resistance is determined by the concentration, depth and length of the N-type drift region, the concentration and length of the P-type channel region, the thickness of the oxide layer, the depth of the groove and other factors.

Table 1: parameters of field effect transistor structure

Reference numerals

Name of structure

Parameter value

Reference numerals

Structure name (Unit)

Parameter value

1

Field effect transistor size

0.5um

10

Width of N-type heavily doped region

0.1um

2

Thickness of N-type substrate

1um

11

Width of P-type heavily doped region

0.1um

3

Thickness of N-type epitaxial layer

3um

12

Depth of trench

1um

4

Depth of P-type first well region

0.28um

13

Width of groove

0.35um

5

Depth of the first P-type channel

0.45um

14

First gate depth

0.35um

6

Width of the first P-type channel

0.16um

15

Second gate depth

0.18um

7

Second P-type channel width

0.18um

16

Width of grid

0.18um

8

Depth of N-type heavily doped region

0.15um

17

Depth of filling layer

0.3um

9

Depth of P-type heavily doped region

0.15um

The power semiconductor devices in table 1 were simulated, and the simulation results are shown in fig. 8a and 8 b. Fig. 8a and 8b are graphs showing simulation graphs of breakdown voltage characteristics of devices. When the potentials of the first gate and the first source (source S1) are both low, the voltages of the second source and the second gate are gradually increased from 0V, and the current of the second source (source S2) is gradually read. When the second source current suddenly changes to 1uA/mm, the corresponding second source voltage is the breakdown voltage of the second MOS structure, i.e. the breakdown voltage from the second source to the first source, and as can be seen from fig. 8a, the breakdown voltage of the second MOS structure is 15V. Similarly, the breakdown voltage of the first MOS structure is the breakdown voltage from the first source to the second source, and as can be seen from fig. 8b, the breakdown voltage of the first MOS structure is 15V.

Fig. 9a and 9b are graphs showing simulation curves of transfer switching characteristics of the power semiconductor device. When the first source electrode is at low level and the second source electrode is connected with a fixed voltage of 0.1V, the first grid electrode and the second grid electrode are respectively and gradually increased from 0V and 0.1V, and the current of the second source electrode is gradually read. When the second source current is suddenly increased to 1uA/mm, the corresponding first gate voltage is the threshold voltage of the first MOS structure, as shown in fig. 9a, the threshold voltage simulation result of the first MOS structure is 0.8V. When the first source current is suddenly increased to 1uA/mm, the corresponding second gate voltage is the threshold voltage of the second MOS structure, as shown in fig. 9b, the threshold voltage simulation result of the second MOS structure is 0.8V.

As shown in fig. 9a and 9b, the characteristic on-resistance of the common drain power semiconductor device in the present example is only about 5m Ω · mm under the condition that the gate-source bias voltage of the power semiconductor device is 3.1V²。

Through the experimental verification, it can be seen that when the first MOS structure and the second MOS structure share the longitudinal drift region and the longitudinal distribution of the first gate and the second gate, the breakdown characteristic of the power semiconductor device provided by the embodiment of the application can meet 15V, and the unit on-resistance is only 5m Ω². The current power semiconductor device with two MOSFETs connected in series back to back and common drain has a characteristic on-resistance of 10.6m Ω · mm per unit area under a breakdown voltage of 12V²(FCAB 21490L-Gate resistor embedded Dual N-channel MOSFET lithium-ion semiconductor protection circuits available in 2016.) as a data source, therefore, the on-resistance per unit area of the power semiconductor device provided by the embodiment of the present application can be reduced by 53% compared with the on-resistance per unit area of the conventional power semiconductor device in the industry, and the breakdown voltage can be increased to 15V or more.

To facilitate understanding of the power semiconductor device provided in the embodiments of the present application, the following detailed description describes a manufacturing process of the power semiconductor device, taking the formation of a field effect transistor as an example, the manufacturing process may be manufactured based on a conventional discrete Trench MOS (discrete MOS) or integrated BCD (Bipolar CMOS DMOS), and the specific manufacturing method is as follows, with reference to the structure shown in fig. 3:

epitaxially growing an N-type doped epitaxial layer 12 with a certain doping concentration on an N-type substrate 11; trenches 31 are etched into epitaxial layer 12.

By ion implantation, a P-type doped region is formed in the epitaxial layer 12 below the bottom of the trench 31 to form the second channel 22, and a P-type doped region is formed in the epitaxial layer 12 outside the upper portion of the trench 31 to form the first channel 21.

A gate oxide layer is formed in the trench 31 by thermal oxidation growth, and the gate oxide layer covers the bottom and sidewalls of the trench 31.

Polysilicon is filled in the trench, and an etching process is performed to form a second gate 52, where the second gate 52 is opposite to the second channel 22, so as to control the conduction of the second channel 22. In addition, a portion of the gate oxide layer that isolates the second gate 52 from the second channel 22 is the second gate oxide layer 43.

A heavily doped region 13 of N type and a heavily doped region 14 of N type are formed in the epitaxial layer 12 by ion implantation. A filling layer 42 is deposited by chemical vapor deposition within the trench 31 and a CMP (chemical mechanical polishing) process is performed so that only the trench is filled with the oxide layer 42. Illustratively, the fill layer 42 may be an oxide layer.

And etching to remove part of the filling layer 42, wherein the surface of the filling layer left by etching is the surface for bearing the first gate 51. During the etching of the filling layer 42, part of the gate oxide layer is etched away.

A gate oxide layer, which is the first gate oxide layer 41, is regrown on the sidewalls of the trench 31 by thermal oxidation growth. The thickness of the first gate oxide layer 41 is substantially the same as the thickness of the second gate oxide layer 43. The first gate oxide 41 is disposed on the sidewall of the trench 13 for isolating the first gate 51 from the first trench 21.

Polysilicon is deposited on the filling layer remaining after the etching, and the first gate 51 is formed by an etching process. And continuously depositing a filling layer in the groove by means of chemical vapor deposition and etching.

Removing the filling layer above the ohmic contact region in the trench by an etching mode, and forming a P-type heavily doped region 23 and a P-type heavily doped region 24 on the surface of the epitaxial layer 12 and the ohmic contact region at the bottom of the trench 31 respectively by an ion implantation mode; finally, metal is deposited to form a first source electrode 61 and a second source electrode 62.

Forming a P-type heavily doped region 23 at the ohmic contact region on the surface of the epitaxial layer 12 by means of ion implantation; finally, metal is deposited to form the first source electrode 61.

As shown in fig. 10, fig. 10 is a schematic structural diagram of another power semiconductor device provided in an embodiment of the present application. The power semiconductor device shown in fig. 10 is similar in structure to the power semiconductor device shown in fig. 3 only in that there is a difference in arrangement of the internal structure of the device.

In fig. 10, some reference numerals refer to the same reference numerals in fig. 3, and are not repeated herein. The trenches shown in fig. 10 are T-shaped trenches including a first trench 32 and a second trench 33. Wherein, the second gate 52 is disposed at the bottom of the T-shaped trench (the bottom of the second trench 33); the first gate electrode 51 is provided on the step surface of the T-shaped trench (the bottom of the first trench 32).

As can be seen from fig. 10, the first gate 51 and the second gate 52 are arranged in a staggered manner along the depth direction of the trench, and compared with the power semiconductor device shown in fig. 3, the first gate 51 can be directly arranged at the bottom of the first trench 32, so that the first gate 51 is convenient to position during arrangement, and the accuracy of the arrangement of the first gate 51 is improved. In addition, when the trench shown in fig. 10 is used, when the gate oxide layer is prepared, the first gate 51 and the second gate 52 can be formed at the same time by polysilicon etching once, which simplifies the process during preparation.

Referring to fig. 11, fig. 11 shows a top view of the power semiconductor device. As can be seen from fig. 10 and 11, the plurality of components of the power semiconductor device are arranged laterally, and the adjacent first field effect transistors 100 and the second field effect transistors 101 are in mirror symmetry (along the central line of the trench). On the surface of the epitaxial layer 12, along the lateral direction, a first source 61, a heavily doped region 13 of the first doping type, a first gate oxide layer 41, a filling layer 42 and a second source 62 are sequentially distributed. Two adjacent field effect transistors form a unit cell in mirror symmetry. When the number of the unit cells is plural, the plural unit cells may be arranged periodically and repeatedly in the lateral direction.

Referring to fig. 12, fig. 12 shows a current schematic diagram of a power semiconductor device provided by an embodiment of the present application. The first gate 51 and the second gate 52 are control ports of the power semiconductor device, the first source 61 is an input port of the power semiconductor device, and the second source 62 is an output port of the power semiconductor device. When a voltage is applied to the first gate 51 and the second gate 52, the levels of the first gate 51 and the second gate 52 are high with respect to the levels of the first source 61 and the second source 62, and both the first channel 21 and the second channel 22 are turned on. As shown by the dotted arrow in fig. 5, the current may flow along a first path, where the first path refers to a path that sequentially passes through the first source 61, the first channel 21, the drift region between the first channel 21 and the second channel 22, and the second source 62; alternatively, as shown by solid arrows in fig. 5, the current flows along a second path, which is a path passing through the second source 62, the second channel 22, the drift region between the first channel 21 and the second channel 22, the first channel 21, and the first source 61 in this order. When the first gate 51 is not applied with a positive voltage, the level of the first gate 51 is low with respect to the first source 61, and the first channel 21 is closed; when the second gate 52 is not applied with a positive voltage, the level of the second gate 52 is low with respect to the first source 61, and the second channel 22 is turned off.

In order to verify the technical effect of the present invention, the device structure and performance parameters of the embodiment of the present invention are simulated by using a semiconductor TCAD, and the structure parameters of the field effect transistor are shown in table 2 and fig. 13: at a concentration of 1.8e19cm^-3Is provided with a doping concentration of 1.3e17cm^-3And the N-type epitaxial layer with the thickness of 3um forms a device body. First grooves with the depth and the width of 0.6um and 0.55um are formed on the surface of the device body respectively. And further etching the bottom of the first groove to form second grooves with the depth and the width of 0.3um and 0.35um respectively. Forming a first P-type channel (first channel) with a potential well depth of 0.28um and a channel length of 14um on the surface of the device body by P-type ion implantation with an implantation dosage of 1.35e13cm^-3(ii) a Forming a heavily doped region of a first doping type with the depth of 0.15um and the width of 0.1um by N-type ion implantation; and forming a second doping type heavily doped region with the depth of 0.15um and the width of 0.1um by P-type ion implantation. A second P-type channel (second channel) having a potential well depth of 0.55um and a channel length of 0.21um is formed at the bottom of the second trench by P-type ion implantation. The first groove and the second groove are internally provided with a thickness of

A gate oxide layer. The first gate (gate G1) and the second gate (gate G2) are respectively formed by filling polysilicon with the depth of 0.4um and the width of 0.18um and the depth of 0.2um and the width of 0.18 um. The threshold voltage of the power semiconductor device depends on the thickness of the gate oxide layer and the concentration of the P-well region. The breakdown voltage and the on-resistance of the device are respectively determined by the concentration, the depth and the length of the N-type drift region, the concentration and the length of the P-type channel region, the thickness of an oxide layer, the depth of a groove and other factors.

Table 2: parameters of field effect transistor structure

The power semiconductor devices in table 2 were simulated, and the simulation results are shown in fig. 14a and 14 b. Fig. 14a and 14b are graphs showing breakdown voltage simulation of the power semiconductor device. When the potentials of the first gate and the first source (source S1) are both low, the voltages of the second source and the second gate are gradually increased from 0V, and the current of the second source (source S2) is gradually read. When the second source current suddenly changes to 1uA/mm, the corresponding second source voltage is the breakdown voltage of the second MOS structure, i.e., the breakdown voltage from the second source to the first source, and as can be seen from fig. 14a, the breakdown voltage of the second MOS structure is 15V. Similarly, the breakdown voltage of the first MOS structure is the breakdown voltage from the first source to the second source, and as can be seen from fig. 14b, the breakdown voltage of the first MOS structure is 15V.

Fig. 15a and 15b are graphs showing simulation curves of transfer characteristics of the power semiconductor device. When the first source electrode is at low level and the second source electrode is connected with a fixed voltage of 0.1V, the first grid electrode and the second grid electrode are respectively and gradually increased from 0V and 0.1V, and the current of the second source electrode is gradually read. When the second source current is suddenly increased to 1uA/mm, the corresponding first gate voltage is the threshold voltage of the first MOS structure, as shown in fig. 15a, the threshold voltage simulation result of the first MOS structure is 0.9V. When the second source current is suddenly increased to 1uA/mm, the corresponding second gate voltage is the threshold voltage of the second MOS structure, as shown in fig. 15b, the threshold voltage simulation result of the second MOS structure is 0.9V.

In addition, under the conditions that the breakdown voltage of the power semiconductor device is 15V and the gate-source bias voltage is 3.1V, the characteristic on-resistances of the first MOS structure and the second MOS structure in the embodiment of the present application are only about 7m Ω · mm²。

Through the experimental verification, it can be seen that when the power semiconductor device provided by the embodiment of the application adopts the two MOS structures to share the longitudinal drift region, the first gate and the second gate are distributed in a vertically staggered manner, and the transverse groove structure, the unit on-resistance is 7m Ω². The current power semiconductor device with two MOS structures connected in series by back-to-back common-drain has a specific on-resistance of 10.6m Ω · mm per unit area under the condition of a breakdown voltage of 12V²(FCAB 21490L-Gate resistor embedded Dual N-channel MOSFET lithium-ion semiconductor protection circuits available in 2016.) as a data source, therefore, the on-resistance per unit area of the power semiconductor device provided by the embodiment of the present application can be reduced by 33% compared with the on-resistance per unit area of the conventional power semiconductor device in the industry, and the breakdown voltage can be increased to 15V or more. In addition, the first grid and the second grid are arranged in a staggered mode, so that the preparation process can be simplified, and the production efficiency can be improved.

The embodiment of the application further provides an electronic device, such as a notebook computer, a mobile phone, a wearable device, a tablet computer and other electronic devices. The electronic device includes a battery and an output circuit connected to the battery, the output circuit including any one of the power semiconductor devices described above. In the technical scheme, the first grid and the second grid are longitudinally arranged along the depth direction of the groove, so that the size occupied by the common-drain metal oxide semiconductor field effect transistor in the transverse direction is reduced, in addition, the first metal oxide semiconductor structure and the second metal oxide semiconductor structure share the drift region, the resistance of the drift region is reduced, and the two same common-drain metal oxide semiconductor field effect transistors are symmetrically connected in parallel back to back, so that the resistance of the power semiconductor device is half of that of the power semiconductor device adopting a single common-drain metal oxide semiconductor, and the characteristic on-resistance of the power semiconductor device in unit area is further reduced.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. The power semiconductor device is characterized by comprising a first doping type epitaxial layer and two common-drain type metal oxide semiconductor field effect transistors; the first doping type epitaxial layer is provided with a groove;

each common-drain type metal oxide semiconductor field effect transistor comprises a first metal oxide semiconductor structure and a second metal oxide semiconductor structure which are arranged along the depth direction of the groove;

the first metal oxide semiconductor structure includes: the first channel is arranged in the first doping type epitaxial layer, and the first source electrode is connected with the first channel; the first source electrode and the first channel are positioned on the same side of the groove, and the first source electrode is connected with the first channel; the first channel is a second doping type area arranged in the first doping type epitaxial layer;

the first metal oxide semiconductor structure further comprises a first grid electrode which is arranged in the groove and used for controlling the conduction of the first channel;

the second metal oxide semiconductor structure comprises a second source electrode and a second channel, the second source electrode is positioned at the bottom of the groove, and the second channel is positioned in the first doping type epitaxial layer and is connected with the second channel; the second channel is a second doping type area arranged in the first doping type epitaxial layer;

the second metal oxide semiconductor structure further comprises a second grid electrode which is arranged in the groove and used for controlling the conduction of the second channel;

the first channels and the second channels are arranged at intervals along the depth direction of the grooves; the second grid and the first grid are arranged at intervals along the depth direction of the groove;

when the first grid and the second grid respectively control the conduction of the first channel and the second channel, current flows along the arrangement direction or the opposite direction of the first source electrode, the first channel, part of the first doping type epitaxial layer among the first channel and the second channel, the second channel and the second source electrode;

the second sources of the two common-drain type metal oxide semiconductor field effect transistors are shared, and two first channels of the two common-drain type metal oxide semiconductor field effect transistors are respectively arranged on two opposite sides of the groove; the two first source electrodes are arranged on two opposite sides of the groove in a splitting mode.

2. The power semiconductor device of claim 1, wherein each common-drain mosfet further comprises:

a first gate oxide layer isolating the first channel from the first gate;

a second gate oxide layer isolating the second channel from the second gate.

3. The power semiconductor device of claim 2, wherein the first and second gate oxide layers are disposed on sidewalls of the trench.

4. The power semiconductor device according to claim 3, wherein the trench is filled with a filling layer that wraps the first gate, the second gate and the second source.

5. The power semiconductor device according to any one of claims 1 to 4, wherein a first source contact region is provided within the first doping type epitaxial layer, and the first channel is connected to the first source through the first source contact region.

6. The power semiconductor device of claim 5, wherein the first source contact region comprises a heavily doped region of a first doping type and a heavily doped region of a second doping type.

7. The power semiconductor device according to any one of claims 1 to 6, wherein a second source contact region is provided in the first doping type epitaxial layer, and the second channel is connected to the second source through the second source contact region.

8. The power semiconductor device of claim 7, wherein the second source contact region comprises a heavily doped region of a first doping type and a heavily doped region of a second doping type.

9. The power semiconductor device according to any one of claims 1 to 8, wherein the trench is a straight trench; the first grid and the second grid are longitudinally arranged along the depth direction of the groove.

10. The power semiconductor device according to any one of claims 1 to 8, wherein the first gate and the second gate are arranged to be shifted in a depth direction of the trench.

11. The power semiconductor device of claim 10, wherein the trench is a T-shaped trench; the second grid electrode is arranged at the bottom of the T-shaped groove; the first grid is arranged on the step surface of the T-shaped groove.

12. An electronic device comprising a battery and an output circuit connected to the battery, the output circuit comprising the power semiconductor device according to any one of claims 1 to 11.