CN114582794A - 用于在通用衬底上的装置集成的植入式隔离 - Google Patents

用于在通用衬底上的装置集成的植入式隔离 Download PDF

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CN114582794A
CN114582794A CN202111160020.1A CN202111160020A CN114582794A CN 114582794 A CN114582794 A CN 114582794A CN 202111160020 A CN202111160020 A CN 202111160020A CN 114582794 A CN114582794 A CN 114582794A
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semiconductor substrate
layer
region
device region
polycrystalline
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西瓦·P·阿度苏米利
M·莱维
黄正铉
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GlobalFoundries US Inc
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Abstract

本申请涉及用于在通用衬底上的装置集成的植入式隔离，揭示了包括集成在半导体衬底上的诸如晶体管的装置的结构，以及形成包括集成在半导体衬底上的诸如晶体管的装置的结构的方法。第一晶体管形成在半导体衬底的第一装置区中，以及第二晶体管形成在半导体衬底的第二装置区中。第二晶体管包括在半导体衬底上的层堆栈，且层堆栈包括由III‑V族化合物半导体材料构成的层。多晶层包括位于第一装置区下方的半导体衬底中的区段。

Description

用于在通用衬底上的装置集成的植入式隔离
技术领域
本发明涉及半导体装置制造和集成电路，更具体地，涉及包括集成在半导体衬底上的装置(例如晶体管)的结构以及形成这种结构的方法。
背景技术
高压电力电子装置，例如高电子迁移率晶体管，可以使用III-V族化合物半导体制造以利用它们的材料特性，例如大于硅的载流子迁移率的载流子迁移率。III-V族化合物半导体包括III族元素(铝、镓、铟)和V族元素(氮、磷、砷、锑)。高电子迁移率晶体管可以包括具有不同带隙的结晶III-V族化合物半导体材料之间的异质结，例如二元氮化镓和三元铝-镓氮化物之间的异质结。在操作过程中，二维电子气体在异质结的界面附近形成，并定义高电子迁移率晶体管的沟道。
高电子迁移率晶体管与场效应晶体管或通过互补性金属氧化半导体(CMOS)处理在同一芯片上形成的异质结双极晶体管的集成已被证明是一个复杂的过程，因为，例如，需要电气隔离不同的装置。集成可以通过晶圆接合或通过使用工程或混合衬底来实现，这在本质上替将高电子迁移率晶体管与这些其他类型的晶体管集成的过程带来显着的复杂性。
需要改进的结构，包括集成在半导体衬底上的装置，例如晶体管，以及形成这种结构的方法。
发明内容
在本发明的一个实施例中，一种结构包括具有第一和第二装置区的半导体衬底、在所述第一装置区中的第一晶体管和在所述第二装置区中的第二晶体管。所述第二晶体管包括在所述半导体衬底上的层堆栈，且所述层堆栈包括由III-V族化合物半导体材料构成的层。所述结构还包括多晶层，所述多晶层具有位于所述第一装置区下方的所述半导体衬底中的区段。
在本发明的一个实施例中，一种方法包括形成具有位于半导体衬底的第一装置区下方的区段的多晶层，在所述半导体衬底的所述第一装置区中形成第一晶体管，形成包括在所述半导体衬底的第二装置区中由III-V族化合物半导体材料构成的层的层堆栈，且使用所述层堆栈形成第二晶体管。
附图说明
包含在本说明书中并构成本说明书一部分的附图示出本发明的各种实施例，且与上面给出的本发明的一般描述和下面给出的实施例的详细描述一起用于解释本发明的实施例。在附图中，相同的附图标记表示不同视图中的相同特征。
图1至图3是在根据本发明的实施例的处理方法的连续制造阶段的结构的截面图。
图3A是根据本发明的实施例的图3的一部分的放大截面图。
图4至图6是在图3之后的处理方法的连续制造阶段的结构的截面图。
图6A是根据本发明的实施例的图6的一部分的放大截面图。
图7至图8是在图6之后的处理方法的连续制造阶段的结构的截面图。
图8A是根据本发明的实施例的图8的一部分的放大剖视图。
图9和图10是根据本发明的替代实施例的结构的截面图。
具体实施方式
参考图1并根据本发明的实施例，提供包含单晶半导体材料(例如单晶硅)的半导体衬底10。半导体衬底10具有可以是平面的顶面12。半导体衬底10可以是包含单晶半导体材料(例如，单晶硅)的块体衬底(bulk substrate)。在一个实施例中，半导体衬底10的单晶半导体材料可以具有金刚石(diamond)晶格结构，其具有由米勒指数(Miller indice)指定的<111>晶向。在一个实施例中，半导体衬底10可以包含具有具有<111>晶向的金刚石晶格结构的单晶硅。对于具有<111>晶向的半导体衬底10，(111)晶面平行于半导体衬底10的顶面12，且[111]晶向垂直于(111)面。(100)晶轴不位于顶面12的平面中。半导体衬底10可以表征为非绝缘体上硅衬底(即，非SOI衬底)，非绝缘体上硅衬底缺少绝缘体上硅(SOI)衬底的埋入式氧化物层特性。在一个实施例中，半导体衬底10可以完全由具有<111>晶体取向的半导体材料构成。
形成从半导体衬底10的顶面12延伸到半导体衬底10中的浅沟槽隔离区14。浅沟槽隔离区14可以包含通过化学气相沉积沉积到在半导体衬底10中蚀刻、抛光和脱釉的沟槽中的介电材料。浅沟槽隔离区14中包含的介电材料可以包括二氧化硅、氮化硅、碳化硅、富硅二氧化硅，或这些材料中的两种或更多种的组合。浅沟槽隔离区14可以相对于顶面12延伸到半导体衬底10中的深度d1。浅沟槽隔离区14围绕并限定多个装置区16、18、20，且浅沟槽隔离区14横向位于不同的装置区16、18、20之间。在一个实施例中，装置区18中的顶面12可以与装置区16中的顶面12共面，也可以与装置区20中的顶面12共面。
可由氮化硅构成的焊垫层21位于所有装置区16、18、20中的顶面12上。焊垫层21可以是用于图案化其中形成浅沟槽隔离区14的沟槽的硬掩模的残余物。在常规工艺流程中，在形成浅沟槽隔离区14之后去除焊垫层21。
参考图2，其中相似的附图标记指代与图1中相似的特征，并在处理方法的后续制造阶段，在装置区18中的半导体衬底10中形成沟槽30。为此，将焊垫层21通过光刻和蚀刻工艺图案化并从装置区18去除以限定通常位于装置区18上方的开口，使得暴露装置区18中的半导体衬底10的顶面12。
通过蚀刻工艺例如反应离子蚀刻工艺在半导体衬底10中的焊垫层21中的开口位置处形成沟槽30。沟槽30可以延伸到与半导体衬底10的表面共同延伸的沟槽底部32且可以具有侧表面或侧壁29、31。半导体衬底10的部分布置在沟槽30和相邻的浅沟槽隔离区14之间。沟槽底部的表面32可以位于半导体衬底10中相对于顶表面12的深度d2，所述深度d2大于浅沟槽隔离区14的深度d1。焊垫层21，任选地用于图案化沟槽30的光致抗蚀剂，在蚀刻工艺期间保护装置区16和装置区20中的半导体衬底10。在一个实施例中，沟槽底部的表面32可以是平面的且没有形貌。在一个实施例中，顶面12可以是平面，沟槽底部的表面32可以是平面，顶面12和表面32的平面可以平行。
与沟槽30的侧壁29、31相邻地形成侧壁间隔物34。侧壁间隔物34可以从半导体衬底10的顶面12延伸到沟槽30底部的表面32。可以通过沉积由介电材料(例如氮化硅)构成的衬垫层并利用各向异性蚀刻工艺例如反应离子蚀刻工艺蚀刻沉积的衬垫层来形成侧壁间隔物34。
参考图3、图3A，其中相同的附图标记指代图2中的相同特征，且在处理方法的后续制造阶段，在位于沟槽30内部的半导体衬底10的表面32上形成包含一个或多个化合物半导体层的层堆栈36。在一个实施例中，层堆栈36可以包括至少一个由III-V族化合物半导体材料构成的结晶层。在一个实施例中，层堆栈36可以包括由二元III-V族化合物半导体材料构成的至少一个结晶层。在一个实施例中，层堆栈36可以包括至少一个由三元III-V族化合物半导体材料构成的结晶层。在一个实施例中，层堆栈36可以包括由不同III-V族化合物半导体材料构成的多个结晶层。在一个实施例中，层堆栈36可以包括由二元III-V族化合物半导体材料构成的至少一个结晶层和由三元III-V族化合物半导体材料构成的至少一个结晶层。在一个实施例中，层堆栈36可以包括一个或多个包含镓和氮的结晶层。在一个实施例中，层堆栈36可以包括一个或多个结晶层，所述结晶层包含氮化镓或基于氮化镓的三元III-V族化合物半导体材料(例如，氮化铝镓)。
可以通过外延生长工艺形成层堆栈36。层堆栈36的每个单独层可以具有单晶的晶体结构，或替代地为具有不同水平的结晶缺陷度的实质上单晶的晶体结构。通过比具有<100>晶体取向的衬底更接近的晶格匹配，半导体衬底10的半导体材料(例如，单晶硅)的<111>晶向促进具有低晶体缺陷度的层堆栈36的III-V族化合物半导体材料(例如氮化镓)的外延生长。特别地，具有<111>晶向的半导体衬底10的表面上的原子排列成六边形，其可以与层堆栈36中的一种或多种化合物半导体材料(例如，基于二元六方密堆积晶体系统的氮化镓的纤锌矿晶体结构)的晶体结构相当良好地晶格匹配。
在一个实施例中，可以通过选择性外延生长工艺形成层堆栈36，其中半导体材料不在电介质表面上形成，例如硬掩模26和侧壁间隔物34。在一个实施例中，层堆栈36可以通过非选择性外延生长工艺形成，其中通过光刻和蚀刻工艺沉积和图案化半导体材料。在一个实施例中，层堆栈36的侧壁37可以位于与沟槽侧壁29、31相邻并间隔开的位置，且在那种情况下，沟槽30可以实质上被层堆栈36填充。在代表性实施例中，层堆栈36具有远离沟槽侧壁29、31向内倾斜以限定例如梯形形状并将侧壁37与沟槽侧壁29、31隔开的侧壁37。侧壁37可以在层堆栈36的顶面35会聚。在一个实施例中，顶面35可以与半导体衬底10的顶面12共面或实质上共面。隔离区(未示出)可以通过例如氮或氩的掩模植入形成在层堆栈36的顶面35。
在一个实施例中且如图3A中最佳所示，层堆栈36可以包括缓冲层76、沟道层78、间隔物层80和阻挡层82。可以使用诸如金属有机化学气相沉积的外延生长工艺连续形成层76、78、80、82。层76、78、80、82可以各自具有单晶的晶体结构，或替代地为具有不同水平的结晶缺陷度的实质上单晶的晶体结构。层76、78、80、82中的一层或多层可包括特征在于不同组成或掺杂的多个子层。缓冲层76可以包含III-V族化合物半导体材料，例如氮化镓，其在材料成分、掺杂和/或层厚度方面被定制以适应半导体衬底10的材料和沟道层78的材料之间的晶格失配。设置在缓冲层76上方的沟道层78可以包含III-V族化合物半导体材料，例如氮化镓。间隔物层80和阻挡层82设置在沟道层78上方，间隔物层80在沟道层78和阻挡层82之间。可以比沟道层78薄的间隔物层80可以包含III-V族化合物半导体，例如氮化铝。阻挡层82可包含III-V族化合物半导体，例如氮化铝镓、氮化铝或氮化铝铟，其提供与不同成分的沟道层78的异质界面。间隔物层80和阻挡层82，连同沟道层78的材料特性，有助于在装置操作期间在充满高迁移率和丰富电子的异质界面产生二维电子气体。
参考图4，其中相同的附图标记指代图3中的相同特征且在处理方法的后续制造阶段，通过利用光刻和蚀刻工艺进行图案化，从装置区16和装置区20去除焊垫层21。图案化后的焊垫层21的一部分保留在沟槽30的侧壁29和相邻的浅沟槽隔离区14之间的顶面12上的装置区18中，且图案化后的焊垫层21的另一部分保留在沟槽30的侧壁31与相邻的浅沟槽隔离区14之间的顶面12上的装置区18中。
在装置区18中铺设植入掩模22，所述植入掩模22包括位于层堆栈36中央上方的部分和填充层堆栈36与沟槽30的侧壁29、31之间的间隙的部分。植入掩模22包括暴露层堆栈36的顶面的部分并由此确定可用于植入的区域的开口。在装置区16和装置区20中也不存在植入掩模22。植入掩模22可以包括通过旋涂工艺铺设、预烘烤、暴露于通过光掩模投射的光、曝光后烘烤、并用化学显影剂显影以定义布置在要植入的区域上的开口和在不要植入的区域上的形状。
参考图5，其中相同的附图标记指代图4中的相同特征且在处理方法的后续制造阶段，在整个装置区16和装置区20中，在半导体衬底10的顶面12下方的半导体衬底10中形成包含损坏或非晶半导体材料的植入层38。在装置区18中，植入层38也形成在沟槽30的侧壁29、31和各自的相邻浅沟槽隔离区14之间的半导体衬底10的部分中。植入区40形成在层堆栈36中，其位置由植入掩模22限定。
植入层38和植入区40可以通过离子植入工艺同时形成，所述离子植入工艺引入具有离子轨迹的高能离子，所述高能离子撞击顶面12并在半导体衬底10和层堆栈36内的路径中行进。高能离子通过与原子核和电子在穿越的半导体材料中的随机散射事件沿其路径损失能量，并在其能量耗散后最终停止。核碰撞中损失的能量将半导体衬底10和层堆栈36的目标原子从它们的原始晶格位置移开，这会损坏它们各自的晶格结构。与位于植入层38的下边界15和层堆栈36的非植入层下方的半导体衬底10的半导体材料的未损坏区域24相比，半导体衬底10的晶格结构在植入层38内被损坏或非晶化。在一个实施例中，半导体衬底10中的植入层38可以从下边界15延伸到顶面12。在一个实施例中，下边界15可以是平面的。在替代实施例中，下边界15可以在焊垫层21下方较浅，其作用是在植入期间局部增加材料厚度并减小焊垫层21下方的半导体衬底10的部分中的离子范围。
层堆栈36中的植入区40延伸到层堆栈36内的浅深度且可以位于与侧壁37相邻的位置。在一个实施例中，植入区40在层堆栈36中延伸穿过沟道层78和阻挡层82之间的界面以在使用期间限定层堆栈36中用于二维电子气体的区域的边界。
离子可以由合适的源气体产生，且可以使用离子植入工具在一个或多个植入条件下植入到半导体衬底10和层堆栈36中。可选择用于离子植入工艺的植入条件(例如，离子种类、剂量、能量)以调整植入层38和植入区40的特性。在一个实施例中，离子可以由惰性气体产生，例如氩气或氙气。在一个实施例中，氩离子的剂量可以大于或等于1x1014离子/cm2。在一个实施例中，氩离子的剂量范围可以从大约1x1014离子/cm2到大约5x1015离子/cm2。在一个实施例中，氩离子的能量可以在从大约30keV到大约1000keV的范围内。其他植入的惰性气体离子种类的剂量和能量可以与氩的剂量和能量相似或不同。离子植入条件可以包括单次植入、以不同能量执行的多次植入、分段植入等。
参考图6、图6A，其中相同的附图标记指代图5中的相同特征，且在处理方法的后续制造阶段，去除剩余的焊垫层21和植入掩模22。可以沉积和图案化介电层42以覆盖装置区18中的层堆栈36。在图案化期间从装置区16和装置区20去除介电层42，使得半导体衬底10的顶面12在装置区16、20中暴露。介电层42由介电材料构成，例如二氧化硅。
通过执行热处理(即，退火工艺)，植入层38中的受损半导体材料被转化为半导体衬底10中的多晶层44和多晶区46。在一个实施例中，用于热处理半导体衬底10的植入层38和形成多晶层44和多晶区46的热处理可以是快速热退火。在一个实施例中，可以使用例如将半导体衬底10加热到900℃至1125℃范围内的峰值温度的闪光灯组来执行快速热退火，并在峰值温度下停留时间30毫秒至5秒，且在特定实施例中，峰值温度可以保持在1000℃，停留时间小于或等于1秒。
多晶层44和多晶区46包含多晶半导体材料(例如，多晶硅)的晶粒。除了多晶晶粒之外，多晶层44和多晶区46还可以包含缺陷作为残余损伤，且缺陷可包含被植入种类(例如，氩或氙)的俘获原子。在装置区16和装置区20中，热处理还将多晶层44和顶面12之间的植入层38的受损半导体材料再结晶成半导体衬底10的层48，所述层48包括再结晶的半导体材料(例如，再结晶的单晶硅)。在装置区16中，由于介电层42的存在，植入层38的受损半导体材料不会再结晶，且在热处理之后，多晶区46可以延伸到顶面12。与多晶层44和多晶区46相反，层48中的再结晶单晶半导体材料没有多晶晶粒和缺陷，也可能没有植入种类的原子。
多晶区46与沟槽30相邻，更具体地，与沟槽30的侧壁29、31相邻。多晶层44包括装置区16中的区段和装置区20中的区段，但不存在于沟槽30下方的装置区18中。装置区16中的多晶层44区段在装置区16其间的浅沟槽隔离区14下方延伸以连接到装置区18中的其中一个多晶区46。类似地，装置区20中的多晶层44的区段在装置区20其间的浅沟槽隔离区14下方延伸以连接到装置区18中的另一个多晶区46。在每种情况下，各自的多晶区46从顶面12延伸以连接到多晶层44的区段中的一个或另一个。在一个实施例中，多晶层44的区段可以在装置区16和20中的每一个的整体下方相对于顶面12横向延伸。例如，装置区16中的多晶层44的区段可以相对于围绕装置区16的浅沟槽隔离区14之间的顶面12横向延伸并接触这些浅沟槽隔离区14，且装置区20中的多晶层44的区段可以相对于围绕装置区20的浅沟槽隔离区14之间的顶面12横向延伸并接触这些浅沟槽隔离区14。
再结晶的单晶层48位于在装置区16和装置区20中的多晶层44的上边界43和半导体衬底10的顶面12之间。半导体衬底10还包括多晶层44和多晶区46的下边界47之下的未损坏区24中的单晶半导体材料。结果，多晶层44被埋入在装置区16和装置区20中的顶面12下方，且嵌入在半导体衬底10的单晶半导体材料中。
多晶层44和多晶区46可以表征为具有大于或等于半导体衬底10的单晶半导体材料的电阻率的电阻率的富陷阱材料(trap-rich material)。在一个实施例中，多晶层44和多晶区46可以具有大于或等于1,000ohm-cm的电阻率。在一个实施例中，多晶层44的电阻率和多晶区46的电阻率可以在约10,000ohm-cm至约1,000,000ohm-cm的范围内。
装置区18中的多晶区46在层堆栈36和装置区16之间以及层堆栈36和装置区20之间提供增强的电隔离。多晶区46可以与相邻的浅沟槽隔离区14共同扩展。
在一个实施例中，层堆栈36中的植入区40可以通过热处理再结晶成隔离区41，隔离区41包括单晶或实质上单晶的半导体材料，所述半导体材料含有植入离子种类的原子浓度。植入离子种类的原子浓度将层堆栈36的半导体材料转化为电绝缘体。隔离区40可以比多晶层44的深度更浅的深度延伸到叠层36中。
参考图7，其中相同的附图标记指代图6中的相同特征，且在处理方法的后续制造阶段，场效应晶体管50可以通过互补金属氧化物(CMOS)处理来制造而在半导体衬底10的装置区16中形成装置结构。场效应晶体管50可以包括栅极电极52、栅极电介质53、源极/漏极区54和栅极电极52下方的沟道区。栅极电极52和栅极电介质53形成在半导体衬底10的顶面12上。场效应晶体管50的源极/漏极区54和沟道区包含半导体衬底10的单晶半导体材料的各自部分。源极/漏极区54至少部分地位于顶面12下方，而沟道区位于顶面12下方，通常位于源极/漏极区54之间。
双极结晶体管56可以制造为半导体衬底10的装置区20中的装置结构。双极结晶体管56可以包括多个端子，其形式为限定在半导体衬底10中的集电极58、发射极60和布置在集电极58和发射极60之间的基极层62。基极层62可以包含外延生长在半导体衬底10的顶面12上的单晶半导体材料(例如，硅-锗)。在一个实施例中，集电极58和发射极60可以包含n型半导体材料，且基极层62可以包含p型半导体材料以限定NPN双极结晶体管。
场效应晶体管50和双极结晶体管56构成不同类型或分类的晶体管结构。场效应晶体管50和双极结晶体管56之间的区别在于场效应晶体管50中只有多数载流子流动，而双极结晶体管56中多数载流子和少数载流子都流动。场效应晶体管50和双极结晶体管56在它们各自的构造中不包括任何碳化硅层，因此不含碳化硅。场效应晶体管50和双极结晶体管56都形成在半导体材料上，其特征在于与用于形成层堆栈36的半导体材料具有相同的<111>晶体取向。
参考图8、图8A，其中相同的附图标记指代图7中的相同特征，且在处理方法的后续制造阶段，通过蚀刻工艺从装置区18部分地去除介电层42。部分介电层42保留在层堆栈36的侧壁37和侧壁间隔物34之间的空间中的沟槽30内。在所有装置区16、18、20上形成一个或多个介电层65。一个或多个介电层65被图案化以在装置区18中限定暴露层堆栈36的开口。
晶体管64使用层堆栈36形成为装置区18中的装置结构。晶体管64包括栅极电极66、源极区68和漏极区69，它们可以形成在设置在层堆栈36的顶表面上的介电层中。栅极电极66、源极区68和漏极区69可以由金属构成，例如金属氮化物。来自源极区68和漏极区69的金属原子可以扩散到层堆栈36中。
晶体管64不是通过CMOS工艺形成的，因此可以被认为是非CMOS晶体管。在一个实施例中，晶体管64可以是高电子迁移率晶体管(HEMT)。在一个实施例中，晶体管64可以是金属-绝缘体-半导体高电子迁移率晶体管(MISHEMT)。在一个实施例中，晶体管64可以是金属氧化物半导体高电子迁移率晶体管(MOSHEMT)。在实施例中，装置区18还可包括用于电隔离的深沟槽隔离区和/或用于电连接的硅通孔。
接着进行中段工艺处理和后段工艺处理，其中包括形成用于位于半导体衬底10上方和晶体管50、56、64之上的互连结构的触点、通孔、以及布线。可以形成与场效应晶体管50、双极结晶体管56和晶体管64耦合的各种金属化层，例如第一金属化(M1)层。为此，在形成金属化层之前，可以用介电材料填充一个或多个介电层65中的开口。
装置区18中的多晶区46在装置区16中的场效应晶体管50和装置区18中的晶体管64之间以及装置区20中的双极结晶体管56和装置区18中的晶体管64之间提供横向电隔离。多晶层44为装置区16中的场效应晶体管50和装置区20中的双极结晶体管56提供垂直电隔离。由多晶层44和多晶区46提供的隔离可以防止串扰并提高射频性能。
参考图9且根据替代实施例，半导体衬底10可以是绝缘体上硅衬底，其包括埋入式氧化物层84和特征在于<111>晶体取向的处理衬底(handle substrate)86。通过控制植入层38的植入条件，由植入层38的热处理形成的多晶层44可以位于埋入式氧化物层84下方。沟槽30穿过埋入式氧化物层84延伸到装置区18中的处理衬底86，且层堆栈36外延生长在处理衬底86上。装置区16中的场效应晶体管50和装置区20中的双极结晶体管56使用绝缘体上硅衬底的装置层形成。
参考图10并根据替代实施例，多晶层45可以在半导体衬底10中围绕沟槽30的外围形成。更具体地，多晶层45可以与位于表面32的沟槽底部相邻且在半导体衬底10中与侧壁29、31相邻。在形成层堆栈36之前，多晶层45可以通过离子植入工艺在与沟槽30的表面32和侧壁29、31相邻的植入层(与植入层38类似)中产生损坏的半导体材料而形成。植入层可以通过与用于形成多晶层44和多晶区46的相同热处理转化为多晶层45。单晶半导体材料的再结晶层17位于多晶层45和沟槽底部的半导体衬底10的表面32之间。在用作形成多晶层45的工艺流程的一部分的植入工艺期间，装置区16和装置区20可以通过类似于植入掩模22的植入掩模来遮蔽。
如上所述的方法用于制造集成电路芯片。所得集成电路芯片可由制造商以原始晶圆形式(例如，作为具有多个未封装芯片的单个晶圆)、作为裸晶粒或以封装形式分发。在后一种情况下，芯片安装在单个芯片封装中(例如，塑料载体，引线固定在主板或其他更高级别的载体上)或多芯片封装(例如，陶瓷载体，具有表面互连或埋入互连或两者皆有)。在任何情况下，芯片都可以与其他芯片、分立电路元件和/或其他信号处理装置集成，作为中间产品或最终产品的一部分。
本文对由近似语言修饰的术语，例如“大约(about)”、“大约(approximately)”和“实质上(substantially)”的引用，不限于指定的精确值。近似语言可能对应于用于测量值的仪器的精度，除非另外依赖于仪器的精度，否则可能表示所述值的+/-10％。
本文对诸如“垂直”、“水平”等术语的引用是作为示例而非限制，以建立参考框架。如本文所用，术语“水平”被定义为平行于半导体衬底的常规平面的平面，而不管其实际的三维空间取向。术语“垂直”和“法线”指的是垂直于水平线的方向，正如刚刚定义的那样。术语“横向”是指水平面内的方向。
“连接(connected)”或“耦合(coupled)”到另一特征或与另一特征“连接”或“耦合”的特征可直接连接或耦合至另一特征或与之耦合，或替代地，可存在一个或多个中间特征。如果不存在中间特征，则特征可以与另一特征“直接连接”或“直接耦合”或与另一特征“直接连接”或“直接耦合”。如果存在至少一个中间特征，则特征可以与另一特征“间接连接”或“间接耦合”。“在”另一特征上或“接触”另一特征的特征可直接在另一特征上或直接接触另一特征，或替代地，可存在一个或多个中间特征。如果不存在中间特征，则特征可能“直接”在另一个特征上与另一个特征“直接接触”。如果存在至少一个中间特征，则特征可以“间接”在另一特征上或与另一特征“间接接触”。
本发明的各种实施例的描述是出于说明的目的而呈现的，但并非旨在穷举或限于所公开的实施例。在不脱离所描述实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员来说将是显而易见的。选择此处使用的术语以最好地解释实施例的原理、实际应用或对市场中发现的技术的技术改进，或使本领域普通技术人员能够理解此处公开的实施例。

Claims (20)

1.一种结构，包括：
半导体衬底，具有第一装置区和第二装置区；
第一晶体管，在所述半导体衬底的所述第一装置区中；
第二晶体管，在所述半导体衬底的所述第二装置区中，所述第二晶体管包括在所述半导体衬底上的层堆栈，且所述层堆栈包括由III-V族化合物半导体材料构成的层；以及
多晶层，在所述半导体衬底中，所述多晶层包括位于所述第一装置区下方的所述半导体衬底中的第一区段。
2.如权利要求1所述的结构，其中，所述半导体衬底具有第一表面和从所述第一表面延伸至所述半导体衬底中的沟槽，所述层堆栈位于所述沟槽内的所述半导体衬底上，且还包括：
多晶区，在所述半导体衬底中与所述沟槽相邻。
3.如权利要求2所述的结构，其中，所述多晶区从所述第一表面延伸到所述多晶层的所述第一区段。
4.如权利要求3所述的结构，还包括：
浅沟槽隔离区，在所述半导体衬底中，所述浅沟槽隔离区横向位于所述第一装置区和所述第二装置区之间，
其中，所述多晶层的所述第一区段在所述浅沟槽隔离区下方横向延伸至所述多晶区。
5.如权利要求2所述的结构，其中，所述半导体衬底在所述沟槽的底部具有第二表面，所述沟槽包括从所述第一表面延伸至所述第二表面的侧壁，所述层堆栈位于所述半导体衬底的所述第二表面上，且所述多晶区位于与所述沟槽的所述侧壁相邻。
6.如权利要求5所述的结构，还包括：
浅沟槽隔离区，在所述半导体衬底中，所述浅沟槽隔离区横向位于所述第一装置区和所述第二装置区之间，
其中，所述多晶区横向位于所述沟槽的所述侧壁与所述浅沟槽隔离区之间。
7.如权利要求5所述的结构，其中，所述多晶层包括在所述半导体衬底中位于所述沟槽的所述底部的所述半导体衬底的所述第二表面下方的第二区段。
8.如权利要求5所述的结构，其中，在所述沟槽的所述底部的所述半导体衬底的所述第二表面下方不存在所述多晶层。
9.如权利要求1所述的结构，还包括：
隔离区，在所述层堆栈中。
10.如权利要求9所述的结构，其中，所述半导体衬底包括顶面，所述多晶层的所述第一区段位于相对于所述半导体衬底的所述顶面的第一深度，所述层堆栈包括顶面，所述隔离区位于相对于所述层堆栈的所述顶面的第二深度，且所述第二深度小于所述第一深度。
11.如权利要求1所述的结构，其中，所述半导体衬底包括位于所述第一装置区中的埋入式氧化物层，且所述埋入式氧化物层位于所述多晶层的所述第一区段和所述第一装置区之间。
12.如权利要求1所述的结构，其中，所述半导体衬底具有顶面，且所述多晶层的所述第一区段在整个所述第一装置区下方相对于所述顶面横向延伸。
13.如权利要求12所述的结构，其中，所述半导体衬底具有第三装置区，且还包括：
第三晶体管，在所述半导体衬底的所述第三装置区中，
其中，所述多晶层包括位于所述第二装置区下方的所述半导体衬底中的第二区段，且所述第一晶体管和所述第二晶体管是不同类型的晶体管结构。
14.如权利要求13所述的结构，其中，所述多晶层的所述第二区段在整个所述第三装置区下方相对于所述顶表面横向延伸。
15.如权利要求13所述的结构，其中，所述第一晶体管是包括至少部分位于所述顶面下方的所述半导体衬底中的源极/漏极区的场效应晶体管，且所述第三晶体管是包括至少部分位于所述顶面下方的所述半导体衬底中的端子的双极结晶体管。
16.如权利要求1所述的结构，其中，所述半导体衬底由具有金刚石晶格结构和<111>晶向的单晶半导体材料构成。
17.如权利要求16所述的结构，其中，所述半导体衬底是块体衬底，所述单晶半导体材料包括单晶硅，且所述III-V族化合物半导体材料包括具有实质上单晶的晶体结构的氮化镓。
18.一种方法，包括：
形成具有位于半导体衬底的第一装置区下方的第一区段的多晶层；
在所述半导体衬底的所述第一装置区中形成第一晶体管；
在所述半导体衬底的第二装置区中形成包括由III-V族化合物半导体材料构成的层的层堆栈；以及
使用所述层堆栈形成第二晶体管。
19.如权利要求18所述的方法，还包括：
在形成所述多晶层的同时在所述层堆栈中形成隔离区。
20.如权利要求18所述的方法，还包括：
在所述半导体衬底中形成沟槽，
其中，所述层堆栈形成在所述沟槽内的所述半导体衬底上，且所述多晶层包括形成在所述半导体衬底中与所述沟槽相邻的第二区段。
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