CN114580324A - Clock tree correction device and correction method thereof - Google Patents

Abstract

The invention provides a frequency tree correction device and a correction method thereof. The method for correcting the frequency tree comprises the following steps: executing a frequency signal path tracking action aiming at a network link table of the circuit according to the time limit information so as to obtain a frequency tree circuit structure; identifying the confluence state of the frequency tree circuit structure to find out at least one frequency confluence point, and setting one of a plurality of frequency signals on the frequency confluence point as a selected frequency signal; based on the selected frequency signal, performing correction point identification action aiming at the frequency tree circuit structure to obtain a plurality of candidate correction points; and respectively calculating a plurality of weighted values of the candidate correction points, and obtaining a plurality of selected correction points according to the weighted values.

Description

Clock tree correction device and correction method thereof

Technical Field

The present invention relates to a clock tree correction apparatus and a correction method thereof, and more particularly, to a correction apparatus capable of automatically performing a clock tree correction method.

Background

In the field of circuit design, clock pre-correction (clock pre) of clock tree is necessary to perform clock scanning operation by using functional clock signal as scanning clock signal, and in a circuit with complex clock structure, the pre-correction takes much time for designer and causes reduction of design efficiency.

Existing Electronic Design Automation (EDA) software often inserts multiplexers into the circuit so that the clock signal can be routed through the extrapolated multiplexers into the circuit. Such a method usually causes a burden in performing Clock Tree Synthesis (CTS), and increases the circuit area significantly.

Disclosure of Invention

The invention relates to a clock tree correction method and device, which can automatically and quickly perform the pre-correction (prefix) action on a clock tree.

According to the embodiment of the invention, the clock tree correction method comprises the following steps: performing a clock signal path tracking action aiming at a network link table of the circuit according to the time limit information to obtain a clock tree circuit structure; identifying the bus state of the clock tree circuit structure to find out at least one clock bus point, and setting one of a plurality of clock signals on the clock bus point as a selected clock signal; based on the selected clock signal, performing correction point identification action aiming at the clock tree circuit structure to obtain a plurality of candidate correction points; and respectively calculating a plurality of weighted values of the candidate correction points, and obtaining a plurality of selected correction points according to the weighted values.

According to an embodiment of the present invention, a device for modifying a clock tree of a circuit includes a storage element and a controller. The memory element stores a time limit information pin and a network link table of the circuit. The controller is coupled to the storage element for executing the clock tree modification method.

According to the above, the clock tree correction method of the present invention obtains the clock tree circuit structure by tracking the clock signal path, identifies the candidate correction points in the clock tree circuit structure, sets a plurality of weight values for the candidate correction points, and obtains a plurality of selected correction points according to the weight values. Therefore, the selected correction point can be generated quickly and automatically, and the efficiency of design analysis is improved.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

FIG. 1 is a flow chart illustrating a method for modifying a clock tree according to an embodiment of the invention;

FIG. 2 is a flow chart illustrating a method for modifying a clock tree according to another embodiment of the present invention;

FIG. 3 shows a schematic diagram of a clock tree circuit structure of an embodiment of the present invention;

FIG. 4 illustrates a schematic diagram of a clock merge point of an embodiment of the present invention;

FIG. 5 is a schematic diagram of a clock tree circuit structure and its correction points according to an embodiment of the present invention;

FIG. 6 is a diagram illustrating a manner in which a plurality of candidate correction points are generated according to an embodiment of the invention;

fig. 7A to 7C are schematic diagrams illustrating a weight setting manner of candidate correction points;

fig. 8A and 8B are schematic diagrams illustrating a selection manner of selecting a correction point;

fig. 9 is a schematic diagram of a clock tree correction apparatus according to an embodiment of the invention.

Description of the reference numerals

300. 400 and 500: a clock tree circuit structure;

610. 620, 630: a solution meaning tree structure;

900: a clock tree correction device;

910: a controller;

920: a storage element;

AN1, AN2, AN3, AN4, AN41, AN 42: an AND gate;

CL11, CL12, CL21, CL22, CL 23: a combinational logic circuit;

clk, clk1, clk 2: a clock signal;

ICG1, ICG2, ICG: a clock isolation gate;

IE 1-IE 3, P1-P3, A, B, C, D, E, F, G, H, I, J1, J2, J3, K, L: an input end;

IF 1: a network link table;

IF 2: time limit information;

J. m, N, O: an output end;

LC 1: a logic component;

MUX1, MUX 41: a multiplexer;

ND 11-ND 39: candidate correction points;

OR1, OR 2: an OR gate;

s110 to S140, S210 to S250: correcting a clock tree;

and SE: a source;

W11-W39: and (4) weighting values.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Referring to fig. 1, fig. 1 is a flowchart illustrating a clock tree modification method according to an embodiment of the invention. In step S110, a clock signal path tracing operation is performed on a network link table (netlist) of the circuit according to the time constraint information, and a clock tree circuit structure is obtained through the clock signal path tracing operation. Next, in step S120, a bus state of the clock tree circuit structure obtained in step S110 may be identified to find one or more clock bus points, and one of the clock signals at the clock bus points may be set as a selected clock signal. It should be noted that in a circuit design, there may be multiple clock signals in a clock tree circuit structure. Step S120 is used to identify the clock confluence points of the clock signals. Here, the designer may select one of the plurality of clock signals as a selected clock signal.

Incidentally, in the present embodiment, the clock confluence of the clock signal usually occurs on a circuit component which is a multiplexer (multiplexer).

In step S130, a correction point recognition operation is performed on the clock tree circuit structure based on the selected clock signal, and a plurality of candidate correction points are obtained. In this embodiment, a plurality of circuit elements (logic gates) associated with the selected clock signal in the clock tree circuit structure may be analyzed and set as a plurality of candidate correction points.

In step S140, weight values are set and calculated for the candidate correction points, and a plurality of selected correction points are obtained according to the weight values of the candidate correction points. Corresponding to a plurality of selected correction points, a designer can make the logic value on the selected correction point sufficient for the selected clock signal to be smoothly transmitted in the clock tree circuit structure by correcting the logic expression, and make the functional clock path (function clock path) be used as the scan clock path (scan clock path).

Referring to fig. 2, fig. 2 is a flowchart illustrating a clock tree modification method according to another embodiment of the invention. In step S210, the network link table IF1 and the time limit information IF2 of the circuit are received, and the clock path tracking operation is performed accordingly. Please refer to fig. 2 and fig. 3 synchronously, wherein fig. 3 illustrates a schematic diagram of a clock tree circuit structure according to an embodiment of the present invention. When the clock path tracking operation is performed, the clock signal clk in the circuit can be found out, and the tracking operation is performed according to the transmission direction of the clock signal clk. In the tracking operation, the circuit elements along the transmission path of the clock signal clk are recorded, and in FIG. 3, the clock signal clk is received by the AND gate AN1 and is sequentially transmitted along the multiplexer MUX1, the AND gate AN2 and the logic element LC 1. It is noted that the tracking action in the clock path of the clock signal clk starts at the source SE of the clock signal clk and ends at the clock isolation gate (ICG) ICG1, ICG2 in the path. In this embodiment, the clock isolation gates ICG1 and ICG2 may be D-type inverters. In fig. 3, the clock tree 300 corresponding to the clock signal clk is established by recording the connection relationship among the and gate AN1, the multiplexer MUX1, the and gate AN2 and the logic element LC 1.

It should be noted that, in the embodiment of the present invention, the input logic values may be recorded in a plurality of circuit elements of the clock tree circuit structure 300, so that the clock signal clk can be transmitted smoothly. Taking the embodiment of fig. 3 as AN example, one input of the and gate AN1 receives the clock signal clk, and the other input of the and gate AN1 is set to logic 1, so that the clock signal clk can be transmitted to the output of the and gate AN 1. Similarly, the input terminal of the multiplexer MUX1 is set to logic value based on the fact that the input terminal of the multiplexer MUX1 corresponding to the selection signal is coupled to the output terminal of the and gate AN 1. The first input of the AND gate AN2 is coupled to the output of the multiplexer MUX1, and therefore the second input of the AND gate AN2 is set to a logic value.

Of course, the clock tree circuit structure 300 of fig. 3 includes only illustrative components and structures, and is not intended to limit the scope of the present invention.

Referring to fig. 2 again, next, in step S220, the clock junction of the clock tree circuit structure is identified. Referring to fig. 2 and fig. 4 synchronously, fig. 4 is a schematic diagram of a clock bus point according to an embodiment of the invention. In embodiments of the present invention, the clock bus points often occur in multiplexers in a clock tree circuit structure. In fig. 4, there are a plurality of clock signals clk1, clk2 in the clock tree circuit structure 400. The multiplexer MUX41 receives the clock signals clk1 and clk2 through the and gates AN41 and AN42, respectively. Here, multiplexer MUX41 may be identified as a clock merge point. When a clock bus point (multiplexer MUX41) is identified, the designer may select one of the clock signals clk1, clk2 as the selected clock signal. In the embodiment, taking the clock signal clk1 as the selected clock signal, the select terminal of the multiplexer MUX may be set to logic 0, so that the clock signal clk1 can be transmitted smoothly. In the other part, the input terminal of the and gate AN41 which does not receive the clock signal clk1 is set to logic value 1; the input of AND gate AN42 that does not receive the clock signal clk2 is set to logic 1, and the input of AND gate AN43 that is not coupled to the input of multiplexer MUX41 is set to logic 1. In addition, the clock isolation gate ICG may be the termination point of the clock tree circuit structure 400.

Referring back to fig. 2, after the clock tree circuit structure and the logic values of all the input terminals are set, the correction point recognition operation of the clock tree circuit structure can be performed. Referring to fig. 5, fig. 5 is a schematic diagram of a clock tree circuit structure and its correction points according to an embodiment of the invention. The clock tree circuit structure 500 is generated according to the clock tree circuit structure 300 of FIG. 3 and a plurality of control logic circuits at the periphery thereof. The clock tree circuit structure 500 has a plurality of input terminals IE1 to IE3 for controlling the clock signal clk1, the input terminals IE1 to IE3 respectively correspond to the and gate AN1, the multiplexer MUX1 and the and gate AN2, and the logic values set by the input terminals IE1 to IE3 are respectively logic values 1, 0 and 1.

In addition, the input end IE1 is controlled by an OR gate OR1 and combined logic circuits CL11 and CL 12; the input end IE2 is controlled by AN AND gate AN3 and combined logic circuits CL21 and CL 22; the input IE3 is controlled by a combinational logic circuit CL 23. In the present embodiment, the input terminals and the output terminals of the OR gate OR1, the combinational logic circuits CL11, CL12, the and gate AN3, the combinational logic circuits CL21, CL22 and the combinational logic circuit CL23 can be set as a plurality of candidate correction points, respectively.

Next, referring to fig. 2 again, in step S230, a fixed value is set in the node, that is, a logic value capable of effectively transmitting the clock signal clk is set in the plurality of circuit elements set as the candidate correction points. Specifically, the output of OR gate OR1 is set to logic value 1 (equal to the logic value of input IE 1), and at least one of the two inputs of OR gate OR1 is set to logic value 1. The output of the and gate AN3 is set to logic value 0 (equal to the logic value of the input IE 2), and at least one of the inputs of the and gate AN3 needs to be set to logic value 0. The output of combinational logic CL3 needs to be set to logic 1 (equal to the logic of input IE 3).

Next, in step S240, a plurality of weight values are respectively set for the candidate correction points, and in step S250, a plurality of selected correction points are selected from the plurality of candidate correction points according to the weight values.

For details of the steps S240 and S250, please refer to fig. 6 to 8B. Fig. 6 is a schematic diagram illustrating a generation manner of a plurality of candidate correction points according to an embodiment of the present invention, fig. 7A to 7C are schematic diagrams illustrating a weight setting manner of candidate correction points, and fig. 8A and 8B are schematic diagrams illustrating a selection manner of a selected correction point.

In fig. 6, the clock tree circuit structure 600 corresponds to the clock signal clk, and includes and gates AN1, AN2, and a multiplexer MUX 1. The inputs P1, P2, and P3 of the AND gate AN1, multiplexer MUX1, and AND gate AN2 are set to logic values 1, 0, and 1, respectively. The corresponding input terminal P1, OR gate OR1, and gates AN3 and AN4 are used as control logic circuits for controlling the logic value of the input terminal P1. Based on the input terminal P1 being set to logic value 1, the output terminal M of the OR gate OR1 is set to logic value 1; the inputs I, J1 of OR gates OR1 (equivalent to the output J of and gate AN 4) may each be set to a logic value of 1; the inputs A, B of the and gate AN3 are both set to logic 1; the inputs C, D of the and gate AN4 are each set to a logic value of 1.

In addition, based on the input terminal P2 being set to logic value 0, the output terminal N of the OR gate OR2 being set to logic value 0; the input terminals J2 (equivalent to the output terminal J of the and gate AN 4) and K (equivalent to the output terminal of the and gate AN 5) of the OR gate OR2 can both be set to logic value 0; the inputs E, F of the and gate AN5 may both be set to a logic value of 0; the inputs C, D of the and gate AN4 are each set to a logic value of 0.

Based on the input terminal P3 being set to logic value 1, the output terminal O of the OR gate OR3 is set to logic value 1; the inputs J3 (equivalent to the output J of the and gate AN 4), L (equivalent to the output of the and gate AN 6) of the OR gate OR3 may each be set to a logic value of 1; the inputs G, H of the and gate AN6 may each be set to a logic value of 1; the inputs C, D of the and gates AN4 are both set to a logic value of 1.

According to the above-mentioned setting of the logic values of the endpoints, the solution meaning tree structures 610, 620, 630 can be established corresponding to the input ends P1, P2, P3, respectively. The solution meaning tree structures 610, 620, and 630 include tree structures formed by a plurality of candidate correction points of the corresponding input terminals P1, P2, and P3, respectively.

It is noted that in embodiments of the present invention, binary integer tree linear programming (binary integer linear programming) or a heuristic algorithm may be applied to obtain the selected correction points from the solution meaning tree structures 610, 620, 630. An exemplary embodiment is provided below to illustrate the method for obtaining the selected correction point.

In FIG. 7A, for the solution meaning tree structure 610, an analysis may be performed for a plurality of endpoints therein and corresponding set logic values, and a weight value may be applied to each candidate correction point in the solution meaning tree structure 610. In the weight value setting method, a candidate correction point in the solution meaning tree structure 610 may be selected as a parent node, and the weight values of a plurality of child nodes of the parent node are set according to the type of logic circuit corresponding to the parent node and the weight value of the parent node. First, the candidate correction point ND11 may be set as the parent node, and the weight value W11 of the candidate correction point ND11 may be set to 1. Since the candidate correction point ND11 has only one child node (candidate correction point ND12), the weight value W12 of the candidate correction point ND12 is the same as the weight value W11 of the candidate correction point ND11 (1). Next, since the candidate correction point ND12 corresponds to the output terminal M of the OR gate OR1, when the candidate correction point ND12 is a parent node, the weight values W13, W14 of its child nodes (candidate correction points ND13, ND14) may be the same as the weight value W12 of the candidate correction point ND 2(═ 1). In addition, when the candidate correction point ND13 is the parent node, the output terminal I of the and gate AN3 is corresponded based on the candidate correction point ND 13. Therefore, the weight value W13 of the candidate correction point ND13 may be equally distributed to its child nodes (candidate correction points ND15, ND16), and the weight values W15, W16 of the candidate correction points ND15, ND16 are made equal to 0.5.

By analogy with the above method, the weight values W11 to W19 of all the candidate correction points ND11 to ND19 can be calculated.

In fig. 7B, weight values W21W 29 may be set for the candidate correction points ND21 ND29 in the solution meaning tree structure 620, respectively, in the same manner as in fig. 7A. Similarly, in fig. 7C, the weight values W31 to W39 may be set in effect for the candidate correction points ND31 to ND39 in the solution meaning tree structure 630.

Next, in the embodiment of the present invention, the weighting values W11 to W39 corresponding to all the candidate correction points ND11 to ND39 may be sorted, and the candidate correction points corresponding to the same end point and having the same logic value set therein may be subjected to the operation of adding the weighting values, so that fig. 8A may be obtained. It should be noted that the candidate correction point ND17 in fig. 7A and the candidate correction point ND37 in fig. 7C correspond to the same output terminal J and are set to the same logic value 1. Therefore, the weight values W17 and W37 of the candidate correction point ND17 and the candidate correction point ND37 may be added, and a weight value corresponding to J ═ 1 (equal to 2) is generated.

As can be seen from fig. 8A, the candidate correction point corresponding to J ═ 1 has the highest weight value, and therefore the candidate correction point having J ═ 1 can be selected first as the first selected correction point.

Next, in fig. 8B, candidate fix-up points based on J ═ 1 have been selected, and all candidate fix-up points associated with solution meaning tree structures 610, 630 are pruned. At this time, the candidate correction point corresponding to N ═ 0 has the highest weight value (═ 1), and therefore, the candidate correction point corresponding to N ═ 0 is selected as the second selected correction point.

Further, by the clock tree modification method according to the embodiment of the present invention, it can be known that only the output terminal J of the and gate AN4 in the clock tree circuit structure 600 of fig. 6 needs to be controlled to be logic 1, that is, the input terminals P1 and P3 can be controlled to be logic 1, and the output terminal N of the OR gate OR2 in the clock tree circuit structure 600 of fig. 6 is controlled to generate logic 0, so that the input terminal P2 can be controlled to be logic 0. As such, the clock signal clk may be efficiently transmitted. The embodiment of the invention finishes the correcting action of the clock tree by an automatic and quick method.

Referring to fig. 9, fig. 9 is a schematic diagram illustrating a clock tree correction apparatus according to an embodiment of the invention. The clock tree modification apparatus 900 includes a controller 910 and a storage element 920. The controller 910 and the storage element 920 are coupled to each other. The storage element 920 may be used to store the time limit information of the circuit and the network link table. The controller 910 can read the time limit information of the circuit and the network link table from the storage element 920, and execute the clock tree modification method shown in fig. 1 and 2 according to the time limit information of the circuit and the network link table.

The details of the clock tree correction method have been described in detail in the foregoing embodiments, and are not repeated herein.

In the present embodiment, the storage element 920 is also used to store temporary data generated by the calculation process of the controller 910. In terms of hardware architecture, the controller 910 may be a processor with computing capabilities. Alternatively, the controller 910 may be a Hardware Circuit designed by Hardware Description Language (HDL) or any other digital Circuit design known to those skilled in the art, and implemented by Field Programmable Gate Array (FPGA), Complex Programmable Logic Device (CPLD) or Application-specific Integrated Circuit (ASIC). In addition, the storage component 920 can be various Random Access Memories (RAMs), Read Only Memories (ROMs), etc., but not limited thereto.

In summary, the present invention identifies a plurality of candidate correction points in the clock tree circuit structure, sets a plurality of weight values for the candidate correction points, and finds out a selected correction point according to the weight values. Therefore, the correcting action of the clock tree of the circuit can be found out quickly and automatically, and the efficiency of circuit design is improved.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A method of modifying a clock tree, comprising:

performing a clock signal path tracking action aiming at a network link table of the circuit according to the time limit information to obtain a clock tree circuit structure;

identifying the confluence state of the clock tree circuit structure to find out at least one clock confluence point, and setting one of a plurality of clock signals on the at least one clock confluence point as a selected clock signal;

based on the selected clock signal, performing correction point identification action aiming at the clock tree circuit structure to obtain a plurality of candidate correction points; and

and respectively calculating a plurality of weighted values of the candidate correction points, and obtaining a plurality of selected correction points according to the weighted values.

2. The method for correcting clock trees according to claim 1, wherein the step of calculating a plurality of weighting values for the candidate correction points respectively and obtaining the selected correction points according to the weighting values comprises:

establishing a plurality of solution meaning tree structures aiming at the candidate correction points respectively; and

performing a binary whole tree linear programming or heuristic algorithm on the plurality of solution meaning tree structures to obtain the plurality of selected correction points.

3. The method for correcting a clock tree according to claim 2, wherein the step of calculating the plurality of weight values of the plurality of candidate correction points respectively comprises:

setting each candidate correction point as a parent node, and setting the weight values of a plurality of child nodes of the parent node according to the logic circuit type corresponding to the parent node and the weight value of the parent node.

4. The method for correcting a clock tree according to claim 3, wherein when the logic circuit corresponding to the parent node is an AND gate, the sum of the weight values of the plurality of child nodes is equal to the weight value of the parent node, and when the logic circuit corresponding to the parent node is an OR gate or a buffer, the weight value of each of the child nodes is equal to the weight value of the parent node.

5. The method for modifying a clock tree as defined in claim 1, wherein the step of obtaining the selected correction points according to the weight values comprises:

selecting the maximum weighted value to generate a selected weighted value, and setting a candidate correction point corresponding to the selected weighted value as a first selected node; and

removing at least one associated candidate correction point associated with the first selected node, and selecting the candidate correction point with the largest weight value as a second selected node.

6. The method of claim 1, wherein the step of performing the clock signal path tracing operation for the network link table of the circuit according to the time constraint information to obtain the clock tree circuit structure comprises:

based on a clock signal, finding a plurality of circuit components on a transmission path of the clock signal; and

and marking a plurality of logic signals which can enable the clock signal to be transmitted smoothly on the plurality of circuit components.

7. The method for modifying a clock tree as defined in claim 1, wherein the step of setting one of the plurality of clock signals at the at least one clock junction as the selected clock signal further comprises:

and marking a logic signal which can enable the selected clock signal to be transmitted on the at least one clock confluence point.

8. An apparatus for modifying a clock tree of a circuit, comprising:

a storage element storing a time limit information pin and a network link table of the circuit; and

a controller coupled to the storage element for:

executing a clock signal path tracking action aiming at the network link table according to the time limit information so as to obtain the clock tree circuit structure;

identifying the bus state of the clock tree circuit structure to find out at least one clock bus point, and setting one of a plurality of clock signals on the at least one clock bus point as a selected clock signal;

based on the selected clock signal, performing correction point identification action aiming at the clock tree circuit structure to obtain a plurality of candidate correction points; and

and respectively calculating a plurality of weighted values of the candidate correction points, and obtaining a plurality of selected correction points according to the weighted values.

9. The clock tree correction apparatus of claim 8, wherein the controller establishes a plurality of solution meaning tree structures for the plurality of candidate correction points, respectively, and performs a binary whole tree linear programming or heuristic for the plurality of solution meaning tree structures to obtain the plurality of selected correction points.

10. The apparatus for modification of a clock tree as defined in claim 8, wherein the controller is configured to:

setting each candidate correction point as a parent node, and setting the weight values of a plurality of child nodes of the parent node according to the logic circuit type corresponding to the parent node and the weight value of the parent node;

selecting the maximum weighted value to generate a selected weighted value, and setting a candidate correction point corresponding to the selected weighted value as a first selected node; and

removing at least one associated candidate correction point associated with the first selected node, and selecting the candidate correction point with the largest weight value as a second selected node.

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