CN112651198A

CN112651198A - Method for dividing non-causal circuit and method for gate-level circuit parallel simulation

Info

Publication number: CN112651198A
Application number: CN202110120810.0A
Authority: CN
Inventors: 黄国勇; 张聪; 丁家峰; 赵岩
Original assignee: Guowei Group Shenzhen Co ltd
Current assignee: Guowei Group Shenzhen Co ltd
Priority date: 2021-01-28
Filing date: 2021-01-28
Publication date: 2021-04-13

Abstract

The invention provides a non-causal circuit partitioning method and a gate-level circuit parallel simulation method, wherein the non-causal circuit partitioning method comprises the following steps: step S1: converting the gate-level circuit into a directed graph, and storing data by using a structure body; step S2: searching a set V of output nodes with output to the outside from the structure body; step S3: all directed edges in the directed graph are reversely processed, and nodes in the set V are explored in sequence; step S4: initially dividing the directed graph into a plurality of primary units according to the exploration result; step S5: and merging the primary units meeting the merging requirement in the initial division to form a secondary unit, outputting all final primary units which cannot be merged, and storing the secondary unit and all primary units which cannot be merged in a structural body form. Compared with the prior art, the invention can divide the circuits without dependency relationship in the digital circuit and run simulation independently, thereby improving the simulation efficiency.

Description

Method for dividing non-causal circuit and method for gate-level circuit parallel simulation

Technical Field

The invention relates to EDA circuit parallel simulation, in particular to a non-causal circuit division method and a gate-level circuit parallel simulation method.

Background

With the rapid development of modern integrated circuit manufacturing technology, very large scale integrated circuits have tens of millions or even hundreds of millions of gates. In the design of an EDA circuit, in order to accelerate the simulation speed of a very large scale integrated circuit, parallel simulation is adopted and is an effective way for improving the simulation precision and shortening the simulation period. In order to parallelize simulation efficiently, circuits are divided reasonably before simulation. The traditional circuit division is a causal division method, and dependency relationships exist among circuits of each block of causal division. However, circuits without dependency relationship in the circuits cannot be well divided, so that the simulation efficiency is not well improved.

Therefore, how to design a non-causal circuit partitioning method and a gate level circuit parallel simulation method for partitioning a circuit without dependency relationship in the circuit is an urgent technical problem to be solved in the industry.

Disclosure of Invention

Aiming at the technical problem that a circuit without dependency relationship cannot be divided in the prior art, the invention provides a non-causal circuit dividing method and a gate-level circuit parallel simulation method.

The technical scheme of the invention is that a method for dividing a non-causal circuit is provided, which comprises the following steps: step S1: converting the gate-level circuit into a directed graph, and storing data by using a structure body;

step S2: searching a set V of output nodes with output to the outside from the structure body;

step S3: all directed edges in the directed graph are reversely processed, and nodes in the set V are explored in sequence;

step S4: initially dividing the directed graph into a plurality of primary units according to the exploration result;

step S5: and merging the primary units meeting the merging requirement in the initial division to form a secondary unit, outputting all final primary units which cannot be merged, and storing the secondary unit and all primary units which cannot be merged in a structural body form.

Further, the converting the gate level circuit into a directed graph comprises:

the nodes in the directed graph represent a gate level circuit, and the directed edges (a, b) between the nodes represent the output of the gate level circuit a connected to the output of the gate level circuit b.

Further, let the structure be G, which contains at least 7 parts, which are g.name, g.matrix, g.input.name, g.input.matrix, g.output.name, g.output.matrix, g.cost;

the name stores the name of each node of the graph;

the G.matrix stores a adjacency matrix of the directed graph;

the g.input.name stores the name of the external input to the directed graph;

the G.input.matrix is a matrix and stores external input information to the directed graph;

the g.output.name stores a name of an output to the outside of the graph;

the g.output.matrix is a matrix, and stores information output to the outside by the graph;

cost stores the cost of each node in the graph.

Further, the searching the set V of output nodes having outputs to the outside from the structural body includes:

and obtaining an output node with output to the outside in the directed graph according to the G.output.matrix, and recording as a set V.

Further, the initially dividing the directed graph into a plurality of primary units according to the exploration result includes:

and sequentially carrying out depth-first exploration from the output nodes in the set V, storing all nodes obtained by each search, dividing each exploration into one primary unit, and counting the ith primary unit as M { i }.

Further, the merging requirement is: the minimum number a of the same nodes required by combination between any two units is less than or equal to the number b of the same nodes actually required by combination between any two units.

Further, the step S5 further includes:

step S51: inputting primary unit s1, primary unit s2, and similar scale per;

step S52: finding the minimum number a of the same nodes required by the combination of the primary unit s1 and the primary unit s2 and the number b of the same nodes of the primary unit s1 and the primary unit s 2;

step S53: and comparing the sizes of the a and the b, judging whether the sizes meet the merging requirement, and if so, executing merging operation.

Further, after the merging operation is executed, the method further comprises the following steps:

step S54: judging whether the similar proportion per of the primary unit S1 and the primary unit S2 meets the preset requirement, if so, combining the primary unit S1 and the primary unit S2, and if not, entering the step S55;

step S55: sequentially judging the similarity of the primary unit s1 and all the other units, and performing merging operation when the similarity meets the preset requirement;

step S56: and reselecting the primary units, sequentially comparing all the primary units which are not compared, and outputting the primary units which cannot be combined until all the primary units cannot be combined.

Further, the reselecting the primary unit, and sequentially comparing all the primary units not compared includes:

and (3) setting the total unit number as S, and the previous detection unit as the ith unit, reselecting the (i + 1) th unit, and comparing with the rest un-compared units until the reselected unit number i +1 is equal to the total unit number S.

The invention also provides a gate-level circuit parallel simulation method, which divides the circuit by adopting the non-causal circuit division method.

Compared with the prior art, the invention has at least the following beneficial effects:

a non-causal partitioning of the gate level circuit can be achieved. The result of circuit division has no dependency relationship and can be completely independently simulated in parallel. Meanwhile, the combination severity can be controlled by controlling the size of the threshold value per, so that the number of blocks of a circuit division result is controlled, and the practicability is high.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

FIG. 1 is an overall flow chart of the present invention;

FIG. 2 is a flowchart of an algorithm procedure for determining whether two primary units meet the merge requirement after the initial partition of the present invention;

FIG. 3 is a flowchart of an algorithm procedure for merging the initial partitioning results according to the present invention.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Thus, a feature indicated in this specification will serve to explain one of the features of one embodiment of the invention, and does not imply that every embodiment of the invention must have the stated feature. Further, it should be noted that this specification describes many features. Although some features may be combined to show a possible system design, these features may also be used in other combinations not explicitly described. Thus, the combinations illustrated are not intended to be limiting unless otherwise specified.

The principles and construction of the present invention will be described in detail below with reference to the drawings and examples.

Because the structure of the integrated circuit is complex, in order to accelerate the speed of ultra-large scale integrated circuit simulation, parallel simulation is an effective way for improving the simulation precision and shortening the simulation period, in order to carry out efficient parallel simulation, circuits need to be reasonably divided before simulation, the traditional circuit division is causal division, and circuits without dependency relationship in the circuits cannot be well divided. The idea of the invention is to provide a non-causal circuit dividing method, which divides a circuit into a plurality of mutually independent units, performs independent simulation and improves the simulation efficiency.

Referring to fig. 1, the present invention provides a method for non-causal circuit partitioning, which includes steps S1: converting the gate-level circuit into a directed graph, and storing data by using a structure body;

In the directed graph G (V, E), V = {,

,…,

is a set of nodes, E = &

,

,…,

Is the set of edges. By using

To indicate the presence of a directed edge, from the vertex

Pointing to the vertex

The resulting matrix D = D (g) =

Is an adjacency matrix of the directed graph G. In digital circuits, which often have a plurality of gate-level circuits, adjacent gate-level circuits are connected and the output of gate-level circuit a is connected to the input of gate-level circuit b. So here the digital circuit can be abstracted as a directed graph, where each node in the directed graph can represent a gate level circuit and the directed edges (a, b) between the nodes represent the connection of the output of gate a to the input of gate b, and the adjacency matrix of the directed graph

The connection relationship of each part in the digital circuit can be expressed.

In the prior art, causal division is mostly adopted, dependency exists between two blocks of a circuit in the causal division, the output of a first block may be the input of a second block, but the division of a part without the dependency in the circuit cannot be good.

The step S1 of storing data with the structure includes: the structure is G, and the structure is divided into at least 7 parts, namely G.name, G.matrix, G.input.name, G.input.matrix, G.output.name, G.output.matrix and G.cost;

the G.name stores the name of each node of the graph;

matrix stores the adjacency matrix of the directed graph;

name stores the name of the external input to the directed graph;

input. matrix is a matrix, and stores external input information to the directed graph;

name stores the name of the output of the graph to the outside;

output, matrix is a matrix, which stores the information output from the graph to the outside;

cost stores the cost of each node in the graph.

After data is saved in the form of the structure body, the information of the digital circuit can be rapidly acquired through the structure body, if the information of the digraph output to the outside is required to be acquired, the digraph can be directly searched through G.output.matrix, and when the information of the outside input to the digraph is required to be acquired, the digraph can be directly searched through G.input.matrix, so that the digraph is more convenient and rapid.

After data are stored in a structural body form, the circuit is primarily divided, all directed graphs in the directed graphs are subjected to reverse processing in the application, nodes output from the outside are traced back from the directed graphs until the nodes are initially input, all nodes obtained by each exploration are stored, all nodes obtained by each exploration are divided into a primary unit, and the ith primary unit is M { i }.

The number of primary units obtained after the initial division is consistent with the number of output nodes externally output by the directed graph. The nodes externally output by the directed graph are searched back, all the nodes influencing the nodes can be found out, if the nodes influencing the output of a certain node cannot be determined by searching the input nodes of the directed graph, for example, the output ends of a gate-level circuit a1 and a gate-level circuit a2 are connected to the input end of a gate-level circuit a3, the output end of a gate-level circuit a3 is connected to the input end of a gate-level circuit a4, the gate-level circuits influencing the gate-level circuit a4 have a1, a2 and a3, if the nodes are searched from the forward direction, the gate-level circuit a1 is searched to the gate-level circuit a4, only the gate-level circuits a1, a3 and a4 are searched in the middle, the influence of the gate-level circuit a2 on the gate-level circuit a3 is ignored, and after the nodes are searched back, all the gate-level circuits a1, a2, a3 and a4 can be found.

After the gate-level circuit is reversely processed, each node can be explored once from an output node of the original directed graph for external output, each node is preliminarily divided into a primary unit, and after the exploration is finished finally, the number of the obtained primary units is consistent with the number of the nodes of the directed graph for external output.

When searching is carried out, all output nodes which are output to the outside in the directed graph need to be found firstly, the nodes are searched through a structural body, the structural body G.output.matrix stores information which is output to the outside of the directed graph, so that the output nodes which are output to the outside of the directed graph can be determined, the number of the counting nodes is S, the number of primary units obtained after initial division is S, all nodes which have influence on the output nodes are recorded after searching is carried out, and the counting nodes are M { i }, namely the primary units, if the first node which is output to the outside is 1, the set of the nodes which have influence on the primary units is M {1}, the second node which is output to the outside is 2, the set of the nodes which have influence on the primary units is M {2}, and the like, the set of the nodes which have influence on the nodes which are output to the outside is calculated.

Since there are cases where the output of one gate stage circuit is connected to the inputs of a plurality of gate stage circuits or the input of one gate stage circuit is connected to the outputs of a plurality of gate stage circuits in a digital circuit, for example, the output of gate stage circuit a1 is connected to the input of gate stage circuit a2, the output of gate stage circuit a2 is connected to the input of gate stage circuit a3, the output of gate stage circuit a3 is connected to the input of gate stage circuit a4, and the outputs of gate stage circuit a4 are connected to the inputs of gate stage circuit a5 and gate stage circuit a6, respectively, and then output through gate stage circuit a5 and gate stage circuit a 6. After the reverse exploration, the circuit is divided into 2 primary units which are respectively a gate-level circuit a1, a gate-level circuit a2, a gate-level circuit a3, a gate-level circuit a4 and a gate-level circuit a 5; the gate-level circuit a1, the gate-level circuit a2, the gate-level circuit a3, the gate-level circuit a4 and the gate-level circuit a6 show that only the gate-level circuit a5 and the gate-level circuit a6 are different in the two primary units, and the rest parts are completely the same, and if the two primary units are separately simulated, almost repeated simulation is performed twice, so that the two primary units with higher similarity need to be combined.

Taking any two elementary units as S1 and S2, the same node number in elementary unit S1 and elementary unit S2 is b, the minimum same node number required for merging elementary unit S1 and elementary unit S2 is a, if a is less than or equal to b, it can be determined that elementary unit S1 and elementary unit S2 can be merged to meet the merging requirement.

Please refer to fig. 2, which is a flowchart of an algorithm procedure for determining whether two primary units meet the merging requirement after the initial partitioning, and specifically, the method includes: step S51: inputting primary unit s1, primary unit s2, and similar scale per;

Here, the similarity ratio per is between 0 and 1, which represents the similarity between two units, and the higher the similarity, the larger the number of nodes that are considered to be the same between two primary units. The output results are 0 and 1, when b is more than or equal to a, the output result is 1, which represents that the combination can be realized, and when a is more than or equal to b, the combination can not be realized.

Please refer to fig. 3, which is a flowchart of an algorithm procedure for merging initial partitioning results according to the present invention, and when it is determined that the initial partitioning results can be merged by the flowchart in fig. 2, the merging operation is performed by the algorithm in fig. 3, which includes:

step S54: judging whether the similar proportion per of the primary unit S1 and the primary unit S2 meets the preset requirement, if so, entering the merging operation, and if not, entering the step S55;

As shown in the figure, at the beginning stage, let enable signal be 1, and enter to judge whether enable signal is 1, when enable signal is 0, it is determined that it does not need to be merged, when enable signal is 1, it is determined that it needs to be merged, after the flow in fig. 2, it is determined that two elementary units can be merged, so here, after entering the flow in fig. 3, let initial enable signal be 1, it is determined that it can be merged, and enter to the merging cycle.

In fig. 3, the dotted line portion is a merging operation, the two primary units are i and j, i is 1, j is i +1=2, the similarity between M {1} and M {2} is determined, if the similarity is 1, merging is performed and then output, and en =1, since en =1 re-asserts it to 1 and enters a loop when it re-enters a signal frame for determining whether the enable signal en is 1, i = i +1 at this time, since the previous primary unit has already performed a merging operation, it is determined again and merged from the next primary unit after i = i +1 is performed here. If the similarity between M { i } and M { j } is judged to be not 1, judging whether j is equal to S at the moment, if j = S at the moment, judging that the current ith primary unit and other primary units are judged to be finished, outputting M { i }, and enabling i = i +1 to judge the next primary unit; if j is not equal to S, let j = j +1, determine the similarity between the next primary unit and the ith primary unit until the similarity is 1, and merge or j = S, and all the units identical to i are determined.

Assuming that the total number of cells is 5, the initial value of i is 1, when j is i +1=2, the similarity between M {1} and M {2} is determined, if the similarity is not 1, j = j +1 is made, the similarity between M {1} and M {3} is determined, until two similarities are 1, a merging operation is performed, or if the similarity is not 1, the determination of M {1} and M {2}, M {3}, M {4}, and M {5} is completed, and M {1} is output to determine that it is not necessary to merge, at this time, i = i +1 is made, the determination is started from M {2} and compared with M {3}, M {4}, and M {5}, and so on, the similarity between any two cells in 5 primary cells can be compared, and merging is performed.

After the program in fig. 3 is passed, any two units in the final output result cannot perform a merge action, that is, there is no dependency relationship between any two units in the gate-level circuit, and the simulation can be performed independently. The output result unit comprises a secondary unit and a primary unit, the secondary unit is a unit obtained by merging the primary units, and the primary unit, the secondary unit and the secondary unit cannot be merged in the final result.

In this embodiment, the preset requirement of the similarity is 1, the threshold of the similarity per may be adjusted according to the actual situation, for example, it is set to 0.6, and whether the similarity between M { i } and M { j } is equal to 1 is changed to be equal to or greater than 0.6 is determined, and when the similarity is equal to or greater than 0.6, the merging is performed, and the severity of the merging may be changed according to the actual need.

Compared with the prior art, the invention can realize non-causal division of the gate-level circuit. The result of circuit division has no dependency relationship and can be completely independently simulated in parallel. Meanwhile, by controlling the size of the threshold per, the severity of the combination can be controlled, thereby controlling the number of blocks of the circuit division result. Practice proves that the practicability is high.

The invention also provides a parallel simulation method of the gate-level circuit, which adopts the division method of the non-causal circuit in the parallel simulation of the gate-level circuit. And a plurality of units which can not be combined are obtained through non-causal division and are independently simulated in parallel.

The above is only a part or preferred embodiment of the present invention, and neither the text nor the drawings should limit the scope of the present invention, and all equivalent structural changes made by the present specification and the contents of the drawings or the related technical fields directly/indirectly using the present specification and the drawings are included in the scope of the present invention.

Claims

1. A method of non-causal circuit partitioning, comprising:

step S1: converting the gate-level circuit into a directed graph, and storing data by using a structure body;

2. The method of non-causal circuit partitioning of claim 1, wherein said converting said gate level circuit into a directed graph comprises:

3. The method of non-causal circuit partitioning of claim 1, wherein said structure is G, comprising at least 7 parts, g.name, g.matrix, g.input.name, g.input.matrix, g.output.name, g.output.matrix, g.cost;

the name stores the name of each node of the graph;

the G.matrix stores a adjacency matrix of the directed graph;

the g.input.name stores the name of the external input to the directed graph;

the g.output.name stores a name of an output to the outside of the graph;

cost stores the cost of each node in the graph.

4. The method of non-causal circuit partitioning as claimed in claim 1, wherein said searching for a set of output nodes from the structure, V, that have outputs to the outside comprises:

5. The method of non-causal circuit partitioning according to claim 1, wherein said initially partitioning a directed graph into a plurality of primary cells according to an exploration result comprises:

and sequentially carrying out depth-first exploration from the output nodes in the set V, storing all nodes obtained by each exploration, dividing each exploration into one primary unit, and counting the ith primary unit as M { i }.

6. Method of non-causal circuit partitioning according to claim 1, wherein said merging requirement is: the minimum number a of the same nodes required by combination between any two units is less than or equal to the number b of the same nodes actually required by combination between any two units.

7. The method of non-causal circuit partitioning of claim 1, wherein said step S5 further comprises:

step S51: inputting primary unit s1, primary unit s2, and similar scale per;

8. The method of non-causal circuit partitioning as set forth in claim 1, further comprising, after entering into performing a merge operation:

step S55: sequentially judging the similarity of the primary unit s1 and all the other units, and merging when the similarity meets the preset requirement;

9. The method of non-causal circuit partitioning of claim 1, wherein said reselecting primary cells, sequentially comparing all cells of non-compared primary comprising:

and (3) setting the total unit number as S, reselecting the (i + 1) th primary unit when the primary unit detected last time is the ith primary unit, and comparing with the rest primary units which are not compared until the reselected unit number i +1 is equal to the total unit number S.

10. Method for parallel simulation of gate level circuits, characterized in that it is divided by the method for non-causal circuit division according to any of claims 1 to 9.