CN114578625B - Liquid crystal display device - Google Patents
Liquid crystal display device Download PDFInfo
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- CN114578625B CN114578625B CN202210248850.8A CN202210248850A CN114578625B CN 114578625 B CN114578625 B CN 114578625B CN 202210248850 A CN202210248850 A CN 202210248850A CN 114578625 B CN114578625 B CN 114578625B
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Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
Abstract
The invention provides a liquid crystal display device, which comprises an upper substrate, a lower substrate and a liquid crystal layer arranged between the upper substrate and the lower substrate; the lower substrate comprises a lower glass substrate, a thin film transistor structure arranged between the lower glass substrate and the liquid crystal layer, an organic flat layer arranged between the thin film transistor structure and the liquid crystal layer, and a pixel electrode arranged between the organic flat layer and the liquid crystal layer, wherein the thin film transistor structure comprises a polysilicon layer, a first insulating layer, a first common electrode, a passivation layer and a metal layer which are sequentially arranged from the lower glass substrate towards one side of the organic flat layer; the polysilicon layer has conductivity after being heavily doped to the parts facing the source electrode and the drain electrode. The liquid crystal display device solves the problems that the potential retention rate of a pixel electrode is insufficient due to the fact that the storage capacitance is too small, and the voltage of the pixel electrode is obviously reduced due to the electric leakage of a thin film transistor in the prior art, so that the working performance of the display device is affected.
Description
Technical Field
The invention belongs to the technical field of liquid crystal display, and particularly relates to a liquid crystal display device.
Background
The liquid crystal display device comprises a transmission type liquid crystal display device and a reflection type liquid crystal display device, wherein the transmission type liquid crystal display device takes backlight as a light source, and a pixel electrode of an array substrate and a liquid crystal box form a light valve for controlling light to realize display pictures. The reflective liquid crystal display device mainly uses a front light source or external natural light as a light source, and a reflective electrode made of metal or other materials with good reflective characteristics, such as a Pixel electrode, is arranged on an array substrate, and is suitable for being used in places with strong external light sources for displaying pictures by reflecting the front light source or the external natural light, so that the energy consumption of the display device can be effectively reduced.
In the prior art, when the Pixel density of the liquid crystal display device becomes high and the Pixel size is smaller, due to the problem of wiring space, the data line, the scanning line and the Thin Film Transistor (TFT) switch occupy larger space, so that the space limitation of the storage capacitor can only be designed to be very small, the TFT is in a closed state after the Pixel charging is completed within the display time of one frame, at the moment, the TFT cannot be completely closed to have a certain leakage current, and due to the smaller storage capacitor, the storage requirement of the leakage current cannot be met, the Pixel electrode voltage drop is serious when the panel works, and the working performance of the device is greatly influenced.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a liquid crystal display device, which is used for solving the technical problems of the prior art that the liquid crystal display device generates Pixel electrode voltage drop due to the influence of TFT leakage current due to smaller storage capacitance.
The invention provides a liquid crystal display device, which comprises an upper substrate, a lower substrate and a liquid crystal layer arranged between the upper substrate and the lower substrate, wherein the lower substrate comprises a lower glass substrate, a thin film transistor structure arranged between the lower glass substrate and the liquid crystal layer, an organic flat layer arranged between the thin film transistor structure and the liquid crystal layer, and a pixel electrode arranged between the organic flat layer and the liquid crystal layer, and the thin film transistor structure comprises a polysilicon layer, a first insulating layer, a first common electrode, a passivation layer and a metal layer which are sequentially arranged from the lower glass substrate towards one side of the organic flat layer;
the thin film transistor structure comprises a pixel electrode, a polysilicon layer, a metal layer, a thin film transistor structure and a metal layer, wherein the metal layer comprises a source electrode and a drain electrode, the source electrode is electrically connected with the polysilicon layer, the drain electrode is electrically connected with the pixel electrode and the polysilicon layer, the polysilicon layer has conductivity after being heavily doped opposite to the source electrode and the drain electrode, the thin film transistor structure further comprises a grid electrode arranged between the source electrode and the drain electrode, and the grid electrode and the metal layer are arranged in different layers;
an overlapping region between the heavily doped portion of the polysilicon layer and the first common electrode forms a first storage capacitor, and an overlapping region between the first common electrode and the drain electrode forms a second storage capacitor.
Compared with the prior art, the invention has the beneficial effects that: the polysilicon layer is made to have conductivity after being heavily doped, so that the first insulating layer is used as a medium to form a first storage capacitor, the passivation layer is used as a medium to form a second storage capacitor, the capacity of the storage capacitor is increased, the serious Pixel electrode voltage drop caused by TFT leakage current influence is avoided, the working performance of the device is ensured, and the technical problem that the TFT leakage current influence generates the Pixel electrode voltage drop due to the fact that the storage capacitor is smaller in a liquid crystal display device in the prior art is solved.
Preferably, the thin film transistor structure further includes a second common electrode and a second insulating layer sequentially disposed from a side of the organic planarization layer away from the pixel electrode, an overlapping region between the second common electrode and the drain electrode forms a third storage capacitor, and an overlapping region between the pixel electrode and the second common electrode forms a fourth storage capacitor.
Preferably, the thin film transistor structure further includes a second common electrode and a second insulating layer sequentially disposed from the organic planarization layer toward one side of the pixel electrode, an overlapping region between the drain electrode and the second common electrode forms a third storage capacitor, and an overlapping region between the second common electrode and the pixel electrode forms a fourth storage capacitor.
Preferably, the source electrode and the drain electrode sequentially penetrate through the passivation layer and the first insulating layer respectively through a pin, and the pixel electrode sequentially penetrates through the organic flat layer, the second common electrode and the second insulating layer to be connected with the drain electrode.
Preferably, the source electrode and the drain electrode sequentially penetrate through the passivation layer and the first insulating layer respectively through a pin, and the pixel electrode sequentially penetrates through the second insulating layer, the second common electrode and the organic flat layer through a pin to be connected with the drain electrode.
Preferably, the material of the second insulating layer is one of silicon dioxide or silicon nitride.
Preferably, the liquid crystal layer is an ECB type arrangement.
Preferably, the lower substrate further comprises a buffer layer, and the buffer layer is arranged between the lower glass substrate and the polysilicon layer.
Preferably, the surfaces of the liquid crystal layer facing the upper substrate and the lower substrate are respectively provided with a liquid crystal alignment layer.
Preferably, the upper substrate includes an upper glass substrate and a third common electrode disposed from the upper glass substrate toward the liquid crystal layer side.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a circuit diagram of a prior art liquid crystal display device;
fig. 2 is a block diagram of a liquid crystal display device according to a first embodiment of the present invention;
fig. 3 is a block diagram of a liquid crystal display device according to a second embodiment of the present invention;
FIG. 4 is an equivalent circuit diagram of a liquid crystal display device according to a second embodiment of the present invention;
FIG. 5 is a graph showing the voltage variation of the pixel electrode according to the second embodiment of the present invention;
fig. 6 is a structural diagram of a liquid crystal display device in a third embodiment of the present invention.
Reference numerals illustrate:
10. an upper substrate;
11. a top glass substrate; 12. a third common electrode;
20. a liquid crystal layer;
30. a lower substrate;
31. a lower glass substrate; 32. a buffer layer; 33. a polysilicon layer; 34. a first insulating layer 35, a first common electricity; 36. a passivation layer; 371. a source electrode; 372. a drain electrode; 38. an organic planarization layer; 39. a pixel electrode; 40. a gate;
50. a second insulating layer; 60. a second common electrode;
70. a liquid crystal alignment layer.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and intended to illustrate embodiments of the invention and should not be construed as limiting the invention.
In the description of the embodiments of the present invention, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the embodiments of the present invention and simplify description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless explicitly defined otherwise.
In the embodiments of the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured" and the like are to be construed broadly and include, for example, either permanently connected, removably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the embodiments of the present invention will be understood by those of ordinary skill in the art according to specific circumstances.
In the prior art, when the Pixel density of the liquid crystal display device becomes high and the Pixel size is smaller, the data line, the scanning line and the TFT switch occupy larger space due to the problem of wiring space, so that the space limitation of the storage capacitor can only be designed to be very small.
In addition, referring to fig. 1, an equivalent circuit diagram of a liquid crystal display device in the prior art is shown, in which Date signals, gate signals and Pixel electrodes form parasitic capacitances Cdp and Cgp, and signal crosstalk is generated to the Pixel electrodes when the Date and Gate signals jump, so as to affect the stability of the device. To ameliorate such problems, the present invention is illustrated by the following specific examples. The specific examples of the present invention are not limited to the examples listed below.
Example 1
Referring to fig. 2, a liquid crystal display device according to a first embodiment of the invention is shown, the liquid crystal display device includes an upper substrate 10, a lower substrate 30, and a liquid crystal layer 20 disposed therebetween, the upper substrate 10 includes an upper glass substrate 11 and a third common electrode 12 disposed from the upper glass substrate 11 toward one side of the liquid crystal layer 20.
The lower substrate 30 includes a lower glass substrate 31, a thin film transistor structure disposed between the lower glass substrate 31 and the liquid crystal layer 20, an organic planarization layer 38 disposed between the thin film transistor structure and the liquid crystal layer 20, and a pixel electrode 39 disposed between the organic planarization layer 38 and the liquid crystal layer 20, and the thin film transistor structure includes a polysilicon layer 33, a first insulating layer 34, a first common electrode 35, a passivation layer 36, and a metal layer sequentially disposed from the lower glass substrate 31 toward the organic planarization layer 38.
The metal layer includes a source electrode 371 and a drain electrode 372, the source electrode 371 is electrically connected with the polysilicon layer 33, the drain electrode 372 is electrically connected with the pixel electrode 39 and the polysilicon layer 33, the polysilicon layer 33 has conductivity after being heavily doped to the source electrode 371 and the drain electrode 372, the thin film transistor structure further includes a gate 40 arranged between the source electrode 371 and the drain electrode 372, and the gate 40 and the metal layer are in different layers.
An overlapping region between the heavily doped portion of the polysilicon layer 33 and the first common electrode 35 forms a first storage capacitor, and an overlapping region between the first common electrode 35 and the drain electrode 372 forms a second storage capacitor.
Specifically, in fig. 2, the n+ portion of the polysilicon layer 33 represents a heavily doped portion, the n-portion represents a lightly doped portion, and the n-portion represents an undoped portion, wherein the lightly doped portion is used to reduce the TFT off-state current, the highly doped portion is used to increase the TFT on-state current, and the undoped portion retains the semiconductor characteristics. It should be noted that, in practical applications, the gate electrode 40 needs to be disposed first, and the first common electrode 35 is disposed after the doping process, so that the portion of the polysilicon layer 33 opposite to the first common electrode 35 can be heavily doped.
It can be appreciated that by heavily doping the polysilicon layer 33 and then making it conductive, the first insulating layer 34 is used as a medium to form a first storage capacitor, and the passivation layer 36 is used as a medium to form a second storage capacitor, so that the capacity of the storage capacitor is increased, the influence of TFT leakage current on the generation of severe Pixel electrode voltage drop is avoided, and the working performance of the device is ensured.
Example 2
Referring to fig. 3, a liquid crystal display device according to a second embodiment of the present invention includes an upper substrate 10, a lower substrate 30, and a liquid crystal layer 20 disposed therebetween, wherein the upper substrate 10 includes an upper glass substrate 11 and a third common electrode 12 disposed from the upper glass substrate 11 toward one side of the liquid crystal layer 20;
the lower substrate 30 includes a lower glass substrate 31, a thin film transistor structure disposed between the lower glass substrate 31 and the liquid crystal layer 20, an organic planarization layer 38 disposed between the thin film transistor structure and the liquid crystal layer 20, and a pixel electrode 39 disposed between the organic planarization layer 38 and the liquid crystal layer 20, wherein the thin film transistor structure includes a polysilicon layer 33, a first insulating layer 34, a first common electrode 35, a passivation layer 36, and a metal layer sequentially disposed from the lower glass substrate 31 toward the organic planarization layer 38;
the polysilicon layer 33 is heavily doped and has conductivity, the metal layer includes a source electrode 371 and a drain electrode 372, the source electrode 371 is electrically connected with the polysilicon layer 33, the drain electrode 372 is electrically connected with the pixel electrode 39 and the polysilicon layer 33, the thin film transistor structure further includes a gate 40 disposed between the source electrode 371 and the drain electrode 372, and the gate 40 and the metal layer are in different layers;
an overlapping region between the polysilicon layer 33 and the first common electrode 35 forms a first storage capacitor, and an overlapping region between the first common electrode 35 and the drain electrode 372 forms a second storage capacitor.
The thin film transistor structure further includes a second common electrode 60 and a second insulating layer 50 sequentially disposed from the organic planarization layer 38 away from the pixel electrode 39, an overlapping region between the second common electrode 60 and the drain electrode 372 forms a third storage capacitor, and an overlapping region between the pixel electrode 39 and the second common electrode 60 forms a fourth storage capacitor. The material of the second insulating layer 50 is one of silicon dioxide or silicon nitride.
It should be explained that, the present invention uses Poly-Si (polysilicon layer 33) having conductivity after being heavily doped, and uses the Poly-Si layer as one electrode of the storage capacitor, and uses ITO (first common electrode 35 electrode) as common electrode above the heavily doped Poly-Si after the gate electrode 40 is heavily doped; a PV layer (second insulating layer 50) and an ITO (Metal) layer (second common electrode 60) are designed between the Metal layer and the organic planarization layer 38, the ITO (Metal) layer giving a common signal.
Wherein, heavily doped Poly-Si (polysilicon layer 33) and ITO (first common electrode 35) are used as upper and lower electrodes, and GI (first insulating layer 34) is used as a dielectric layer to form Cst1 (first storage capacitor); ITO (first common electrode 35) and drain electrode 372 form Cst2 (second storage capacitor), the medium is ILD (passivation layer 36); a PV layer (second insulating layer 50) and an ITO (Metal) layer (second common electrode 60) are designed between the Metal layer and the organic planarization layer 38, the ITO (Metal) layer gives a common signal, the Metal and the ITO (Metal) form Cst3 (third storage capacitor), the medium of which is the PV layer (second insulating layer 50) can form a larger capacitor, and the ITO (Metal) layer (second common electrode 60) and the pixel (pixel electrode 39) form Cst4 (fourth storage capacitor), the medium of which is the organic planarization layer 38. Cst=cst1+cst2+cst3+cst4, and Cst is further increased on the basis of original cst=cst1+cst2, so that the problem that the normal use of the device is affected by voltage drop generated by TFT leakage current is solved.
Further, the source electrode 371 and the drain electrode 372 are respectively connected to the polysilicon layer 33 through the passivation layer 36 and the first insulating layer 34 in sequence, and the pixel electrode 39 is connected to the drain electrode 372 through the organic planarization layer 38, the second common electrode 60 and the second insulating layer 50 in sequence. In this embodiment, the outer diameter of the pin gradually decreases towards the direction of the lower glass substrate 31 to form an inverted cone structure, and it can be appreciated that the inverted cone structure design has higher safety in the actual manufacturing process. In specific practice, the working mechanism of the phase modulator is as follows: when the voltages of the gates 40 are different, the free electron concentration of p-Si under the gates 40 is different, and the higher the voltage of the gates 40 is in a certain range, the higher the free electron concentration of p-Si is, and the larger the current flowing to the drain 372 from the source 371 is; the source electrode 371 is a voltage signal to be written, and the drain electrode 372 is connected to the pixel electrode 39 to channel the source electrode 371 to the pixel electrode 39, and the on/off or on state of the thin film transistor is controlled by the voltage of the control gate 40.
Further, the pixel electrode 39 includes silver metal having a single-layer structure. Specifically, a reflection area is formed on the corresponding upper surface, and when no voltage is applied, the phase retardation of the light passing through the reflection area is the largest, and when the voltage is applied by the reflection electrode, the liquid crystal layer 20 in the reflection area generates a vertical deflection angle, the phase retardation of the light passing through the reflection area becomes smaller, and the higher the voltage, the larger the liquid crystal vertical deflection angle, and the smaller the phase retardation.
Referring to fig. 3 to 5, in this embodiment, cdc and Cgc are formed by adding the second insulating layer 50 and the second common electrode 60, which can shield the coupling effect of the signal jump of Date and Gate on the pixel electrode 39, increase Cst, and reduce the voltage drop caused by the influence of the leakage current on the pixel electrode 39 in the TFT off state, thereby improving the working performance of the device.
It should be noted that Cdc refers to a parasitic capacitance formed between the source electrode 371 and the second common electrode 60 by 50 as a medium, and Cgc refers to a parasitic capacitance formed between the gate electrode 40 and the second common electrode 60 by the passivation layer 36 and the second insulating layer 50 as a medium.
Preferably, the materials of the gate electrode 40, the common electrode, the source electrode 371 and the drain electrode 372 are alloy metals of titanium/aluminum/titanium in sequence from the bottom layer to the top layer; the storage capacitor is to prevent the thin film transistor from leaking when the thin film transistor is turned off, so that the voltage of the pixel electrode 39 is maintained in the desired voltage range.
Further, the lower substrate 30 further includes a buffer layer 32, and the buffer layer 32 is disposed between the lower glass substrate 31 and the polysilicon layer 33. The buffer layer 32 is attached to the lower glass substrate 31 to contact the polysilicon layer 33, so as to protect the lower glass substrate 31 in the presence of a strong external force.
Further, the surfaces of the liquid crystal layer 20 facing the upper substrate 10 and the lower substrate 30 are respectively provided with a liquid crystal alignment layer 70. In this embodiment, the main components of the liquid crystal alignment layer 70 are polyimide and DMA; of course, the main component of the liquid crystal alignment layer 70 of other embodiments may be one of polyimide and NMP, polyimide and BC. The solid component of the liquid crystal alignment layer 70 is a small molecular compound in the stock solution, and generates polymerization reaction at high temperature to form a long-chain macromolecular solid polymer polyamide with a plurality of branched chains, wherein the included angle between the branched chains and the main chain in the polymer molecule is the so-called pretilt angle of the guide layer, the acting force between the branched chain group of the polymer and the liquid crystal molecule is stronger, and the liquid crystal alignment layer has an anchoring effect on the liquid crystal molecule, so that the liquid crystal can be aligned in the pretilt angle direction. In the specific process, a layer of the liquid crystal alignment layer 70 is coated on one side of the upper substrate 10 and one side of the lower substrate 30, which correspond to each other, a circle of frame sealing glue is coated on the glass edge of the display area of the lower substrate 30 after the liquid crystal alignment layer 70 is rubbed or optically aligned, liquid crystal is dripped on the liquid crystal alignment layer 70 in the frame sealing glue, the upper substrate 10 and the lower substrate 30 are aligned and attached under a vacuum environment, and the frame sealing glue is cured under the condition of ultraviolet illumination setting and heating adjustment, so as to form the glass-based liquid crystal phase modulation device.
Further, the liquid crystal layer 20 employs a positive liquid crystal. In this embodiment, the liquid crystal layer 20 is an ECB type liquid crystal (electrically controlled birefringence type liquid crystal), and the liquid crystal cell satisfies Δnd > 2pi. When the ECB type liquid crystal display device is powered on, the angle θ between the long axis of the liquid crystal molecules and the electric field changes due to the voltage, so that the birefringence of the liquid crystal cell changes. When linearly polarized light is incident on the cell, different phase delays are formed at different birefringence, and the phase modulator thus has a phase modulation capability.
It should be explained that the ECB type liquid crystal is a color liquid crystal that can display a plurality of colors by voltage control. According to the different internal structure principles, ECB is divided into three types of vertical alignment liquid crystal (DAP type), parallel alignment mode and LB film orientation mixed alignment nematic (HAN type), wherein the DAP type liquid crystal is formed by aligning nematic liquid crystal with negative dielectric anisotropy perpendicular to the surface of a liquid crystal box; the parallel arrangement mode adopts a parallel orientation liquid crystal box in which the long axes of nematic liquid crystal molecules with positive dielectric anisotropy are arranged along the parallel surface of the substrate; the HAN type liquid crystal is composed of nematic liquid crystals having positive dielectric anisotropy, one side of which is aligned perpendicularly to the cell surface and the other side of which is aligned parallel to the cell surface.
In summary, the polysilicon layer 33 is heavily doped and then made conductive, so that the first insulating layer 34 is used as a medium to form a first storage capacitor, the passivation layer 36 is used as a medium to form a second storage capacitor, the second insulating layer 50 is used as a medium to form a third storage capacitor, and the organic planarization layer 38 is used as a medium to form a fourth storage capacitor, so that the capacity of the storage capacitor is increased, the Pixel electrode voltage drop caused by the TFT leakage current is avoided, the working performance of the device is ensured, and the technical problem that the Pixel electrode voltage drop is caused by the TFT leakage current due to the smaller storage capacitor in the liquid crystal display device in the prior art is solved.
Example 3
Referring to fig. 6, a liquid crystal display device according to a third embodiment of the present invention includes an upper substrate 10, a lower substrate 30, and a liquid crystal layer 20 disposed therebetween, wherein the upper substrate 10 includes an upper glass substrate 11 and a third common electrode 12 disposed from the upper glass substrate 11 toward one side of the liquid crystal layer 20;
the lower substrate 30 includes a lower glass substrate 31, a thin film transistor structure disposed between the lower glass substrate 31 and the liquid crystal layer 20, an organic planarization layer 38 disposed between the thin film transistor structure and the liquid crystal layer 20, and a pixel electrode 39 disposed between the organic planarization layer 38 and the liquid crystal layer 20, wherein the thin film transistor structure includes a polysilicon layer 33, a first insulating layer 34, a first common electrode 35, a passivation layer 36, and a metal layer sequentially disposed from the lower glass substrate 31 toward the organic planarization layer 38;
the polysilicon layer 33 is heavily doped and has conductivity, the metal layer includes a source electrode 371 and a drain electrode 372, the source electrode 371 is electrically connected with the polysilicon layer 33, the drain electrode 372 is electrically connected with the pixel electrode 39 and the polysilicon layer 33, the thin film transistor structure further includes a gate 40 disposed between the source electrode 371 and the drain electrode 372, and the gate 40 and the metal layer are in different layers; an overlapping region between the polysilicon layer 33 and the first common electrode 35 forms a first storage capacitor, and an overlapping region between the first common electrode 35 and the drain electrode 372 forms a second storage capacitor.
Specifically, the thin film transistor structure further includes a second common electrode 60 and a second insulating layer 50 sequentially disposed from the organic planarization layer 38 toward the pixel electrode 39 side, an overlapping region between the drain electrode 372 and the second common electrode 60 forms a third storage capacitance, and an overlapping region between the second common electrode 60 and the pixel electrode 39 forms a fourth storage capacitance. The material of the second insulating layer 50 is one of silicon dioxide or silicon nitride. In this embodiment, since the second insulating layer 50 and the second common electrode 60 are added to form Cdc and Cgc, the coupling influence of the signal transitions of Date and Gate on the pixel electrode 39 can be shielded, cst is increased, and the voltage drop caused by the influence of the leakage current on the pixel electrode 39 in the TFT off state is reduced, thereby improving the phase modulation capability of the device.
It should be explained that, the present invention uses Poly-Si (polysilicon layer 33) having conductivity after being heavily doped, and uses the Poly-Si layer as one electrode of the storage capacitor, and uses ITO (first common electrode 35 electrode) as common electrode above the heavily doped Poly-Si after the gate electrode 40 is heavily doped; a PV layer (second insulating layer 50) and an ITO (Metal) layer (second common electrode 60) are designed between the Metal layer and the organic planarization layer 38, the ITO (Metal) layer giving a common signal.
Wherein, heavily doped Poly-Si (polysilicon layer 33) and ITO (first common electrode 35) are used as upper and lower electrodes, and GI (first insulating layer 34) is used as a dielectric layer to form Cst1 (first storage capacitor); ITO (first common electrode 35) and drain electrode 372 form Cst2 (second storage capacitor), the medium is ILD (passivation layer 36); a PV layer (second insulating layer 50) and an ITO (Metal) layer (second common electrode 60) are designed between the Metal layer and the organic planarization layer 38, the ITO (Metal) layer gives a common signal, the Metal and ITO (Metal) form Cst3 (third storage capacitor), the medium is the organic planarization layer 38, the ITO (Metal) layer (second common electrode 60) and pixel (pixel electrode 39) form Cst4 (fourth storage capacitor), and the medium is the PV layer (second insulating layer 50) form a larger capacitor. Cst=cst1+cst2+cst3+cst4, and Cst is further increased on the basis of original cst=cst1+cst2, so that the problem that the normal use of the device is affected by voltage drop generated by TFT leakage current is solved.
Further, the source electrode 371 and the drain electrode 372 are respectively connected to the polysilicon layer 33 by sequentially passing through the passivation layer 36 and the first insulating layer 34 through a lead, the pixel electrode 39 is connected to the drain electrode 372 by sequentially passing through the second insulating layer 50, the second common electrode 60 and the organic flat layer 38 through a lead, in this embodiment, the outer diameter of the lead gradually decreases towards the direction of the lower glass substrate 31 to form an inverted cone structure, and it can be understood that the inverted cone structure design has higher safety in the actual manufacturing process. In specific practice, the working mechanism of the phase modulator is as follows: when the voltages of the gates 40 are different, the free electron concentration of p-Si under the gates 40 is different, and the higher the voltage of the gates 40 is in a certain range, the higher the free electron concentration of p-Si is, and the larger the current flowing to the drain 372 from the source 371 is; the source electrode 371 is a voltage signal to be written, and the drain electrode 372 is connected to the pixel electrode 39 to channel the source electrode 371 to the pixel electrode 39, and the on/off or on state of the thin film transistor is controlled by the voltage of the control gate 40.
Further, the pixel electrode 39 may comprise an alloy metal of a multi-layer structure, such as one of titanium/aluminum, titanium/aluminum/titanium in order from bottom layer to top layer. Specifically, a reflection area is formed on the corresponding upper surface, and when no voltage is applied, the phase retardation of the light passing through the reflection area is the largest, and when the voltage is applied by the reflection electrode, the liquid crystal layer 20 in the reflection area generates a vertical deflection angle, the phase retardation of the light passing through the reflection area becomes smaller, and the higher the voltage, the larger the liquid crystal vertical deflection angle, and the smaller the phase retardation.
Further, the materials of the gate electrode 40, the common electrode, the source electrode 371 and the drain electrode 372 may be alloy metals of molybdenum/aluminum/molybdenum in sequence from bottom layer to top layer. The purpose of the storage capacitor is to prevent leakage of the thin film transistor when the thin film transistor is turned off, so that the voltage of the pixel electrode 39 is maintained in the voltage range to be written.
Further, the lower substrate 30 further includes a buffer layer 32, and the buffer layer 32 is disposed between the lower glass substrate 31 and the polysilicon layer 33. The buffer layer 32 is attached to the lower glass substrate 31 to contact the polysilicon layer 33, so as to protect the lower glass substrate 31 in the presence of a strong external force.
Further, the surfaces of the liquid crystal layer 20 facing the upper substrate 10 and the lower substrate 30 are respectively provided with a liquid crystal alignment layer 70. In this embodiment, the main components of the liquid crystal alignment layer 70 are polyimide and DMA; of course, the main component of the liquid crystal alignment layer 70 of other embodiments may be one of polyimide and NMP, polyimide and BC. The solid component of the liquid crystal alignment layer 70 is a small molecular compound in the stock solution, and generates polymerization reaction at high temperature to form a long-chain macromolecular solid polymer polyamide with a plurality of branched chains, wherein the included angle between the branched chains and the main chain in the polymer molecule is the so-called pretilt angle of the guide layer, the acting force between the branched chain group of the polymer and the liquid crystal molecule is stronger, and the liquid crystal alignment layer has an anchoring effect on the liquid crystal molecule, so that the liquid crystal can be aligned in the pretilt angle direction. In the specific process, a layer of the liquid crystal alignment layer 70 is coated on one side of the upper substrate 10 and one side of the lower substrate 30, which correspond to each other, a circle of frame sealing glue is coated on the glass edge of the display area of the lower substrate 30 after the liquid crystal alignment layer 70 is rubbed or optically aligned, liquid crystal is dripped on the liquid crystal alignment layer 70 in the frame sealing glue, the upper substrate 10 and the lower substrate 30 are aligned and attached under a vacuum environment, and the frame sealing glue is cured under the condition of ultraviolet illumination setting and heating adjustment, so as to form the glass-based liquid crystal phase modulation device.
In summary, the polysilicon layer 33 is heavily doped and then made conductive, so that the first insulating layer 34 is used as a medium to form a first storage capacitor, the passivation layer 36 is used as a medium to form a second storage capacitor, the organic planarization layer 38 is used as a medium to form a third storage capacitor, and the second insulating layer 50 is used as a medium to form a fourth storage capacitor, thereby increasing the capacity of the storage capacitor, avoiding the serious Pixel electrode voltage drop caused by TFT leakage current influence, ensuring the working performance of the device, and solving the technical problem that the TFT leakage current influence causes the Pixel electrode voltage drop in the liquid crystal display device in the prior art due to smaller storage capacitor.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (6)
1. The liquid crystal display device comprises an upper substrate, a lower substrate and a liquid crystal layer arranged between the upper substrate and the lower substrate, and is characterized in that the lower substrate comprises a lower glass substrate, a thin film transistor structure arranged between the lower glass substrate and the liquid crystal layer, an organic flat layer arranged between the thin film transistor structure and the liquid crystal layer and a pixel electrode arranged between the organic flat layer and the liquid crystal layer, and the thin film transistor structure comprises a polycrystalline silicon layer, a first insulating layer, a first common electrode, a passivation layer and a metal layer which are sequentially arranged from the lower glass substrate towards one side of the organic flat layer;
the thin film transistor structure comprises a pixel electrode, a polysilicon layer, a metal layer, a thin film transistor structure and a metal layer, wherein the metal layer comprises a source electrode and a drain electrode, the source electrode is electrically connected with the polysilicon layer, the drain electrode is electrically connected with the pixel electrode and the polysilicon layer, the polysilicon layer has conductivity after being heavily doped opposite to the source electrode and the drain electrode, the thin film transistor structure further comprises a grid electrode arranged between the source electrode and the drain electrode, and the grid electrode and the metal layer are arranged in different layers;
an overlapping region between the heavily doped part of the polysilicon layer and the first common electrode forms a first storage capacitor, and an overlapping region between the first common electrode and the drain electrode forms a second storage capacitor;
the pixel electrode comprises silver metal with a single-layer structure;
the thin film transistor structure further comprises a second common electrode and a second insulating layer which are sequentially arranged from one side of the organic flat layer away from the pixel electrode, wherein an overlapping region between the second common electrode and the drain electrode forms a third storage capacitor, and an overlapping region between the pixel electrode and the second common electrode forms a fourth storage capacitor;
the source electrode and the drain electrode sequentially penetrate through the passivation layer and the first insulating layer respectively through a pin and are connected with the polysilicon layer, and the pixel electrode sequentially penetrates through the organic flat layer, the second public electrode and the second insulating layer through a pin and is connected with the drain electrode;
or, the thin film transistor structure further includes a second common electrode and a second insulating layer sequentially disposed from the organic planarization layer toward one side of the pixel electrode, an overlapping region between the drain electrode and the second common electrode forms a third storage capacitor, and an overlapping region between the second common electrode and the pixel electrode forms a fourth storage capacitor;
the source electrode and the drain electrode sequentially penetrate through the passivation layer and the first insulating layer respectively through a pin and are connected with the polysilicon layer, and the pixel electrode sequentially penetrates through the second insulating layer, the second common electrode and the organic flat layer through a pin and is connected with the drain electrode.
2. The liquid crystal display device according to claim 1, wherein the material of the second insulating layer is one of silicon dioxide or silicon nitride.
3. The liquid crystal display device of claim 1, wherein the liquid crystal layer is an Electrically Controlled Birefringence (ECB) arrangement.
4. The liquid crystal display device according to claim 1, wherein the lower substrate further comprises a buffer layer provided between the lower glass substrate and the polysilicon layer.
5. The liquid crystal display device according to claim 1, wherein surfaces of the liquid crystal layer facing the upper substrate and the lower substrate are respectively provided with a liquid crystal alignment layer.
6. The liquid crystal display device according to claim 1, wherein the upper substrate includes an upper glass substrate and a third common electrode provided from the upper glass substrate toward the liquid crystal layer side.
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| WO2003060603A1 (en) * | 2002-01-17 | 2003-07-24 | Iljin Diamond Co., Ltd | Thin film transistor substrate for liquid crystal display(lcd) and method of manufacturing the same |
| CN1573491A (en) * | 2003-05-30 | 2005-02-02 | 三星电子株式会社 | Thin film transistor array panel and liquid crystal display including the panel |
| CN2852392Y (en) * | 2005-11-12 | 2006-12-27 | 群康科技(深圳)有限公司 | Thin film transistor array substrate and its LCD |
| CN105652542A (en) * | 2016-01-25 | 2016-06-08 | 武汉华星光电技术有限公司 | Array substrate, liquid crystal display panel and liquid crystal display device |
| WO2017054271A1 (en) * | 2015-09-30 | 2017-04-06 | 深圳市华星光电技术有限公司 | Low-temperature poly-silicon tft substrate |
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| US7830346B2 (en) * | 2007-07-12 | 2010-11-09 | Au Optronics Corporation | Liquid crystal display panel with color washout improvement by scanning line coupling and applications of same |
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| WO2003060603A1 (en) * | 2002-01-17 | 2003-07-24 | Iljin Diamond Co., Ltd | Thin film transistor substrate for liquid crystal display(lcd) and method of manufacturing the same |
| CN1573491A (en) * | 2003-05-30 | 2005-02-02 | 三星电子株式会社 | Thin film transistor array panel and liquid crystal display including the panel |
| CN2852392Y (en) * | 2005-11-12 | 2006-12-27 | 群康科技(深圳)有限公司 | Thin film transistor array substrate and its LCD |
| WO2017054271A1 (en) * | 2015-09-30 | 2017-04-06 | 深圳市华星光电技术有限公司 | Low-temperature poly-silicon tft substrate |
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