CN114355681B - Optical phase control display device - Google Patents
Optical phase control display device Download PDFInfo
- Publication number
- CN114355681B CN114355681B CN202210085731.5A CN202210085731A CN114355681B CN 114355681 B CN114355681 B CN 114355681B CN 202210085731 A CN202210085731 A CN 202210085731A CN 114355681 B CN114355681 B CN 114355681B
- Authority
- CN
- China
- Prior art keywords
- electrode
- compensation
- layer
- pixel electrode
- pixel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Geometry (AREA)
- Liquid Crystal (AREA)
Abstract
The invention provides an optical phase control display device, which comprises an upper substrate, a lower substrate and a liquid crystal layer, wherein the lower substrate comprises a lower passivation layer, a plurality of first pixel electrodes and second pixel electrodes, and the first pixel electrodes and the second pixel electrodes are mutually staggered; the upper substrate comprises an upper glass substrate and a compensation structure, the compensation structure comprises an upper passivation layer, a plurality of first compensation electrodes and a plurality of second compensation electrodes, and the first compensation electrodes and the second compensation electrodes are arranged in a staggered manner; the first compensation electrode is arranged corresponding to the first pixel electrode, and the second compensation electrode is arranged corresponding to the second pixel electrode; the distance between the first compensation electrode and the first pixel electrode is consistent with the distance between the second compensation electrode and the second pixel electrode. By the method and the device, the technical problems of reduction of the phase control range of the pixel electrode and increase of power consumption caused by the requirement of higher requirements on chip driving voltage due to the phase difference of the adjacent two pixel electrodes caused by the passivation layer in the prior art are solved.
Description
Technical Field
The invention belongs to the technical field of optical phase control, and particularly relates to an optical phase control display device.
Background
The optical phase control display element can effectively improve the pixel transmittance by improving the pixel aperture ratio, the liquid crystal transmittance efficiency, the polarizer transmittance and the color filter transmittance; the pixel aperture ratio refers to the light transmittance, that is, the higher the pixel aperture ratio index is, the better the optical phase control effect is.
As shown in fig. 1, in order to increase the aperture ratio of the pixel, the adjacent first pixel electrode 141 and second pixel electrode 142 are typically disposed in different layers; when external light enters the optical phase control display device through the liquid crystal layer 20, is reflected by the first pixel electrode 141 and the second pixel electrode 142, and then exits the optical phase control display device through the liquid crystal layer 20, at this time, compared with the second pixel electrode 142, the external light passes through one passivation layer 14 more at the first pixel electrode 141, and when the liquid crystal deflection angles of the first pixel electrode 141 and the second pixel electrode 142 are consistent, the first pixel electrode 141 generates more phase difference phenomenon generated through the passivation layer 14 than the second pixel electrode 142 when light enters and reflects. In order to improve the phase difference phenomenon so that the phase control capability of the first pixel electrode 141 and the second pixel electrode 142 are consistent, a pixel driving method as shown in fig. 2 is generally adopted; as can be seen from fig. 2, the pixel voltage of the first pixel electrode 141 should be higher than the pixel voltage of the second pixel electrode 142, i.e. the driving voltage range of the pixel voltage of the first pixel electrode 141 should be larger than the driving voltage range of the pixel voltage of the second pixel electrode 142; therefore, the pixel voltage of the first pixel electrode 141 has a high requirement for the chip driving voltage range. However, it is difficult for a general chip to meet the requirement that the pixel voltage has a high requirement on the chip driving voltage, resulting in a decrease in the phase control range of the pixel electrode to affect the phase control capability of the entire optical phase control display device; in addition, the requirement of higher pixel voltage requirements for chip driving voltage also causes an increase in power consumption of the entire optical phase control display device.
Therefore, an effective solution has not been proposed for solving the technical problems of the prior art that the phase control range of the pixel electrode is reduced and the power consumption is increased due to the requirement of higher requirements on the chip driving voltage caused by the phase difference between the adjacent two pixel electrodes due to the passivation layer.
Disclosure of Invention
In order to solve the technical problems, the invention provides an optical phase control display device, wherein a compensation structure is arranged on an upper substrate, and the phase difference between two adjacent pixel electrodes due to a passivation layer in the prior art is avoided through the voltage difference between the compensation structures, so that the driving range of the pixel electrodes to the chip driving voltage is reduced.
The invention provides a technical scheme that an optical phase control display device comprises an upper substrate, a lower substrate and a liquid crystal layer arranged between the upper substrate and the lower substrate, wherein the lower substrate comprises a lower passivation layer, a plurality of first pixel electrodes and second pixel electrodes, the lower passivation layer comprises a first surface and a second surface which are opposite, the first pixel electrodes are embedded in the first surface, the second pixel electrodes are embedded in the second surface, and the first pixel electrodes and the second pixel electrodes are mutually staggered; the upper substrate comprises an upper glass substrate and a compensation structure arranged from the upper glass substrate towards one side of the liquid crystal layer;
the compensation structure comprises an upper passivation layer, a plurality of first compensation electrodes and a plurality of second compensation electrodes, wherein the upper passivation layer comprises a third surface and a fourth surface which are opposite to each other, the first compensation electrodes are embedded in the third surface, the second compensation electrodes are embedded in the fourth surface, and the first compensation electrodes and the second compensation electrodes are arranged in a staggered mode; the first compensation electrode and the first pixel electrode are correspondingly arranged, and the projection size of the first compensation electrode on the lower passivation layer is equal to that of the first pixel electrode or the error of the first compensation electrode and the first pixel electrode is less than 1%; the second compensation electrode is arranged corresponding to the second pixel electrode, and the projection size of the second compensation electrode on the lower passivation layer is equal to the second pixel electrode or the error of the second compensation electrode and the second pixel electrode is less than 1%; the distance between the first compensation electrode and the first pixel electrode is consistent with the distance between the second compensation electrode and the second pixel electrode, and the phase difference of the first pixel electrode and the second pixel electrode due to the lower passivation layer is compensated by respectively controlling the writing voltage signals to the first compensation electrode and the second compensation electrode and utilizing the voltage difference of the first compensation electrode and the second compensation electrode.
Compared with the prior art, the invention has the beneficial effects that: the method comprises the steps that a compensation structure comprising an upper passivation layer and a plurality of first compensation electrodes and second compensation electrodes which are arranged on the upper passivation layer in a staggered manner is arranged on an upper substrate, the first compensation electrodes and the first pixel electrodes are correspondingly arranged, the area size of the first compensation electrodes is consistent with or small in phase difference, the second compensation electrodes and the second pixel electrodes are correspondingly arranged, the area size of the second compensation electrodes is consistent with or small in phase difference, the distance between the first compensation electrodes and the first pixel electrodes and the distance between the second compensation electrodes are consistent, write-in voltage signals are respectively controlled by the first compensation electrodes and the second compensation electrodes, and the phase difference between the first pixel electrodes and the second pixel electrodes due to the fact that the second pixel electrodes are generated by the lower passivation layer is utilized, so that the amplitude value of the driving range of the pixel electrodes to chip driving voltage is reduced, the chip driving difficulty and the signal writing complexity degree are reduced, the phase control range and the capability of a phase controller are improved, and the driving power consumption of the phase controller is reduced.
Preferably, the first compensation electrodes are distributed in a rectangular array, and the second compensation electrodes are arranged opposite to the gaps between two adjacent first compensation electrodes.
Preferably, the lower substrate further comprises a lower glass substrate, a thin film transistor structure and an organic flat layer, wherein the thin film transistor structure and the organic flat layer are sequentially arranged from the lower glass substrate towards one side of the liquid crystal layer; the thin film transistor structure comprises a polysilicon layer, a gate insulating layer, a first metal layer, a dielectric layer and a second metal layer which are sequentially arranged from the lower glass substrate towards one side of the liquid crystal layer; and one side of the organic flat layer, which is away from the liquid crystal layer, covers the second metal layer.
Preferably, the polysilicon layer includes a semiconductor layer of a first thin film transistor disposed corresponding to the first pixel electrode and a semiconductor layer of a second thin film transistor disposed corresponding to the second pixel electrode; the first thin film transistor is used for controlling the voltage on the first pixel electrode, and the second thin film transistor is used for controlling the voltage on the second pixel electrode.
Preferably, the first metal layer includes a first gate electrode and a first common electrode disposed corresponding to the first pixel electrode, and a second gate electrode and a second common electrode disposed corresponding to the second pixel electrode.
Preferably, the second metal layer includes a first source electrode and a first drain electrode disposed corresponding to the first pixel electrode, and a second source electrode and a second drain electrode disposed corresponding to the second pixel electrode; the first grid electrode is arranged between the first source electrode and the first drain electrode, and the second grid electrode is arranged between the second source electrode and the second drain electrode; the overlapping area of the first drain electrode and the first common electrode forms a first storage capacitor, and the overlapping area of the second drain electrode and the second common electrode forms a second storage capacitor.
Preferably, the first pixel electrode is electrically connected with the first drain electrode through the organic flat layer by a pin, and the second pixel electrode is electrically connected with the second drain electrode through the organic flat layer by a pin; the first source electrode and the first drain electrode pass through the dielectric layer, the first metal layer and the gate insulating layer through pins and are electrically connected with the semiconductor layer of the first thin film transistor, and the second source electrode and the second drain electrode pass through the dielectric layer, the first metal layer and the gate insulating layer through pins and are electrically connected with the semiconductor layer of the second thin film transistor.
Preferably, the upper passivation layer, the lower passivation layer, the gate insulating layer and the dielectric layer are made of silicon dioxide or silicon nitride.
Preferably, the surfaces of the liquid crystal layer facing the upper substrate and the lower substrate are respectively provided with a liquid crystal alignment layer.
Preferably, the voltage of the first pixel electrode is higher than the voltage of the second pixel electrode.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a prior art optical phase control display device;
FIG. 2 is a schematic diagram of a pixel driving scheme of a prior art optical phase control display device;
FIG. 3 is a block diagram of an optical phase control display device according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating the shapes and arrangements of a first pixel electrode and a second pixel electrode according to an embodiment of the present invention;
FIG. 5 is a schematic diagram showing the shapes and arrangement of the first compensation electrode and the second compensation electrode according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of incident and emergent light paths of external light according to an embodiment of the present invention;
fig. 7 is a schematic diagram of pixel driving of an optical phase control display device according to an embodiment of the present invention.
Reference numerals illustrate:
10. a lower substrate;
11. a lower glass substrate;
12. a thin film transistor structure; 121. a polysilicon layer; 1211. a first thin film transistor; 1212. a second thin film transistor; 122. a gate insulating layer; 123. a first metal layer; 1231. a first gate; 1232. a first common electrode; 1233. a second gate; 1234. a second common electrode; 124. a dielectric layer; 125. a second metal layer; 1251. a first source electrode; 1252. a first drain electrode; 1253. a second source electrode; 1254. a second drain electrode;
13. an organic planarization layer;
14. a lower passivation layer; 141. a first pixel electrode; 142. a second pixel electrode;
20. a liquid crystal layer; 21. a liquid crystal alignment layer;
30. an upper substrate; 31. a top glass substrate; 32. a compensation structure; 321. an upper passivation layer; 322. a first compensation electrode; 323. and a second compensation electrode.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and intended to illustrate embodiments of the invention and should not be construed as limiting the invention.
In the description of the embodiments of the present invention, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the embodiments of the present invention and simplify description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless explicitly defined otherwise.
In the embodiments of the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured" and the like are to be construed broadly and include, for example, either permanently connected, removably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the embodiments of the present invention will be understood by those of ordinary skill in the art according to specific circumstances.
An optical phase control display device as shown in fig. 3 includes an upper substrate 30, a lower substrate 10, and a liquid crystal layer 20 disposed between the upper substrate 30 and the lower substrate 10. Further, the surfaces of the liquid crystal layer 20 facing the upper substrate 30 and the lower substrate 10 are respectively provided with a liquid crystal alignment layer 21. In this embodiment, the main components of the liquid crystal alignment layer 21 are polyimide and DMA; of course, the main component of the liquid crystal alignment layer of other embodiments may be one of polyimide and NMP, polyimide and BC. The solid component of the liquid crystal alignment layer 21 is a small molecular compound in the stock solution, and generates polymerization reaction at high temperature to form a long-chain macromolecular solid polymer polyamide with a plurality of branched chains, wherein the included angle between the branched chains and the main chain in the polymer molecule is the so-called pretilt angle of the guide layer, the acting force between the branched chain group of the polymer and the liquid crystal molecule is stronger, and the liquid crystal alignment layer has an anchoring effect on the liquid crystal molecule, so that the liquid crystal can be aligned in the pretilt angle direction. In the process of manufacturing the device, one side of the upper substrate 30 and one side of the lower substrate 10, which correspond to each other, are coated with the liquid crystal alignment layer 21, after the rubbing or photo-alignment process is performed on the liquid crystal alignment layer 21, a circle of frame sealing glue is coated on the glass edge of the display area of the lower substrate 10, liquid crystal is dripped on the liquid crystal alignment layer 21 in the frame sealing glue, the upper substrate 30 and the lower substrate 10 are aligned and attached under a vacuum environment, and the frame sealing glue is cured under the ultraviolet illumination setting and heating adjustment, so as to form the glass-based liquid crystal phase control device.
Further, the liquid crystal layer 20 employs a positive liquid crystal. In the present embodiment, the liquid crystal layer 20 is ECB type liquid crystal (electrically controlled birefringence type liquid crystal), and the liquid crystal cell satisfies Δ nd > 2pi. When the ECB type liquid crystal display device is electrified, the included angle theta between the long axes of liquid crystal molecules and the electric field changes due to different voltages, so that the birefringence of the liquid crystal box changes. When linearly polarized light impinges on the cell, different phase delays are formed at different birefringence, and the phase controller therefore has phase control capability.
It should be explained that the ECB type liquid crystal is a color liquid crystal that can display a plurality of colors by voltage control. According to the different internal structure principles, ECB is divided into three types of vertical alignment liquid crystal (DAP type), parallel alignment mode and LB film orientation mixed alignment nematic (HAN type), wherein the DAP type liquid crystal is formed by aligning nematic liquid crystal with negative dielectric anisotropy perpendicular to the surface of a liquid crystal box; the parallel arrangement mode adopts a parallel orientation liquid crystal box in which the long axes of nematic liquid crystal molecules with positive dielectric anisotropy are arranged along the parallel surface of the substrate; the HAN type liquid crystal is composed of nematic liquid crystals having positive dielectric anisotropy, one side of which is aligned perpendicularly to the cell surface and the other side of which is aligned parallel to the cell surface.
As shown in fig. 3, the lower substrate 10 includes a lower passivation layer 14, and a plurality of first pixel electrodes 141 and second pixel electrodes 142 embedded on two surfaces of the lower passivation layer 14, wherein the first pixel electrodes 141 and the second pixel electrodes 142 are staggered with each other. In this embodiment, as shown in fig. 4, the patterns and the arrangement manners of the first pixel electrode 141 and the second pixel electrode 142 are shown, wherein reference numeral 1 is the first pixel electrode 141, reference numeral 2 is the second pixel electrode 142, the first pixel electrode 141 is distributed in a rectangular array, and the second pixel electrode 142 is opposite to the gap between two adjacent first pixel electrodes 141. Specifically, the first pixel electrode 141 and the second pixel electrode 142 are both square structures, and the two opposite surfaces of the lower passivation layer 14 are provided with limiting grooves for respectively accommodating the first pixel electrode 141 and the second pixel electrode 142, so that the surfaces of the first pixel electrode 141 and the second pixel electrode 142 and the surface of the lower passivation layer 14 on two sides of the lower passivation layer 14 are located on the same horizontal plane, and the reflection effect is ensured. In addition, the limiting groove may be used to limit the position between the first pixel electrode 141 and the second pixel electrode 142, so that the adjacent first pixel electrode 141 and the adjacent second pixel electrode 142 are alternately arranged, and the gap between the adjacent pixel electrodes only needs to consider the alignment deviation problem (about less than 1 um) in the process, so as to ensure that no overlap is generated between the first pixel electrode 141 and the second pixel electrode 142 after the process, thereby realizing the maximum improvement of the aperture opening ratio.
Further, the first pixel electrode 141 and the second pixel electrode 142 each include silver metal having a single-layer structure. Of course, the pixel electrode of other embodiments may also include a multi-layered structure of alloy metal, such as one of titanium/aluminum, titanium/aluminum/titanium in order from bottom layer to top layer. Specifically, a reflection area is formed on the corresponding upper surface, under the condition that no voltage is applied, the phase delay of light passing through the reflection area is maximum, when the voltage is applied by the reflection electrode, the liquid crystal layer in the reflection area generates a vertical deflection angle, the phase delay of the light passing through the reflection area becomes smaller, the higher the voltage is, the larger the liquid crystal vertical deflection angle is, and the smaller the phase delay is.
As shown in fig. 3, the upper substrate 30 includes an upper glass substrate 31 and a compensation structure 32 disposed from the upper glass substrate 31 toward the liquid crystal layer 20; the compensation structure 32 includes an upper passivation layer 321, and a plurality of first compensation electrodes 322 and second compensation electrodes 323 embedded on two surfaces of the upper passivation layer 321, wherein the first compensation electrodes 322 and the second compensation electrodes 323 are staggered with each other. In this embodiment, as shown in fig. 5, the patterns and the arrangement manners of the first compensation electrode 322 and the second compensation electrode 323 are shown, wherein the first compensation electrode 322 is marked 1, the first compensation electrode 322 is marked 2, the second compensation electrode 323 is distributed in a rectangular array, and the first compensation electrode 322 is arranged opposite to the gaps between two adjacent second compensation electrodes 323. Specifically, the first compensation electrode 322 and the second compensation electrode 323 are both square structures, and the opposite surfaces of the upper passivation layer 321 are provided with limiting grooves for respectively accommodating the first compensation electrode 322 and the second compensation electrode 323, so that the surfaces of the first compensation electrode 322 and the second compensation electrode 323 which are arranged on both sides of the upper passivation layer 321 and the surface of the upper passivation layer 321 are located on the same horizontal plane, thereby ensuring the reflection effect. In addition, the limiting groove can be used for limiting the position between the first compensation electrode 322 and the second compensation electrode 323, so that the adjacent first compensation electrode 322 and the adjacent second compensation electrode 323 are alternately arranged, and the gap between the adjacent compensation electrodes only needs to consider the alignment deviation problem (about less than 1 um) in the process, so that no overlap is generated between the first compensation electrode 322 and the second compensation electrode 323 after the process. It should be noted that two adjacent compensation electrodes of the same layer form an electrical connection at their corresponding corners.
Further, the first compensation electrode 322 is disposed corresponding to the first pixel electrode 141, and the projection size of the first compensation electrode 322 on the lower passivation layer 14 is equal to the first pixel electrode 141 or the error of the first compensation electrode 322 and the first pixel electrode is smaller than a preset value; the second compensation electrode 323 is disposed corresponding to the second pixel electrode 142, and the projection size of the second compensation electrode 323 on the lower passivation layer 14 is equal to the second pixel electrode 142 or the error of the second compensation electrode 323 and the second pixel electrode is smaller than a preset value; the distance between the first compensation electrode 322 and the first pixel electrode 141 is consistent with the distance between the second compensation electrode 323 and the second pixel electrode 142; in this embodiment, the preset value is 1%. As shown in fig. 6, when external light enters the phase controller through the upper substrate 30 and the liquid crystal layer 20, and is reflected by the first pixel electrode 141 and the second pixel electrode 142 and exits the phase controller through the liquid crystal layer 20 and the upper substrate 30, the first pixel electrode 141 and the second pixel electrode 142 have an optical path length larger than that of the first pixel electrode 141 by one passivation layer, and when the liquid crystal deflection angles of the first pixel electrode 141 and the second pixel electrode 142 are identical, the first pixel electrode 141 generates a phase difference between the incident light and the reflected light through the passivation layer more than the first pixel electrode 142. Therefore, in this embodiment, the writing voltage signals of the first pixel electrode 141 and the second pixel electrode 142 are respectively written by controlling the writing corresponding to the first compensation electrode 322 and the second compensation electrode 323, and the phase difference generated by the passivation layer of the first pixel electrode 141 and the second pixel electrode 142 is compensated by using the voltage difference between the first compensation electrode 322 and the second compensation electrode 323, and meanwhile, the voltages of the first pixel electrode 141 and the second pixel electrode 142 are consistent, so that the amplitude value of the driving range of the chip driving voltage of the pixel electrode, the chip driving difficulty and the signal writing complexity are reduced, and the phase control range and the device capability are improved.
FIG. 7 shows the driving method of the present embodiment, in which V com1 For the driving voltage of the first compensation electrode 141, V com2 V for the driving voltage of the second compensation electrode 142 com1 And V is equal to com2 Alternating voltage switched between positive and negative voltage, positive voltage and negative voltage being equal, V com2 Voltage higher than V com1 Voltage higher than the voltage value of V Compensation ，V Compensation The first pixel electrode 141 is compensated for a phase delay voltage generated by light passing through the passivation layer. It should be noted that, in the same frame, the polarities of the pixel electrode voltage and the compensation electrode voltage are opposite, and the driving voltage of the pixel electrode in this embodiment is reduced compared with the prior art, so as to achieve the effect of reducing the power consumption of the device, as shown in fig. 2. In addition, under the condition of limited chip driving voltage, the voltage difference between the compensation electrode and the pixel electrode can be improved by adjusting the voltage of the compensation electrode, therebyImproving the phase control capability of the device.
As shown in fig. 3, the lower substrate 10 further includes a lower glass substrate 11, and a thin film transistor structure 12 and an organic planarization layer 13 sequentially disposed from the lower glass substrate 11 toward the liquid crystal layer 20 side. Specifically, the thin film transistor structure 12 includes a polysilicon layer 121, a gate insulating layer 122, a first metal layer 123, a dielectric layer 124, and a second metal layer 125, which are sequentially disposed from the lower glass substrate 11 toward the liquid crystal layer 20; the side of the organic planarization layer 13 facing away from the liquid crystal layer 20 covers the second metal layer 125. In this embodiment, the materials of the upper passivation layer 321, the lower passivation layer 14, the gate insulating layer 122 and the dielectric layer 124 are all silicon dioxide; of course, other embodiments may employ silicon nitride materials.
Further, the polysilicon layer 121 includes a semiconductor layer of a first thin film transistor 1211 provided corresponding to the first pixel electrode 141 and a semiconductor layer of a second thin film transistor 1212 provided corresponding to the second pixel electrode 142; wherein the first thin film transistor 1211 is used for controlling the voltage on the first pixel electrode 141, and the second thin film transistor 1212 is used for controlling the voltage on the second pixel electrode 142. It should be noted that, the voltage of the first pixel electrode 141 is higher than the voltage of the second pixel electrode 142, specifically, the first pixel electrode 141 and the second pixel electrode 142 are driven by the first thin film transistor 1211 and the second thin film transistor 1212, so that the voltage of the first pixel electrode 141 is higher than the voltage of the second pixel electrode 142, and the rotation angle of the liquid crystal above the first pixel electrode 141 is larger than the rotation angle of the liquid crystal above the second pixel electrode 142, as shown in fig. 3, for compensating the phase delay generated by the light passing through the passivation layer, so as to achieve the effect that the phase delays of the first pixel electrode 141 and the second pixel electrode 142 are consistent.
Further, the first metal layer 123 includes a first gate electrode 1231 and a first common electrode 1232 disposed corresponding to the first pixel electrode 141, and a second gate electrode 1233 and a second common electrode 1234 disposed corresponding to the second pixel electrode 142; the second metal layer 125 includes a first source electrode 1251 and a first drain electrode 1252 provided corresponding to the first pixel electrode 141, and a second source electrode 1253 and a second drain electrode 1254 provided corresponding to the second pixel electrode 142; wherein the dielectric layer 124 is used to space the two metals of the gate, the source and the drain. In this embodiment, the first gate electrode 1231 is disposed between the first source electrode 1251 and the first drain electrode 1252, and the second gate electrode 1233 is disposed between the second source electrode 1253 and the second drain electrode 1254; an overlapping region of the first drain electrode 1252 and the first common electrode 1232 forms a first storage capacitance, and an overlapping region of the second drain electrode 1254 and the second common electrode 1234 forms a second storage capacitance. Preferably, the materials of the grid electrode, the public electrode, the source electrode and the drain electrode adopt alloy metals of titanium/aluminum/titanium in sequence from the bottom layer to the top layer; of course, other embodiments may employ an alloy of molybdenum/aluminum/molybdenum in order from bottom to top. The storage capacitor is designed to prevent leakage of the thin film transistor when the thin film transistor is turned off, so that the pixel electrode voltage is maintained in a desired voltage range.
Further, the first pixel electrode 141 is electrically connected to the first drain electrode 1252 through a pin passing through the organic planarization layer 13, and the second pixel electrode 142 is electrically connected to the second drain electrode 1254 through a pin passing through the organic planarization layer 13; the first source 1251 and the first drain 1252 pass through the dielectric layer 124, the first metal layer 123, the gate insulating layer 122 and the semiconductor layer of the first thin film transistor 1211 by pins, and the second source 1253 and the second drain 1254 pass through the dielectric layer 124, the first metal layer 123, the gate insulating layer 122 and the semiconductor layer of the second thin film transistor 1212 by pins. In this embodiment, the outer diameter of the pin gradually decreases towards the direction of the lower glass substrate 11 to form an inverted cone structure, and it can be appreciated that the inverted cone structure design has higher safety in the actual manufacturing process. In specific practice, the working mechanism of the phase controller is as follows: when the grid voltages are different, the free electron concentration of p-Si under the grid is different, and the higher the grid voltage is in a certain range, the higher the free electron concentration of p-Si is, and the larger the current flowing from the source to the drain is; the source electrode is a voltage signal to be written, the drain electrode is connected with the pixel electrode to transmit a source channel to the pixel electrode, and the on-off or on-state degree of the thin film transistor is controlled by controlling the voltage of the gate electrode.
In summary, the invention adopts a compensation structure comprising an upper passivation layer and a plurality of first compensation electrodes and second compensation electrodes which are arranged on the upper passivation layer in a staggered manner on an upper substrate, wherein the first compensation electrodes and the first pixel electrodes are correspondingly arranged, and have the same or a small difference in area, and the second compensation electrodes and the second pixel electrodes are correspondingly arranged, and have the same or a small difference in area, and the distance between the first compensation electrodes and the first pixel electrodes is consistent with the distance between the second compensation electrodes and the second pixel electrodes.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (10)
1. An optical phase control display device comprises an upper substrate, a lower substrate and a liquid crystal layer arranged between the upper substrate and the lower substrate, wherein the lower substrate comprises a lower passivation layer, a plurality of first pixel electrodes and second pixel electrodes, the lower passivation layer comprises a first surface and a second surface which are opposite, the first pixel electrodes are embedded in the first surface, the second pixel electrodes are embedded in the second surface, and the first pixel electrodes and the second pixel electrodes are mutually staggered; the liquid crystal display device is characterized in that the upper substrate comprises an upper glass substrate and a compensation structure arranged from the upper glass substrate towards one side of the liquid crystal layer;
the compensation structure comprises an upper passivation layer, a plurality of first compensation electrodes and a plurality of second compensation electrodes, wherein the upper passivation layer comprises a third surface and a fourth surface which are opposite to each other, the first compensation electrodes are embedded in the third surface, the second compensation electrodes are embedded in the fourth surface, and the first compensation electrodes and the second compensation electrodes are arranged in a staggered mode; the first compensation electrode and the first pixel electrode are correspondingly arranged, and the projection size of the first compensation electrode on the lower passivation layer is equal to that of the first pixel electrode or the error of the first compensation electrode and the first pixel electrode is less than 1%; the second compensation electrode is arranged corresponding to the second pixel electrode, and the projection size of the second compensation electrode on the lower passivation layer is equal to the second pixel electrode or the error of the second compensation electrode and the second pixel electrode is less than 1%; the distance between the first compensation electrode and the first pixel electrode is consistent with the distance between the second compensation electrode and the second pixel electrode, and the phase difference of the first pixel electrode and the second pixel electrode due to the lower passivation layer is compensated by respectively controlling the writing voltage signals to the first compensation electrode and the second compensation electrode and utilizing the voltage difference of the first compensation electrode and the second compensation electrode.
2. An optical phase control display device according to claim 1, wherein the first compensation electrodes are distributed in a rectangular array, and the second compensation electrodes are arranged opposite to the gap between two adjacent first compensation electrodes.
3. The optical phase control display device according to claim 1, wherein the lower substrate further comprises a lower glass substrate and a thin film transistor structure and an organic planarization layer sequentially disposed from the lower glass substrate toward the liquid crystal layer side;
the thin film transistor structure comprises a polysilicon layer, a gate insulating layer, a first metal layer, a dielectric layer and a second metal layer which are sequentially arranged from the lower glass substrate towards one side of the liquid crystal layer; and one side of the organic flat layer, which is away from the liquid crystal layer, covers the second metal layer.
4. The optical phase control display device according to claim 3, wherein the polysilicon layer includes a semiconductor layer of a first thin film transistor provided corresponding to the first pixel electrode and a semiconductor layer of a second thin film transistor provided corresponding to the second pixel electrode; the first thin film transistor is used for controlling the voltage on the first pixel electrode, and the second thin film transistor is used for controlling the voltage on the second pixel electrode.
5. The optical phase control display device according to claim 4, wherein the first metal layer includes a first gate electrode and a first common electrode provided corresponding to the first pixel electrode, and a second gate electrode and a second common electrode provided corresponding to the second pixel electrode.
6. The optical phase control display device according to claim 5, wherein the second metal layer includes a first source electrode and a first drain electrode provided corresponding to the first pixel electrode, and a second source electrode and a second drain electrode provided corresponding to the second pixel electrode;
the first grid electrode is arranged between the first source electrode and the first drain electrode, and the second grid electrode is arranged between the second source electrode and the second drain electrode; the overlapping area of the first drain electrode and the first common electrode forms a first storage capacitor, and the overlapping area of the second drain electrode and the second common electrode forms a second storage capacitor.
7. The optical phase control display device according to claim 6, wherein the first pixel electrode is electrically connected to the first drain electrode through the organic planarization layer by a pin, and the second pixel electrode is electrically connected to the second drain electrode through the organic planarization layer by a pin; the first source electrode and the first drain electrode pass through the dielectric layer, the first metal layer and the gate insulating layer through pins and are electrically connected with the semiconductor layer of the first thin film transistor, and the second source electrode and the second drain electrode pass through the dielectric layer, the first metal layer and the gate insulating layer through pins and are electrically connected with the semiconductor layer of the second thin film transistor.
8. An optical phase control display device according to claim 3, wherein the upper passivation layer, the lower passivation layer, the gate insulating layer and the dielectric layer are all of silicon dioxide or silicon nitride.
9. The optical phase control display device according to claim 1, wherein surfaces of the liquid crystal layer facing the upper substrate and the lower substrate are respectively provided with a liquid crystal alignment layer.
10. An optical phase control display device according to any one of claims 1 to 9, wherein the voltage of the first pixel electrode is higher than the voltage of the second pixel electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210085731.5A CN114355681B (en) | 2022-01-25 | 2022-01-25 | Optical phase control display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210085731.5A CN114355681B (en) | 2022-01-25 | 2022-01-25 | Optical phase control display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114355681A CN114355681A (en) | 2022-04-15 |
| CN114355681B true CN114355681B (en) | 2023-06-20 |
Family
ID=81093010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210085731.5A Active CN114355681B (en) | 2022-01-25 | 2022-01-25 | Optical phase control display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114355681B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010094908A (en) * | 2000-04-07 | 2001-11-03 | 구본준, 론 위라하디락사 | transflective liquid crystal display device |
| JP2005049894A (en) * | 2004-09-27 | 2005-02-24 | Sanyo Electric Co Ltd | Active matrix liquid crystal display device |
| CN1877403A (en) * | 2005-06-09 | 2006-12-13 | 三洋爱普生映像元器件有限公司 | Liquid crystal device and electronic apparatus |
| CN101393335A (en) * | 2007-09-21 | 2009-03-25 | 群康科技(深圳)有限公司 | Half- penetration and half-reflection LCD |
| CN103915445A (en) * | 2012-12-31 | 2014-07-09 | 乐金显示有限公司 | Ultra high resolution liquid crystal display having a compensating thin film transistor at each pixel |
| CN203909438U (en) * | 2014-03-20 | 2014-10-29 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN106154666A (en) * | 2016-08-23 | 2016-11-23 | 京东方科技集团股份有限公司 | A kind of array base palte, its driving method, display panels and display device |
-
2022
- 2022-01-25 CN CN202210085731.5A patent/CN114355681B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010094908A (en) * | 2000-04-07 | 2001-11-03 | 구본준, 론 위라하디락사 | transflective liquid crystal display device |
| JP2005049894A (en) * | 2004-09-27 | 2005-02-24 | Sanyo Electric Co Ltd | Active matrix liquid crystal display device |
| CN1877403A (en) * | 2005-06-09 | 2006-12-13 | 三洋爱普生映像元器件有限公司 | Liquid crystal device and electronic apparatus |
| CN101393335A (en) * | 2007-09-21 | 2009-03-25 | 群康科技(深圳)有限公司 | Half- penetration and half-reflection LCD |
| CN103915445A (en) * | 2012-12-31 | 2014-07-09 | 乐金显示有限公司 | Ultra high resolution liquid crystal display having a compensating thin film transistor at each pixel |
| CN203909438U (en) * | 2014-03-20 | 2014-10-29 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN106154666A (en) * | 2016-08-23 | 2016-11-23 | 京东方科技集团股份有限公司 | A kind of array base palte, its driving method, display panels and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114355681A (en) | 2022-04-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9341898B2 (en) | Liquid crystal display device | |
| US7495715B2 (en) | Thin film transistor array panel | |
| JP5068886B2 (en) | Liquid crystal panel and liquid crystal display device | |
| KR100486799B1 (en) | Reflection-type liquid crystal display apparatus | |
| US9835911B2 (en) | Liquid crystal display device | |
| GB2326012A (en) | Homeotropic liquid crystal display | |
| US20150049269A1 (en) | Liquid crystal display device | |
| US20130050601A1 (en) | Liquid crystal display device | |
| US20040125296A1 (en) | Liquid crystal display device | |
| WO2012017931A1 (en) | Liquid crystal panel and liquid crystal display unit | |
| US20160291409A1 (en) | Liquid crystal display including pixel and auxiliary electrodes within display substrate | |
| US20090284700A1 (en) | Substrate for display panel, liquid crystal display panel having the substrate, and method of manufacturing the same | |
| US20040100607A1 (en) | Liquid crystal display | |
| US20200201118A1 (en) | Display panel, driving method thereof and display device | |
| US20150015817A1 (en) | Liquid crystal display device | |
| CN113631997B (en) | Liquid crystal panel and display device | |
| US20150248043A1 (en) | Liquid crystal display device | |
| CN114355681B (en) | Optical phase control display device | |
| US20140160417A1 (en) | Liquid crystal display device | |
| US9250486B2 (en) | Liquid crystal display device | |
| US20130148066A1 (en) | Liquid crystal panel and liquid crystal display device | |
| US11822186B2 (en) | Array substrates and liquid crystal display panels thereof | |
| KR19990038180A (en) | Liquid crystal display device having a new liquid crystal driving method | |
| US20150009459A1 (en) | Liquid crystal display panel and liquid crystal display device | |
| US7649603B2 (en) | Method for manufacturing an in-plane switching IPS mode liquid crystal display device with vertical alignment film |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |