CN114578266A - Method and system for testing reliability of domestic mainboard - Google Patents
Method and system for testing reliability of domestic mainboard Download PDFInfo
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- CN114578266A CN114578266A CN202210268256.5A CN202210268256A CN114578266A CN 114578266 A CN114578266 A CN 114578266A CN 202210268256 A CN202210268256 A CN 202210268256A CN 114578266 A CN114578266 A CN 114578266A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
Abstract
The invention discloses a method and a system for testing the reliability of a domestic mainboard, which are applied to a system for testing the reliability of the domestic mainboard; the system comprises an interface testing device; the interface testing device comprises a processing module and a plurality of interface detection modules which are in communication connection with the processing module; the interface detection module comprises a test chip, a connector, an identification resistor and an identification module, and the interface detection module corresponds to a plurality of equipment interfaces of the mainboard to be tested one by one; according to the reliability test method for the domestic mainboard, provided by the invention, whether the connection error occurs between each interface detection module and each equipment interface of the mainboard to be tested can be quickly and effectively detected by comparing the voltage values of the identification resistors, so that the test result error caused by the wiring error in the reliability test of the domestic mainboard is avoided, and the accuracy of the result of the reliability test of the domestic mainboard is ensured.
Description
Technical Field
The invention relates to the technical field of reliability testing of a domestic mainboard, in particular to a method and a system for testing the reliability of a domestic mainboard.
Background
The main board is one of the most basic components of a computer, and a series of equipment interfaces are provided on the main board; the device interfaces are used for connecting functional devices such as a Central Processing Unit (CPU), a display card, a sound card, a hard disk, a memory and the like; the communication cooperation among all functional devices is based on these device interfaces, so in order to ensure the normal use of the computer system, the test must be performed after the production of the motherboard is completed.
Intelligence and automation are the current development direction in the testing field. Especially, each link for testing the mainboard almost has the tendency of applying the artificial intelligence technology; at present, in the process of testing a mainboard, an intelligent test device is usually developed, after the test device is in communication connection with each interface of the mainboard to be tested through a connector, each test signal is sequentially output to the mainboard, the mainboard generates a corresponding response signal after receiving the test signal, and the test device receives the response signal and judges whether the mainboard is qualified or not.
However, the manual operation of connecting the interfaces of each connector on the test equipment and the main board to be tested may cause a connection error between each connector and each interface of the main board to be tested, and if a connection error occurs, an error may also occur in the result of the reliability test of the main board.
Disclosure of Invention
The invention mainly aims to provide a method and a system for testing the reliability of a domestic mainboard, and aims to solve the problem that the existing mainboard reliability testing scheme may cause the condition that each connector of testing equipment is connected with each interface of a mainboard to be tested wrongly.
The technical scheme provided by the invention is as follows:
a method for testing the reliability of a domestic mainboard is applied to a system for testing the reliability of the domestic mainboard; the system comprises an interface testing device; the interface testing device comprises a processing module and a plurality of interface detection modules which are in communication connection with the processing module; the interface detection module comprises a test chip, a connector, an identification resistor and an identification module, the interface detection module corresponds to a plurality of equipment interfaces of the mainboard to be detected one by one, and the connector of the interface detection module is used for establishing communication connection with the corresponding equipment interfaces; one end of the identification resistor is electrically connected with the connector, and the other end of the identification resistor is grounded; the resistance values of the identification resistors are different; the identification module is used for measuring the voltage value of each identification resistor; the method comprises the following steps:
after the connector is in communication connection with the equipment interface, the test chip generates an excitation signal corresponding to the equipment interface and sends the excitation signal to the mainboard to be tested through the connector, wherein the excitation signal comprises an excitation current value;
the test chip generates qualified voltage based on the excitation signal and the resistance value of the corresponding identification resistor;
the method comprises the steps that a to-be-tested mainboard generates a corresponding verification signal based on a received excitation signal and outputs the verification signal to an identification resistor through a corresponding equipment interface, wherein the verification signal is a current signal, and the signal value of the verification signal is an excitation current value;
the identification module measures voltage signal values of the identification resistors, marks the voltage signal values as verification voltages and sends the verification voltages to the processing module;
the processing module judges whether the verification voltage is matched with the qualified voltage;
if so, the processing module controls the test chip to perform interface function test on the equipment interface corresponding to the mainboard to be tested;
if not, the processing module generates an alarm signal.
Preferably, the processing module controls the test chip to perform interface function test on the device interface corresponding to the motherboard to be tested, including:
the processing module sends a detection signal to the test chip;
the test chip sends a test signal to the equipment interface through the connector based on the detection signal;
the method comprises the steps that a mainboard to be tested generates a corresponding feedback signal based on a test signal and sends the feedback signal to a test chip through an equipment interface, wherein the feedback signal comprises data transmission rate, data transmission duration and data volume;
and the test chip generates a test result based on the feedback signal and sends the test result to the processing module, wherein the test result comprises test success and test failure.
Preferably, the excitation signal further includes an excitation duration and a unit duration, and the excitation current value corresponding to each unit duration in the excitation duration is different, so that the excitation current value continuously changes in the excitation duration; the qualified voltage is expressed as a voltage value obtained by calculation when the excitation current passes through the identification resistor within the excitation time; the verification voltage is expressed as a voltage value obtained by measurement when the excitation current passes through the identification resistor within the excitation duration; the processing module judges whether the verification voltage is matched with the qualified voltage value or not, and comprises the following steps:
the processing module acquires Euclidean distances between a voltage curve of the verification voltage and a voltage curve of the qualified voltage in the same time domain;
the processing module calculates the variance of the Euclidean distance;
when the variance is smaller than or equal to a first preset value, the processing module determines that the verification voltage is matched with a qualified voltage value, wherein the value of the first preset value is related to the temperature of the test environment;
when the variance is larger than a first preset value, the processing module determines that the verification voltage does not match the qualified voltage value.
Preferably, the interface testing device further comprises a storage module in communication connection with the processing module; the test chip generates a test result based on the feedback signal and sends the test result to the processing module, and then the method further comprises the following steps:
the processing module stores the test result to the storage module to generate a historical test result, wherein the historical test result comprises the test result of each mainboard to be tested after the interface test is completed;
the method further comprises the following steps:
the processing module acquires a historical test result;
the processing module acquires test results corresponding to each equipment interface based on historical test results as the number of test failures;
the processing module carries out descending ranking on the equipment interfaces according to the times and obtains preset times;
the processing module marks the equipment interface with the frequency greater than the preset frequency as a key interface;
and for the key interface, executing the step of performing interface function test on the equipment interface corresponding to the mainboard to be tested by the processing module control test chip again.
Preferably, the system further comprises a mechanical arm, a camera and a plurality of conveying belts; the camera is in communication connection with the processing module; the number of the conveying belts is consistent with that of the interface testing devices, the conveying belts correspond to the interface testing devices one by one, and the conveying belts are used for conveying the mainboard to be tested to the corresponding interface testing devices; the method further comprises the following steps:
the processing module acquires a conveying video obtained by shooting the conveying belt by the camera in real time;
the processing module carries out image analysis on the transmission video to obtain the reliability test completion number of the domestic mainboard to be tested corresponding to each conveyer belt in the past preset time period;
the processing module generates unit test duration corresponding to the conveyer belt based on a preset time period and the reliability test completion number of the domestic mainboard to be tested;
the processing module carries out image analysis on the transmission video based on the unit testing time length so as to obtain the residual time length required by each conveyer belt to finish the transmission of the current mainboard to be tested;
the processing module marks the conveyer belt with the residual time length less than the first preset time length as a target conveyer belt;
the processing module acquires unit test duration corresponding to the target conveyer belt;
the processing module generates a corresponding preset number based on unit test duration corresponding to the target conveyer belt, wherein the preset number and the unit test duration are in an inverse proportion relation, and a specific calculation formula is as follows:
in the formula, SyThe preset number is used; a is a correction coefficient, and a positive integer is taken; t isvTesting time length in standard unit of second; t isdThe unit is the testing time length and the unit is the second;
the processing module controls the mechanical arm to transfer the preset number of mainboards to be detected to the target conveying belt, and marks the target conveying belt as a normal conveying belt.
Preferably, the system further comprises a dust test chamber; the processing module is in communication connection with the dust test chamber; the method further comprises the following steps:
and (3) carrying out a dust test:
the method comprises the steps that a processing module obtains dust test information, wherein the dust test information comprises dust concentration, air flow speed and first test time length;
the processing module controls the dust test box to start and operate according to the dust concentration and the air flow speed;
after the board to be tested is placed in the dust test box for the first test duration, executing the step that the processing module controls the test chip to perform interface function test on the equipment interface corresponding to the mainboard to be tested so as to judge whether the equipment interface which does not pass the interface function test exists;
if so, the processing module marks the equipment interface which fails the interface function test as a failure interface, and marks the dust test information as detailed information corresponding to the failure interface, wherein the failure interface is the equipment interface which fails the dust test;
and the processing module packages the failure interface and the corresponding detailed information into a dust test result and stores the dust test result in the storage module.
Preferably, the processing module obtains dust test information, and includes:
the processing module acquires the number of the mainboards to be tested which are to be subjected to dust testing, and marks the number as the queuing number;
the processing module determines the dust concentration based on the model of the board card to be detected;
the processing module determines an airflow rate and a first test duration based on the number of queues, wherein the first test duration is calculated by:
in the formula, T1The unit is S, and the first test duration is the first test duration; t isbDetermining the standard dust test duration based on the model of the mainboard to be tested, wherein the unit is S; (ii) a SbThe number is the standard queuing number and is expressed as the queuing number of the mainboard to be tested under the normal test progress; s. thepIs the number of queues;
the calculation formula of the air flow speed is as follows:
in the formula, V1Is the air flow speed, and the unit is m/S; vbThe standard air flow speed is expressed as the air flow speed adopted when the mainboard to be tested performs dust test under the normal test progress, and the unit is m/S; (ii) a P isbThe standard test frequency is determined based on the model of the mainboard to be tested.
Preferably, the system further comprises a temperature testing device; the temperature testing device comprises an infrared thermal imager and a testing processor; the infrared thermal imager is in communication connection with the processing module; the infrared thermal imager is used for shooting the mainboard to be tested; the method further comprises the following steps:
after the test processor is installed on the mainboard to be tested, the test processor starts a temperature test program, wherein after the temperature test program is started, the occupancy rate of the test processor is increased every second preset time according to a preset proportion, and the third preset time is kept until the occupancy rate reaches a second preset value;
the method comprises the steps that a processing module obtains a temperature measurement video obtained by an infrared thermal imager shooting a mainboard to be tested in real time, wherein the starting time of the temperature measurement video is the time when a test processor starts a temperature test program, and the time length of the temperature measurement video is longer than the running time length of the temperature test program;
the processing module carries out image analysis on the temperature measurement video to obtain a position temperature set corresponding to the mainboard to be measured, and marks the position temperature set as a target position temperature set, wherein the target position temperature set is used for expressing the temperature change condition of each position point on the mainboard to be measured within the duration of the temperature measurement video;
the processing module obtains a standard position temperature set corresponding to the mainboard to be tested, and compares the target position temperature set with the standard position temperature set to generate a temperature test result, wherein the standard position temperature set is used for expressing the normal temperature change condition of each position point on the mainboard to be tested, which is qualified in temperature test, within the duration of the temperature measurement video.
Preferably, the comparing the target location temperature set with the standard location temperature set to generate the temperature test result includes:
the processing module judges whether the temperature of each position point of the mainboard to be tested exceeds the standard or not based on the target position temperature set;
the processing module acquires the number of position points with excessive temperature and marks the number as excessive number;
the processing module calculates a temperature exceeding degree coefficient;
the processing module determines whether the following conditions are satisfied: the exceeding quantity is larger than the preset quantity, or the temperature exceeding degree coefficient is larger than the preset coefficient;
if so, the processing module generates a temperature test result for expressing the temperature test failure of the mainboard to be tested;
if not, the processing module generates a temperature test result for expressing the successful temperature test of the mainboard to be tested;
the judgment formula for judging whether the temperature exceeds the standard at each position point of the mainboard to be tested based on the target position temperature set by the processing module is as follows:
if the following conditions are met:
the processing module judges that the temperature of the position point P of the mainboard to be tested exceeds the standard, wherein W isp,tShowing the P-th main board to be measured with the temperature concentration of the target positionThe tth temperature value of the position point, p is more than or equal to 1 and less than or equal to M, and M represents the total number of the position points of the mainboard to be tested; t is more than or equal to 1 and less than or equal to N, and N represents the number of temperature values corresponding to each position point;
the tth temperature value of the pth position point of the mainboard to be measured in the standard position temperature set is represented; wbRepresents a standard single temperature difference;
the calculation formula of the processing module for calculating the temperature overproof degree coefficient is as follows:
wherein C is the coefficient of exceeding the temperature, WzRepresents the standard total temperature difference and has Wz<Wb。
The invention also provides a system for testing the reliability of the domestic mainboard, which is applied to the method for testing the reliability of the domestic mainboard, and comprises an interface testing device; the interface testing device comprises a processing module and a plurality of interface detection modules which are in communication connection with the processing module; the interface detection module comprises a test chip, a connector, an identification resistor and an identification module, the interface detection module corresponds to a plurality of equipment interfaces of the mainboard to be detected one by one, and the connector of the interface detection module is used for establishing communication connection with the corresponding equipment interfaces; one end of the identification resistor is electrically connected with the connector, and the other end of the identification resistor is grounded; the resistance values of the identification resistors are different; the identification module is used for measuring the voltage value of each identification resistor.
Through above-mentioned technical scheme, can realize following beneficial effect:
according to the reliability test method for the domestic mainboard, provided by the invention, whether the connection error occurs between each interface detection module and each equipment interface of the mainboard to be tested can be quickly and effectively detected by comparing the voltage values of the identification resistors, so that the test result error caused by the wiring error in the reliability test of the domestic mainboard is avoided, and the accuracy of the result of the reliability test of the domestic mainboard is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a flowchart of a method for testing reliability of a homemade motherboard according to a first embodiment of the present invention.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention provides a method and a system for testing the reliability of a domestic mainboard.
As shown in fig. 1, in a first embodiment of a method for testing reliability of a localization motherboard, the present embodiment is applied to a system for testing reliability of a localization motherboard; the system comprises an interface testing device; the interface testing device comprises a processing module and a plurality of interface detection modules which are in communication connection with the processing module; the interface detection module is used for detecting each equipment interface of the mainboard to be detected; the interface detection module comprises a test chip, a connector, an identification resistor and an identification module, the interface detection module corresponds to a plurality of equipment interfaces of the mainboard to be detected one by one, and the connector of the interface detection module is used for establishing communication connection with the corresponding equipment interfaces; one end of the identification resistor is electrically connected with the connector, and the other end of the identification resistor is grounded; the resistance values of the identification resistors are different; the identification module is used for measuring the voltage value of each identification resistor; the present embodiment comprises the following steps:
step S110: after the connector is in communication connection with the equipment interface, the test chip generates an excitation signal corresponding to the equipment interface and sends the excitation signal to the mainboard to be tested through the connector, wherein the excitation signal comprises an excitation current value.
Specifically, the excitation signal is used to inform the motherboard to be tested that the device interface is to be tested, before this, it is necessary to verify whether each interface detection module is correctly connected to the corresponding device interface, and the excitation signal includes an excitation current value.
Step S120: the test chip generates qualified voltage based on the excitation signal and the resistance value of the corresponding identification resistor.
Specifically, the pass voltage is the excitation current value multiplied by the resistance value of the corresponding identification resistor.
For example, the interface 1 detection module corresponds to the interface 1 of the device, and the interface 2 detection module corresponds to the interface 2 of the device; the resistance value of the identification resistor of the interface detection module No. 1 is 1K omega, the excitation current value in the excitation signal sent by the test chip of the interface detection module No. 1 is 1A, and the qualified voltage of the identification resistor of the interface detection module No. 1 is 1 kV; the resistance value of the identification resistor of the interface detection module No. 2 is 2K omega, the excitation current value in the excitation signal sent by the test chip of the interface detection module No. 2 is 2A, and the qualified voltage of the identification resistor of the interface detection module No. 2 is 4kV
Step S130: the mainboard to be tested generates a corresponding verification signal based on the received excitation signal, and outputs the verification signal to the identification resistor through a corresponding equipment interface, wherein the verification signal is a current signal, and the signal value of the verification signal is an excitation current value.
Specifically, the main board to be tested outputs the verification signal to the identification resistor through the corresponding equipment interface. For example, the to-be-tested mainboard outputs verification information generated based on the excitation signal from the No. 1 interface detection module to the identification resistor in the interface detection module connected with the No. 1 equipment interface through the No. 1 equipment interface; and the to-be-tested mainboard outputs verification information generated based on the excitation signal from the No. 2 interface detection module to the identification resistor in the interface detection module connected with the No. 2 equipment interface through the No. 2 equipment interface.
Step S140: the identification module measures voltage signal values of the identification resistors, marks the voltage signal values as verification voltages, and sends the verification voltages to the processing module.
Step S150: the processing module judges whether the verification voltage is matched with the qualified voltage.
If yes, go to step S160: and the processing module controls the test chip to perform interface function test on the equipment interface corresponding to the mainboard to be tested.
If not, go to step S170: the processing module generates an alarm signal.
Specifically, for example, when the interface detection module No. 1 is actually in communication connection with the device interface No. 1, and the interface detection module No. 2 is actually in communication connection with the device interface No. 2, the on-state current value of the identification resistor of the interface detection module No. 1 is 1A, and the voltage of the identification resistor of the interface detection module No. 1 is 1kV and is consistent with the qualified voltage of the identification resistor of the interface detection module No. 1; the conducting current value of the identification resistor of the interface detection module No. 2 is 2A, and the voltage of the identification resistor of the interface detection module No. 2 is 4kV and is consistent with the qualified voltage of the identification resistor of the interface detection module No. 1; and if the interface detection module is proved not to be connected in error, the subsequent interface function test step can be continued.
When the interface 1 detection module is in communication connection with the interface 2 incorrectly, the conducted current value of the identification resistor of the interface 1 detection module is 2A, and the voltage of the identification resistor of the interface 1 detection module is 2kV and is inconsistent with the qualified voltage of the identification resistor of the interface 1 detection module; if the connection error between the interface detection module No. 1 and the equipment interface of the mainboard to be tested is proved, the processing module directly generates an alarm signal to remind an operator to correct in real time.
The reliability test method for the domestic mainboard provided by the invention can quickly and effectively detect whether the connection error occurs between each interface detection module and each equipment interface of the mainboard to be tested or not by comparing the voltage values of the identification resistors, thereby avoiding the test result error caused by the wiring error in the reliability test of the domestic mainboard and ensuring the accuracy of the result of the reliability test of the domestic mainboard.
In a second embodiment of the method for testing reliability of a domestic motherboard provided by the present invention, based on the first embodiment, step S160 includes the following steps:
step S210: the processing module sends the detection signal to the test chip.
Step S220: the test chip sends a test signal to the device interface through the connector based on the detection signal.
Step S230: the mainboard to be tested generates a corresponding feedback signal based on the test signal and sends the feedback signal to the test chip through the equipment interface, wherein the feedback signal comprises data transmission rate, data transmission duration and data volume.
Step S240: and the test chip generates a test result based on the feedback signal and sends the test result to the processing module, wherein the test result comprises test success and test failure.
Specifically, the test chip determines whether the communication of the device interface is normal by analyzing the transmission rate, the data transmission duration, and the data volume in the feedback signal, that is, whether the transmission rate of the device interface is normal, whether the data transmission duration of the device interface is normal, and whether the data volume based on the feedback signal sent by the device interface is normal.
In a third embodiment of the method for testing reliability of a localized motherboard provided by the present invention, based on the first embodiment, the excitation signal further includes an excitation duration (e.g., 10 seconds) and a unit duration (e.g., 1 second), and the excitation current values corresponding to each unit duration in the excitation duration are different, so that the excitation current values continuously change in the excitation duration; the qualified voltage is expressed as a voltage value obtained by calculation when the excitation current passes through the identification resistor within the excitation time; the verification voltage is expressed as a voltage value obtained by measurement when the excitation current passes through the identification resistor within the excitation time; step S150, including the steps of:
step S310: the processing module obtains the Euclidean distance between the voltage curve of the verification voltage and the voltage curve of the qualified voltage in the same time domain.
Specifically, the fitting similarity degree of the voltage curve of the verification voltage and the voltage curve of the qualified voltage can be judged by comparing the Euclidean distances.
Step S320: the processing module calculates the variance of the Euclidean distance;
step S330: and when the variance is smaller than or equal to a first preset value, the processing module determines that the verification voltage is matched with the qualified voltage value, wherein the value of the first preset value is related to the temperature of the test environment.
Specifically, the variance is used to express the degree of deviation of the euclidean distance, the larger the variance, the worse the degree of similarity between the voltage curve of the verification voltage and the voltage curve of the pass voltage, and the smaller the variance, the better the degree of similarity between the voltage curve of the verification voltage and the voltage curve of the pass voltage,
step S340: when the variance is larger than a first preset value, the processing module determines that the verification voltage does not match the qualified voltage value.
Specifically, the fitting similarity degree of the voltage curve of the verification voltage and the voltage curve of the qualified voltage can be judged by comparing the variance with a first preset value, if the variance is greater than the first preset value (for example, 10), the fitting similarity degree of the voltage curve of the verification voltage and the voltage curve of the qualified voltage is poor, and further, the voltage curve of the verification voltage is not matched with the voltage curve of the qualified voltage, and the verification voltage is not matched with the qualified voltage; if the variance is less than or equal to the first preset value (for example, 10), it indicates that the fitting similarity between the voltage curve of the verification voltage and the voltage curve of the qualified voltage is good, and further indicates that the voltage curve of the verification voltage and the voltage curve of the qualified voltage are consistent, it indicates that the verification voltage and the qualified voltage are matched. Through the mode of comparing the curves, the reliability of the matching result of the verification voltage and the qualified voltage can be improved, and the first preset value is related to the temperature because the change of the resistance value is related to the temperature, so that the voltage value can change along with the temperature.
In a fourth embodiment of the method for testing reliability of a domestic motherboard, based on the second embodiment, the interface testing apparatus further includes a storage module in communication connection with the processing module; step S240, the following steps are also included thereafter:
step S410: the processing module stores the test result to the storage module to generate a historical test result, wherein the historical test result comprises the test result of each mainboard to be tested after the interface test is completed.
This embodiment further comprises the steps of:
step S420: the processing module obtains a historical test result.
Step S430: and the processing module acquires the test result corresponding to each equipment interface based on the historical test result as the test failure frequency.
Step S440: and the processing module performs descending ranking on the equipment interfaces according to the times and acquires the preset times.
Specifically, the preset number is, for example, 10 times.
Step S450: and the processing module marks the equipment interface with the frequency greater than the preset frequency as a key interface.
Step S460: for the focus interface, step S160 is performed again.
Specifically, step S160 is executed again for the key interface, that is, the key interface is subjected to the interface test 2 times, so as to ensure the accuracy of the final reliability test result of the domestic motherboard.
In a fifth embodiment of the method for testing the reliability of the domestic mainboard, based on the third embodiment, the system further comprises a mechanical arm, a camera and a plurality of conveyer belts; the camera is in communication connection with the processing module; the number of the conveying belts is consistent with that of the interface testing devices, the conveying belts correspond to the interface testing devices one by one, and the conveying belts are used for conveying the mainboard to be tested to the corresponding interface testing devices; the conveyer belt and the interface testing devices are in one-to-one correspondence, and each interface testing device corresponds to an operator for carrying out reliability testing on the domestic mainboard; this embodiment further comprises the steps of:
step 510: the processing module obtains a conveying video obtained by shooting the conveying belt by the camera in real time.
Step 520: the processing module performs image analysis on the transmission video to acquire the number of finished reliability tests of the to-be-tested domestic mainboard corresponding to each conveyor belt within the past preset time period (for example, 1 hour).
Step 530: the processing module generates unit test duration corresponding to the conveyer belt based on a preset time period and the number of finished reliability tests of the domestic mainboard to be tested.
Specifically, the unit test duration is duration of testing one main board by an operator corresponding to the conveyor belt.
Step 540: and the processing module performs image analysis on the transmission video based on the unit testing time length so as to obtain the residual time length required by the transmission of the current mainboard to be tested by each conveyer belt.
Step 550: the processing module marks the conveyor belt with the remaining time length less than a first preset time length (for example, 3 minutes) as the target conveyor belt.
Specifically, the target conveyor belt is a conveyor belt for the mainboard to be tested to complete the test and to be supplemented with the mainboard to be tested.
Step 560: the processing module obtains unit testing duration corresponding to the target conveyer belt.
Step 570: the processing module generates a corresponding preset number based on unit test duration corresponding to the target conveyer belt, wherein the preset number and the unit test duration are in an inverse proportion relation, and a specific calculation formula is as follows:
in the formula, SyThe preset number is used; a is a correction coefficient, and a positive integer is taken; t is a unit ofvTesting time length in standard unit of second; t isdIs the unit test duration in seconds.
Specifically, the preset number is in an inverse proportional relation with the unit test duration, that is, the smaller the unit test duration is, the higher the efficiency of the operator corresponding to the conveyor belt in testing the main board is, so that more main boards to be tested need to be supplemented at one time, that is, the larger the preset number is.
Step 580: the processing module controls the mechanical arm to transfer the preset number of mainboards to be detected to the target conveying belt, and marks the target conveying belt as a normal conveying belt.
Specifically, the mainboard that awaits measuring that the arm will predetermine quantity shifts to the target conveyer belt, accomplishes the replenishment of the mainboard that awaits measuring promptly, and the conveyer belt after accomplishing the replenishment can satisfy operating personnel next a period's test work volume, so with the mark of target conveyer belt normal conveyer belt.
The embodiment is used for supplementing the mainboard to be tested in a personalized manner automatically according to the testing speed of each operator, so that the testing progress of the operators is reasonably arranged.
In a sixth embodiment of the method for testing reliability of a domestic motherboard, based on the fourth embodiment, the system further includes a dust test box; the processing module is in communication connection with the dust test chamber; this embodiment further comprises the steps of:
step S610: performing a dust test comprising the steps of:
step S620: the processing module obtains dust test information, wherein the dust test information includes dust concentration, air flow speed, and a first test duration.
Specifically, the dust concentration and the airflow speed are parameters of the dust test chamber during operation.
Step S630: and the processing module controls the dust test box to start and operate according to the dust concentration and the air flow speed.
Step S640: and after the board to be tested is clamped in the dust test box and the first test duration is placed, executing step S160 to judge whether an equipment interface which does not pass the interface function test exists.
If yes, go to step S650: and the processing module marks the equipment interface which fails the interface function test as a failed interface, and marks the dust test information as detailed information corresponding to the failed interface, wherein the failed interface is the equipment interface which fails the dust test.
Specifically, if yes, it is indicated that after passing through the dust test box, a communication fault occurs in the device interface, that is, the dust affects communication of the device interface, so that the device interface that fails the interface function test is directly marked as a failed interface, that is, the failed interface is an interface that fails the dust test.
Step S660: and the processing module packages the failure interface and the corresponding detailed information into a dust test result and stores the dust test result in the storage module.
Specifically, the failure interface and the corresponding detailed information are packaged into a dust test result, which equipment interfaces fail the dust test clearly can be known through the dust test result, and the corresponding dust test information is obtained when the equipment interfaces fail the dust test, so that an operator can analyze the test result conveniently.
In a seventh embodiment of the method for testing reliability of a domestic motherboard, based on the sixth embodiment, the method further includes the following steps:
step S710: and performing dust tests for multiple times, and gradually increasing the dust concentration in the dust test information corresponding to each dust test until all equipment interfaces fail to pass the dust test.
Step S720: the processing module generates improvement guide information based on dust test results corresponding to a plurality of dust tests, wherein the improvement guide information is used for expressing an equipment interface corresponding to detailed information with the minimum dust amount.
Specifically, the aim at of this embodiment carries out many times dust test to the mainboard that awaits measuring, and the dust concentration of dust test at every turn all can promote, the equipment interface of the mainboard that awaits measuring all fails the dust test, can know the dust test information that each equipment interface corresponds when not passing the dust test like this, can know the biggest dust concentration that each equipment interface can bear, so based on the dust test result that many times dust test corresponds, can generate and improve the guide information, the equipment interface that the minimum detailed information of dust volume corresponds is the first-selected equipment interface who promotes the whole dust endurance capacity of mainboard promptly.
In an eighth embodiment of the method for testing reliability of a localization motherboard provided by the present invention, based on the sixth embodiment, step S620 includes the following steps:
step S810: the processing module obtains the number of the mainboards to be tested which are ready for dust testing and marks the number as the queuing number.
Specifically, the number of queues is the number of motherboards to be tested that need to be tested for dust.
Step S820: the processing module determines the dust concentration based on the model of the board card to be detected.
Specifically, the dust concentrations corresponding to different types of the mainboard to be tested during dust testing are different, so that the dust concentration is determined by the processing module according to the type of the board card to be tested.
Step S830: the processing module determines an airflow rate and a first test duration based on the queued amount,
the calculation formula of the first test duration is as follows:
in the formula, T1The unit of the first test duration is S; t isbDetermining the standard dust test duration based on the model of the mainboard to be tested, wherein the unit is S; (ii) a SbThe number is the standard queuing number and is expressed as the queuing number of the mainboard to be tested under the normal test progress; spIs the number of queues.
Specifically, the larger the queuing number is, the shorter the corresponding first test duration is, in order to ensure that all the motherboards to be tested can complete the dust test.
Step S840: the calculation formula of the air flow speed is as follows:
in the formula, V1Is the air flow speed, and the unit is m/S; vbThe standard air flow speed is expressed as the air flow speed adopted when the mainboard to be tested performs dust test under the normal test progress, and the unit is m/S; (ii) a PbThe standard test frequency is determined based on the model of the mainboard to be tested.
Specifically, the significance of this formula is that if the first test duration is shorter, then in order to ensure the effect of the dust test, the air velocity at which the dust test is performed needs to be increased.
In a ninth embodiment of the method for testing the reliability of a domestic mainboard, based on the second embodiment, the system further comprises a temperature testing device; the temperature testing device comprises an infrared thermal imager and a testing processor; the infrared thermal imager is in communication connection with the processing module; the infrared thermal imager is used for shooting the mainboard to be tested; the embodiment further comprises the following steps:
step S910: after the test processor is installed on the mainboard to be tested, the test processor starts a temperature test program, wherein after the temperature test program is started, the occupancy rate of the test processor is increased according to a preset proportion every second preset time (for example, 10 seconds), and a third preset time (for example, 20 seconds) is kept until the occupancy rate reaches a second preset value (for example, 95%).
Specifically, the step is mainly used for continuously increasing the occupancy rate of the test processor so as to increase the working temperature of the mainboard to be tested, and further performing temperature test on the mainboard to be tested.
Step S920: the processing module obtains a temperature measurement video obtained by the infrared thermal imager shooting the mainboard to be tested in real time, wherein the starting time of the temperature measurement video is the time when the test processor starts the temperature test program, and the time length of the temperature measurement video is longer than the running time length of the temperature test program.
Step S930: the processing module carries out image analysis on the temperature measurement video to obtain a position temperature set corresponding to the mainboard to be measured, and the position temperature set is marked as a target position temperature set, wherein the target position temperature set is used for expressing the temperature change condition of each position point on the mainboard to be measured within the duration of the temperature measurement video.
Step S940: the processing module obtains a standard position temperature set corresponding to the mainboard to be tested, and compares the target position temperature set with the standard position temperature set to generate a temperature test result, wherein the standard position temperature set is used for expressing the normal temperature change condition of each position point on the mainboard to be tested, which is qualified in temperature test, within the duration of the temperature measurement video.
Specifically, whether the temperature of each position of the mainboard to be tested exceeds the standard or not can be known by comparing the target position temperature set with the standard position temperature set, so that a temperature test result is generated, and whether the mainboard to be tested passes through the temperature test or not is judged according to the temperature test result.
In a tenth embodiment of the method for testing reliability of a domestic motherboard provided by the present invention, based on the ninth embodiment, the step of comparing the target location temperature set with the standard location temperature set in step S940 to generate a temperature test result includes the following steps:
step S1010: and the processing module judges whether the temperature of each position point of the mainboard to be tested exceeds the standard or not based on the target position temperature set.
Step S1020: the processing module obtains the number of position points with the temperature exceeding the standard and marks the position points with the temperature exceeding the standard as the standard exceeding number.
Step S1030: the processing module calculates the temperature overproof degree coefficient.
Step S1040: the processing module determines whether the following conditions are satisfied: the superscalar number is greater than a preset number (e.g., 5), or the temperature superscalar coefficient is greater than a preset coefficient (e.g., 1).
If yes, go to step S1050: and the processing module generates a temperature test result for expressing the temperature test failure of the mainboard to be tested.
If not, go to step S1060: and the processing module generates a temperature test result for expressing the successful temperature test of the mainboard to be tested.
The judgment formula for judging whether the temperature exceeds the standard at each position point of the mainboard to be tested based on the target position temperature set by the processing module is as follows:
if the following conditions are met:
the processing module judges that the temperature of the position point P of the mainboard to be tested exceeds the standard, wherein W isp,tThe tth temperature value of the pth position point of the mainboard to be tested in the target position temperature set is represented, P is more than or equal to 1 and less than or equal to M, and M represents the total number of the position points of the mainboard to be tested; and t is more than or equal to 1 and less than or equal to N, N represents each bitThe number of temperature values corresponding to the placement points;
the tth temperature value of the pth position point of the mainboard to be tested in the standard position temperature set is represented; w is a group ofbIndicating a standard single temperature difference.
The calculation formula of the processing module for calculating the temperature overproof degree coefficient is as follows:
wherein C is the coefficient of exceeding the temperature, WzRepresents the standard total temperature difference and has Wz<Wb。
Specifically, by the technical scheme, a specific scheme for comparing the target position temperature set with the standard position temperature set to generate the temperature test result is provided.
The invention also provides a system for testing the reliability of the domestic mainboard, which is applied to the method for testing the reliability of the domestic mainboard, and comprises an interface testing device; the interface testing device comprises a processing module and a plurality of interface detection modules which are in communication connection with the processing module; the interface detection module comprises a test chip, a connector, an identification resistor and an identification module, the interface detection module corresponds to a plurality of equipment interfaces of the mainboard to be detected one by one, and the connector of the interface detection module is used for establishing communication connection with the corresponding equipment interfaces; one end of the identification resistor is electrically connected with the connector, and the other end of the identification resistor is grounded; the resistance values of the identification resistors are different; the identification module is used for measuring the voltage value of each identification resistor.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the description of the foregoing embodiments, it is clear to those skilled in the art that the method of the foregoing embodiments may be implemented by software plus a necessary general hardware platform, and certainly may also be implemented by hardware, but in many cases, the former is a better implementation. Based on such understanding, the technical solutions of the present invention or portions thereof contributing to the prior art may be embodied in the form of a software product, where the computer software product is stored in a storage medium (such as a ROM/RAM, a magnetic disk, and an optical disk), and includes several instructions for enabling a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods according to the embodiments of the present invention.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A method for testing the reliability of a domestic mainboard is characterized by being applied to a system for testing the reliability of the domestic mainboard; the system comprises an interface testing device; the interface testing device comprises a processing module and a plurality of interface detection modules which are in communication connection with the processing module; the interface detection module comprises a test chip, a connector, an identification resistor and an identification module, the interface detection module corresponds to a plurality of equipment interfaces of the mainboard to be detected one by one, and the connector of the interface detection module is used for establishing communication connection with the corresponding equipment interfaces; one end of the identification resistor is electrically connected with the connector, and the other end of the identification resistor is grounded; the resistance values of the identification resistors are different; the identification module is used for measuring the voltage value of each identification resistor; the method comprises the following steps:
after the connector is in communication connection with the equipment interface, the test chip generates an excitation signal corresponding to the equipment interface and sends the excitation signal to the mainboard to be tested through the connector, wherein the excitation signal comprises an excitation current value;
the test chip generates qualified voltage based on the excitation signal and the resistance value of the corresponding identification resistor;
the method comprises the steps that a mainboard to be tested generates a corresponding verification signal based on a received excitation signal and outputs the verification signal to an identification resistor through a corresponding equipment interface, wherein the verification signal is a current signal, and the signal value of the verification signal is an excitation current value;
the identification module measures voltage signal values of the identification resistors, marks the voltage signal values as verification voltages and sends the verification voltages to the processing module;
the processing module judges whether the verification voltage is matched with the qualified voltage;
if so, the processing module controls the test chip to perform interface function test on the equipment interface corresponding to the mainboard to be tested;
if not, the processing module generates an alarm signal.
2. The method according to claim 1, wherein the step of controlling the test chip to perform interface function test on the device interface corresponding to the motherboard to be tested by the processing module comprises:
the processing module sends a detection signal to the test chip;
the test chip sends a test signal to the equipment interface through the connector based on the detection signal;
the method comprises the steps that a main board to be tested generates a corresponding feedback signal based on a test signal and sends the feedback signal to a test chip through an equipment interface, wherein the feedback signal comprises data transmission rate, data transmission duration and data volume;
and the test chip generates a test result based on the feedback signal and sends the test result to the processing module, wherein the test result comprises test success and test failure.
3. The method for testing the reliability of the homemade mainboard according to claim 1, wherein the excitation signal further comprises an excitation duration and a unit duration, and the excitation current value corresponding to each unit duration in the excitation duration is different, so that the excitation current value continuously changes in the excitation duration; the qualified voltage is expressed as a voltage value obtained by calculation when the excitation current passes through the identification resistor within the excitation time; the verification voltage is expressed as a voltage value obtained by measurement when the excitation current passes through the identification resistor within the excitation duration; the processing module judges whether the verification voltage is matched with the qualified voltage value or not, and comprises the following steps:
the processing module acquires Euclidean distances between a voltage curve of the verification voltage and a voltage curve of the qualified voltage in the same time domain;
the processing module calculates the variance of the Euclidean distance;
when the variance is smaller than or equal to a first preset value, the processing module determines that the verification voltage is matched with a qualified voltage value, wherein the value of the first preset value is related to the temperature of the test environment;
when the variance is larger than a first preset value, the processing module determines that the verification voltage does not match the qualified voltage value.
4. The method for testing the reliability of the homemade mainboard according to claim 2, wherein the interface testing device further comprises a storage module in communication connection with the processing module; the test chip generates a test result based on the feedback signal and sends the test result to the processing module, and then the method further comprises the following steps:
the processing module stores the test result into the storage module to generate a historical test result, wherein the historical test result comprises the test result of each mainboard to be tested after the interface test is finished;
the method further comprises the following steps:
the processing module acquires a historical test result;
the processing module acquires the test result corresponding to each equipment interface based on the historical test result as the test failure frequency;
the processing module carries out descending ranking on the equipment interfaces according to the times and obtains preset times;
the processing module marks the equipment interface with the frequency greater than the preset frequency as a key interface;
and for the key interface, executing the step of carrying out interface function test on the equipment interface corresponding to the mainboard to be tested by the processing module control test chip again.
5. The method for testing the reliability of the domestic main board according to claim 3, wherein the system further comprises a mechanical arm, a camera and a plurality of conveyer belts; the camera is in communication connection with the processing module; the number of the conveying belts is consistent with that of the interface testing devices, the conveying belts correspond to the interface testing devices one by one, and the conveying belts are used for conveying the mainboard to be tested to the corresponding interface testing devices; the method further comprises the following steps:
the processing module acquires a conveying video obtained by shooting the conveying belt by the camera in real time;
the processing module carries out image analysis on the transmission video to obtain the reliability test completion number of the domestic mainboard to be tested corresponding to each conveyer belt in the past preset time period;
the processing module generates unit test duration corresponding to the conveyer belt based on a preset time period and the reliability test completion number of the domestic mainboard to be tested;
the processing module carries out image analysis on the transmission video based on the unit testing time length so as to obtain the residual time length required by each conveyer belt to finish the transmission of the current mainboard to be tested;
the processing module marks the conveyer belt with the residual time length less than the first preset time length as a target conveyer belt;
the processing module acquires unit test duration corresponding to the target conveyer belt;
the processing module generates a corresponding preset number based on unit test duration corresponding to the target conveyer belt, wherein the preset number and the unit test duration are in an inverse proportion relation, and a specific calculation formula is as follows:
in the formula, SyThe preset number is used; a is a correction coefficient, and a positive integer is taken; t is a unit ofvTesting time length in standard unit of second; t is a unit ofdThe unit is the testing time length and the unit is the second;
the processing module controls the mechanical arm to transfer the preset number of mainboards to be detected to the target conveying belt, and marks the target conveying belt as a normal conveying belt.
6. The method for testing the reliability of the homemade mainboard according to claim 4, wherein the system further comprises a dust test box; the processing module is in communication connection with the dust test chamber; the method further comprises the following steps:
and (3) carrying out a dust test:
the method comprises the steps that a processing module obtains dust test information, wherein the dust test information comprises dust concentration, air flow speed and first test time length;
the processing module controls the dust test box to start and operate according to the dust concentration and the air flow speed;
after the board to be tested is placed in the dust test box for the first test duration, executing the step that the processing module controls the test chip to perform interface function test on the equipment interface corresponding to the mainboard to be tested so as to judge whether the equipment interface which does not pass the interface function test exists;
if so, the processing module marks the equipment interface which fails the interface function test as a failure interface, and marks the dust test information as detailed information corresponding to the failure interface, wherein the failure interface is the equipment interface which fails the dust test;
and the processing module packages the failure interface and the corresponding detailed information into a dust test result and stores the dust test result in the storage module.
7. The method for testing the reliability of the homemade mainboard according to claim 6, wherein the processing module obtains dust test information, and comprises:
the processing module acquires the number of the mainboards to be tested which are to be subjected to dust testing, and marks the number as the queuing number;
the processing module determines the dust concentration based on the model of the board card to be detected;
the processing module determines an airflow rate and a first test duration based on the number of queues, wherein the first test duration is calculated by:
in the formula, T1The unit is S, and the first test duration is the first test duration; t is a unit ofbDetermining the standard dust test duration based on the model of the mainboard to be tested, wherein the unit is S; (ii) a SbThe standard queuing number is expressed as the queuing number of the mainboard to be tested under the normal test progress; spIs the number of queues;
the formula for calculating the air velocity is:
in the formula, V1Is the air flow speed, and the unit is m/S; vbThe standard air flow speed is expressed as the air flow speed adopted when the mainboard to be tested performs dust test under the normal test progress, and the unit is m/S; (ii) a P isbThe standard test frequency is determined based on the model of the mainboard to be tested.
8. The method for testing the reliability of the domestic mainboard according to claim 2, wherein the system further comprises a temperature testing device; the temperature testing device comprises an infrared thermal imager and a testing processor; the infrared thermal imager is in communication connection with the processing module; the infrared thermal imager is used for shooting the mainboard to be tested; the method further comprises the following steps:
after the test processor is installed on the mainboard to be tested, the test processor starts a temperature test program, wherein after the temperature test program is started, the occupancy rate of the test processor is increased according to a preset proportion at intervals of a second preset time length, and a third preset time length is kept until the occupancy rate reaches a second preset value;
the method comprises the steps that a processing module obtains a temperature measurement video obtained by an infrared thermal imager shooting a mainboard to be tested in real time, wherein the starting time of the temperature measurement video is the time when a test processor starts a temperature test program, and the time length of the temperature measurement video is longer than the running time length of the temperature test program;
the processing module carries out image analysis on the temperature measurement video to obtain a position temperature set corresponding to the mainboard to be measured, and marks the position temperature set as a target position temperature set, wherein the target position temperature set is used for expressing the temperature change condition of each position point on the mainboard to be measured within the duration of the temperature measurement video;
the processing module obtains a standard position temperature set corresponding to the mainboard to be tested, and compares the target position temperature set with the standard position temperature set to generate a temperature test result, wherein the standard position temperature set is used for expressing the normal temperature change condition of each position point on the mainboard to be tested, which is qualified in temperature test, within the duration of the temperature measurement video.
9. The method for testing the reliability of the homemade mainboard according to claim 8, wherein the comparing the target location temperature set with the standard location temperature set to generate the temperature test result comprises:
the processing module judges whether the temperature of each position point of the mainboard to be tested exceeds the standard or not based on the target position temperature set;
the processing module acquires the number of position points with excessive temperature and marks the number as excessive number;
the processing module calculates the coefficient of the degree of exceeding the temperature;
the processing module determines whether the following conditions are satisfied: the exceeding quantity is larger than the preset quantity, or the temperature exceeding degree coefficient is larger than the preset coefficient;
if so, the processing module generates a temperature test result for expressing the temperature test failure of the mainboard to be tested;
if not, the processing module generates a temperature test result for expressing the successful temperature test of the mainboard to be tested;
the judgment formula for judging whether the temperature exceeds the standard at each position point of the mainboard to be tested based on the target position temperature set by the processing module is as follows:
if the following conditions are met:
the processing module judges that the temperature of the position point P of the mainboard to be tested exceeds the standard, wherein W isp,tThe tth temperature value of the pth position point of the mainboard to be tested in the target position temperature set is represented, P is more than or equal to 1 and less than or equal to M, and M represents the total number of the position points of the mainboard to be tested; t is more than or equal to 1 and less than or equal to N, and N represents the number of temperature values corresponding to each position point;
the tth temperature value of the pth position point of the mainboard to be measured in the standard position temperature set is represented; wbRepresents a standard single temperature difference;
the calculation formula of the processing module for calculating the temperature overproof degree coefficient is as follows:
wherein C is the coefficient of exceeding the temperature, WzRepresents the standard total temperature difference and has Wz<Wb。
10. A reliability test system for a localization mainboard, which is applied to the reliability test method for the localization mainboard according to any one of claims 1-9, and comprises an interface test device; the interface testing device comprises a processing module and a plurality of interface detection modules which are in communication connection with the processing module; the interface detection module comprises a test chip, a connector, an identification resistor and an identification module, the interface detection module corresponds to a plurality of equipment interfaces of the mainboard to be detected one by one, and the connector of the interface detection module is used for establishing communication connection with the corresponding equipment interfaces; one end of the identification resistor is electrically connected with the connector, and the other end of the identification resistor is grounded; the resistance values of the identification resistors are different; the identification module is used for measuring the voltage value of each identification resistor.
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