CN115809622B - Chip simulation acceleration system with automatic configuration optimizing function - Google Patents
Chip simulation acceleration system with automatic configuration optimizing function Download PDFInfo
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Abstract
The invention provides a chip simulation acceleration system with an automatic configuration optimizing function, which is characterized in that a configuration module is identified to obtain first key information, and the first configuration information of chip simulation equipment to a target chip is obtained according to the first key information; the statistics module is used for segmenting the first test codes according to the code segment function to obtain a plurality of second test codes, and counting a test preset result corresponding to each second test code; the determining module is used for counting preset output ports corresponding to the second test codes to obtain preset port sets, and counting preset output information of preset output ports in each preset port set to obtain a simulation verification table; the acquisition module is used for counting target output ports with time sequences to obtain an output port set; and the verification simulation module is used for verifying the output port set based on the simulation verification table to obtain a problem port set, and determining a plurality of third test codes corresponding to the second test codes according to the problem port set.
Description
Technical Field
The invention relates to a data processing technology, in particular to a chip simulation acceleration system with an automatic configuration optimizing function.
Background
Chip simulation is usually a means for verifying a chip by using a large number of code programs, and if the chip can execute corresponding simulation codes without errors, a simulation result generated by executing on a simulator should be consistent with a preset result, so that the chip simulation can be used for verifying the stability of the chip, and the chip simulation execution is a very time-consuming process because repeated simulation verification of a large number of codes is required.
Therefore, how to perform targeted simulation verification on the error portions of different chips is a problem to be solved.
Disclosure of Invention
The embodiment of the invention provides a chip simulation acceleration system with an automatic configuration optimizing function, which can conduct targeted simulation verification aiming at the problem part of a chip, and saves simulation verification time while ensuring a simulation result.
In a first aspect of the embodiment of the present invention, a chip simulation acceleration system with an automatic configuration optimization function is provided, including:
the identification configuration module is used for identifying the chip specification to obtain first key information of the chip when receiving the simulation instruction of the target chip, and obtaining first configuration information of the chip simulation equipment to the target chip according to the first key information;
The statistics module is used for determining a first test code corresponding to the target chip, segmenting the first test code according to the code segment function to obtain a plurality of second test codes, and counting a test preset result corresponding to each second test code;
the determining module is used for determining a plurality of preset output ports of the target chip, counting all preset output ports corresponding to each second test code to obtain preset port sets, and counting preset output information of the preset output ports in each preset port set to obtain a simulation verification table;
the acquisition module is used for acquiring output target information of each target output port according to the time sequence when simulating the target chip, and counting the target output ports with corresponding time sequences to obtain an output port set;
and the verification simulation module is used for verifying the output port set based on the simulation verification table to obtain a problem port set, determining a plurality of third test codes corresponding to the second test codes according to the problem port set, and simulating the chip again based on the third test codes.
Optionally, in one possible implementation manner of the first aspect, when receiving a simulation instruction for a target chip, the identifying the chip specification to obtain first key information of the chip, and obtaining, according to the first key information, first configuration information of the chip simulation device for the target chip, includes:
When a simulation instruction for a target chip is received, a chip specification corresponding to the target chip is called, and the chip specification is identified to obtain first key information of the chip, wherein the first key information at least comprises chip area information, highest frequency information, CPU type information, interface type information, core function information, IP information and/or PVT information;
and sending the first key information to a control device of the chip simulation equipment so that the chip simulation equipment carries out chip simulation according to the first configuration information.
Optionally, in one possible implementation manner of the first aspect, the determining a plurality of preset output ports of the target chip, counting all preset output ports corresponding to each second test code to obtain a preset port set, and counting preset output information of preset output ports in each preset port set to obtain a simulation verification table includes:
counting all preset output ports corresponding to each second test code to obtain a preset port set, and sequencing the signal output sequence of the preset output ports in the preset port set to obtain a port output sequence of each preset port set;
And counting preset output information of preset output ports in each preset port set according to the sequence of the preset output ports in the port output sequence to obtain a simulation verification table.
Optionally, in one possible implementation manner of the first aspect, when simulating the target chip, obtaining output target information of each target output port according to the time sequence, counting the target output ports with corresponding time sequences to obtain an output port set includes:
when the target chip is simulated, monitoring target output ports of the target chip to obtain output target information of each target output port, and determining a time sequence label corresponding to each output target information;
and carrying out statistical sorting on the output target information of all the target output ports according to the time sequence labels of all the output target information, and sorting all the target output ports based on the statistical sorting of the output target information to obtain a port output sequence of an output port set.
Optionally, in one possible implementation manner of the first aspect, the verifying the output port set based on the simulation verification table to obtain a problem port set, determining a plurality of third test codes corresponding to the second test codes according to the problem port set, and simulating the target chip again based on the third test codes includes:
If the second test code is relatively inconsistent with the class pair of the preset port set in the output port set obtained by the test, determining the port with the class problem in the output port set to obtain a first problem port set, and carrying out quantization processing on the first problem port set to obtain a first problem coefficient;
after the category comparison is completed, comparing the port output sequence of the preset port set with the port output sequence of the output port set, determining the port with sequence problem in the output port set to obtain a second problem port set, and carrying out quantization processing on the second problem port set to obtain a second problem coefficient;
after port output sequence comparison is completed, determining a target output port which does not correspond to preset output information in an output port set based on a simulation verification table to obtain a third problem port set, and carrying out quantization processing on the third problem port set to obtain a third problem coefficient;
and counting the first problem coefficient, the second problem coefficient and the third problem coefficient corresponding to each second test code, determining the code selection number of the third test codes corresponding to the second test codes, and selecting the third test codes corresponding to the code selection number to simulate the chip again.
Optionally, in one possible implementation manner of the first aspect, if the second test code is inconsistent between the pair of types of output port sets obtained by performing the test and the preset port set, determining that a port with a type problem in the output port set obtains a first problem port set, and performing quantization processing on the first problem port set to obtain a first problem coefficient, where the method includes:
determining target output ports which exist in the output port set and do not exist in the preset port set as first type target output ports, and determining target output ports which do not exist in the output port set and do not exist in the preset port set as second type target output ports;
counting the first type of target output ports and the second type of target output ports to obtain a first problem port set;
performing quantization calculation according to the first kind number of the first type of target output ports and the second kind number of the second type of target output ports to obtain a first problem coefficient, calculating the first problem coefficient by the following formula,
wherein, the liquid crystal display device comprises a liquid crystal display device,
for the first problem coefficient, +.>
For the first category number- >
For the first category weight->
For the second category number->
For the second category weight->
Weighting the number of questions.
Optionally, in one possible implementation manner of the first aspect, after the class comparison is completed, comparing a port output sequence of the preset port set with a port output sequence of the output port set, determining that a port with a sequential problem in the output port set obtains a second problem port set, and performing quantization processing on the second problem port set to obtain a second problem coefficient, where the method includes:
labeling each preset output port in the port output sequence of the preset port set to obtain a preset output port with a first label, and labeling each target output port in the port output sequence of the output port set to obtain a target output port with a second label;
counting the same number of preset output ports and target output ports corresponding to the first label and the second label of the same number respectively to obtain the same number of ports;
counting different numbers of preset output ports and target output ports corresponding to the first label and the second label of the same number respectively to obtain different numbers of ports;
Calculating according to the same number of ports and different numbers of ports to obtain a second problem coefficient of the quantization processing of the second problem port set, calculating the second problem coefficient by the following formula,
wherein, the liquid crystal display device comprises a liquid crystal display device,
for the second problem coefficient, +.>
For different numbers of ports +.>
For the same number of ports->
Weighting the number of ports.
Optionally, in one possible implementation manner of the first aspect, after the port output sequence comparison is completed, determining, based on a simulation verification table, a target output port in the output port set, which does not correspond to the preset output information, to obtain a third problem port set, and performing quantization processing on the third problem port set to obtain a third problem coefficient, where the method includes:
counting the same quantity of output target information of the target output port and corresponding preset output information to obtain the same quantity of information;
counting the different numbers of the output target information of the target output port and the corresponding preset output information to obtain the different numbers of the information;
calculating according to the same quantity of the information and different quantities of the information to obtain a third problem coefficient by carrying out quantization processing on a third problem port set, calculating the third problem coefficient by the following formula,
Wherein, the liquid crystal display device comprises a liquid crystal display device,
for the third problem coefficient, +.>
For different numbers of ports +.>
For the same number of ports->
Is the information quantity weight.
Optionally, in one possible implementation manner of the first aspect, the counting the first problem coefficient, the second problem coefficient, and the third problem coefficient corresponding to each second test code, determining a code selection number of the third test codes corresponding to the second test codes, and selecting the third test codes corresponding to the code selection number to simulate the target chip again includes:
counting the first problem coefficient, the second problem coefficient and the third problem coefficient corresponding to each second test code, and performing comprehensive calculation to obtain a comprehensive problem coefficient;
comparing the comprehensive problem coefficient with a preset problem coefficient to obtain a coefficient difference value, calculating according to the coefficient difference value and the preset code quantity to obtain the code selection quantity of the third test code, calculating the code selection quantity of the third test code by the following formula,
wherein, the liquid crystal display device comprises a liquid crystal display device,
to calculate the third test codeCode pick number,/->
For the preset problem coefficient, +.>
Normalized value for coefficient>
For the preset code quantity, ++ >
Is a quantitative weight value;
if the code selection number is not an integer, rounding the code selection number, and selecting a third test code of the same type as the second test code in a code database according to the code selection number;
after judging that the user corrects the target chip again, simulating the target chip again based on the selected third test code.
Optionally, in one possible implementation manner of the first aspect, the method further includes:
if the user is judged to adjust the code selection quantity of the third test code, comparing the code selection quantity adjusted by the user with the calculated code selection quantity to obtain a code quantity adjustment value;
if the code quantity adjusting value is larger than 0, the weight training model carries out increasing training on the digital weight value according to the code quantity adjusting value, and the number weight value after increasing training is used for adjusting the number weight value before increasing training;
if the code quantity adjusting value is smaller than 0, the weight training model carries out reduction training on the digital weight value according to the code quantity adjusting value, adjusts the quantity weight value before the reduction training on the quantity weight value after the reduction training, the weight training model carries out training on the quantity weight value through the following formula,
Wherein, the liquid crystal display device comprises a liquid crystal display device,
to increase the number weight value after training, +.>
Selecting a number of codes for the user after adjustment, +.>
To increase training coefficient->
To reduce the number weight value after training, +.>
To reduce the training coefficients.
The chip simulation acceleration system with the automatic optimization configuration function provided by the invention can perform simulation verification on corresponding first configuration information of different specifications of different target chips, classify and test and verify first test codes for simulation verification according to different functions, compare output target information obtained in an actual output port set in a simulation process with a simulation verification table, determine a problem port set, take second test codes corresponding to the problem port set as third test codes, simulate and verify the chip again based on the third test codes, select corresponding simulation verification codes for the problem part of the chip, and perform targeted simulation verification by selecting the obtained simulation verification codes.
According to the technical scheme provided by the invention, the problem ports inconsistent with the types of the preset port sets, the ports with sequential problems in the output port sets and the problem ports not corresponding to the preset output information are respectively quantized to obtain the first problem coefficient, the second problem coefficient and the third problem coefficient, the comprehensive problem coefficient is obtained by comprehensive calculation according to the first problem coefficient, the second problem coefficient and the third problem coefficient, and the code selection quantity is determined according to the comprehensive problem coefficient, so that the invention can pointedly select the simulation codes with corresponding quantity to carry out subsequent simulation according to the number of the problems during chip simulation, and the efficiency of chip simulation verification is improved.
According to the technical scheme, the system has an autonomous learning training process, when a user finds that the code quantity of the simulation training is too large, the system can actively record the user tuning down process, reduces the weight and trains the code quantity of the subsequent output to be more suitable, when the user finds that the code quantity of the simulation training is too small, the system can actively record the user tuning up process, and increases the weight and trains the code quantity of the subsequent output to be more suitable.
Drawings
Fig. 1 is a schematic structural diagram of a chip simulation acceleration system with an automatic configuration optimization function provided by the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein.
It should be understood that, in various embodiments of the present invention, the sequence number of each process does not mean that the execution sequence of each process should be determined by its functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
It should be understood that in the present invention, "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements that are expressly listed or inherent to such process, method, article, or apparatus.
It should be understood that in the present invention, "plurality" means two or more. "and/or" is merely an association relationship describing an association object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. "comprising A, B and C", "comprising A, B, C" means that all three of A, B, C comprise, "comprising A, B or C" means that one of the three comprises A, B, C, and "comprising A, B and/or C" means that any 1 or any 2 or 3 of the three comprises A, B, C.
It should be understood that in the present invention, "B corresponding to a", "a corresponding to B", or "B corresponding to a" means that B is associated with a, from which B can be determined. Determining B from a does not mean determining B from a alone, but may also determine B from a and/or other information. The matching of A and B is that the similarity of A and B is larger than or equal to a preset threshold value.
As used herein, "if" may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to detection" depending on the context.
The technical scheme of the invention is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
The invention provides a chip simulation acceleration system with an automatic optimal configuration function, as shown in fig. 1, which comprises the following specific steps:
and the identification configuration module is used for identifying the chip specification to obtain first key information of the chip when receiving the simulation instruction of the target chip, and obtaining first configuration information of the chip simulation equipment to the target chip according to the first key information.
The chip specifications are specifications corresponding to each chip, and it can be understood that each chip has a specification corresponding to the chip, and the specifications include all parameter information corresponding to the chip, that is, the first key information.
It should be noted that, the parameters corresponding to each chip are different, and the configuration data of the chip simulation device according to the different parameters are also different, so that the corresponding first configuration information needs to be configured for the chip simulation device according to the first key information of different chips.
By the implementation mode, different simulation environments can be configured for different chips, so that the subsequent simulation results are accurate.
In some embodiments, the identifying configuration module (when receiving the simulation instruction for the target chip, identifying the chip specification to obtain first key information of the chip, and obtaining first configuration information of the chip simulation device for the target chip according to the first key information) includes:
and when a simulation instruction for the target chip is received, a chip specification corresponding to the target chip is called, and the chip specification is identified to obtain first key information of the chip, wherein the first key information at least comprises chip area information, highest frequency information, CPU type information, interface type information, core function information, IP information and/or PVT information.
It can be understood that when the simulation instruction is received, a corresponding keyword is extracted from the chip specification corresponding to the target chip, so that corresponding first key information is extracted, where the first key information at least includes chip area information, highest frequency information, CPU type information, interface type information, core function information, IP information, PVT information, and the like, so that a subsequent chip simulation device can conveniently configure a suitable simulation environment according to corresponding parameters.
And sending the first key information to a control device of the chip simulation equipment so that the chip simulation equipment carries out chip simulation according to the first configuration information.
The chip simulation device configures corresponding first configuration information according to the first key information, so as to generate a simulation environment which is suitable for a target chip.
It can be understood that the simulation environments adapted to the parameters of different chips are different, so that the proper simulation environments need to be configured according to the parameters of different chips, thereby facilitating the subsequent simulation verification of the chips.
The statistics module is used for determining a first test code corresponding to the target chip, segmenting the first test code according to the code segment function to obtain a plurality of second test codes, and counting a test preset result corresponding to each second test code.
The first test code is all tested codes, for example: the traffic light chip is detected, the first test code comprises a traffic light test of a three-way intersection, a traffic light test of the intersection and the like, and the first test code can also detect a travelling trolley and comprises turning, straight running, turning, stopping and the like, and all test conditions are included.
The second test codes are test codes obtained by segmenting the first test codes according to the function of the code segments, and it can be understood that the traffic light test of the three-way intersection is one second test code segment, the traffic light test of the crossroad is another second test code segment, the first test codes are segmented by the function to obtain a plurality of second test codes, and the test preset result corresponding to each second test code is counted, wherein the test preset result is the preset correct result after each second test code is tested.
By the method, the first test codes are segmented through the code segment function to obtain the plurality of second test codes, each second test code corresponds to one test scene based on one function, and the test preset result corresponding to each second test code is obtained, so that whether errors exist or not can be conveniently found through comparison between the actual detection result and the test preset result.
The determining module is used for determining a plurality of preset output ports of the target chip, counting all preset output ports corresponding to each second test code to obtain preset port sets, and counting preset output information of preset output ports in each preset port set to obtain a simulation verification table.
The preset output port is an output port of the target chip, and it can be understood that different second test codes correspond to different detection conditions, and pins (ports) of the output signal with different detection conditions are different, for example: the traffic light detection theoretical output ports of the three-way intersection are port 1, port 2 and port 3, and the traffic light detection theoretical output ports of the three-way intersection are port 3, port 4 and port 5.
The preset output information is theoretical output information of preset output ports in each preset port set, for example: the traffic light detection theory output port of the three-fork intersection is port 1: high level, port 2: low and port 3: high level.
It can be understood that the actual output condition of each port of the chip under each condition can be obtained by counting the preset output port of the chip under each condition and the corresponding preset output information, so as to obtain the simulation verification table.
By the method, the codes corresponding to the situations of easy mistakes are found by comparing the actual verification result with the theoretical result conveniently, and the corresponding simulation codes are selected conveniently according to the mistakes.
In some embodiments, the determining module (determining a plurality of preset output ports of the target chip, counting all preset output ports corresponding to each second test code to obtain a preset port set, and counting preset output information of preset output ports in each preset port set to obtain a simulation verification table) includes:
counting all preset output ports corresponding to each second test code to obtain a preset port set, and sequencing the signal output sequence of the preset output ports in the preset port set to obtain a port output sequence of each preset port set.
It may be appreciated that each second test code theoretically calculates a preset output port to obtain a preset port set, and sorts the signal output sequence of the preset output ports in the preset port set according to the time sequence to obtain a port output sequence, for example: the traffic light detection theory output ports of the three-fork intersection are a port 1 (1 s), a port 2 (2 s) and a port 3 (3 s), and the port output sequence is as follows: the preset port sets are port 1, port 2 and port 3, and it should be noted that the port output sequence is a sequence obtained by sequencing according to the time sequence of the output signals of the preset output ports.
And counting preset output information of preset output ports in each preset port set according to the sequence of the preset output ports in the port output sequence to obtain a simulation verification table.
It can be understood that the simulation verification table is obtained by counting the preset output port corresponding to each second test code, the output sequence of the preset output port and the preset output information of the preset output port, and the simulation verification table contains the theoretical output result corresponding to each second test code.
The acquisition module is used for acquiring the output target information of each target output port according to the time sequence when simulating the target chip, and counting the target output ports with the corresponding time sequence to obtain an output port set.
It can be understood that when the target chip is simulated, the output target information of each target output port is acquired according to the time sequence, wherein the output target information is the actual information output by the target output port, and all the actual target output ports are counted to obtain an output port set, so that the output port set in the actual situation and the output target information output according to the time sequence can be conveniently compared with a theoretical simulation verification table, and the corresponding problem port is determined.
In some embodiments, the obtaining module (when simulating the target chip, obtaining the output target information of each target output port according to the time sequence, and counting the target output ports with the corresponding time sequence to obtain the output port set) includes:
and when the target chip is simulated, monitoring the target output ports of the target chip to obtain output target information of each target output port, and determining a time sequence label corresponding to each output target information.
The target output port is an actual output port of the target chip; the output target information is an actual signal output by each actual output port, and for example, the output target information can be a high level or a low level; the time sequence tag is a time sequence tag corresponding to each piece of output target information, for example: port 1 signals after 1s and port 2 signals after 2 s.
It can be understood that when the target chip is simulated, all the target output ports of the target chip are monitored, so that output target information of each target output port is obtained, the output target information can be high level or the ground level is not limited, and a time sequence label corresponding to the output target information is determined, so that the output target information of all the target output ports can be conveniently and statistically ordered according to the time sequence label.
And carrying out statistical sorting on the output target information of all the target output ports according to the time sequence labels of all the output target information, and sorting all the target output ports based on the statistical sorting of the output target information to obtain a port output sequence of an output port set.
The port output sequence of the output port set is a sequence obtained by sequencing output target information of corresponding target output ports based on a time sequence tag of the target information.
It can be understood that the port output sequence of the output port set is an actually output signal sequence when each second test code is simulated and verified, so that the ports which are easy to be problematic can be found by comparing actual and theoretical values.
And the verification simulation module is used for verifying the output port set based on the simulation verification table to obtain a problem port set, determining a plurality of third test codes corresponding to the second test codes according to the problem port set, and simulating the chip again based on the third test codes.
It can be understood that comparing the theoretical simulation verification table with the actual output port set to determine the problem ports, and counting all the problem ports to obtain the problem port set; and selecting a plurality of third test codes with the same function as the second test codes of the ports with problems, and simulating the third test codes with problems again on the chip.
For example: and (3) performing simulation verification on the target chip, wherein the crossroad has 3 directions to display, but 1 direction is not displayed, so that a code segment special for verifying the directions is obtained as a third test code, and subsequent simulation is performed.
In some embodiments, the obtaining module (verifying the output port set based on the simulation verification table to obtain a problem port set, determining a plurality of third test codes corresponding to the second test codes according to the problem port set, and simulating the target chip again based on the third test codes) includes:
if the second test code is relatively inconsistent with the class pair of the preset port set in the output port set obtained by the test, determining the port with the class problem in the output port set to obtain a first problem port set, and carrying out quantization processing on the first problem port set to obtain a first problem coefficient.
It can be understood that if the actual output port set of the second test code is inconsistent with the preset theoretical port set in comparison, the port with the type problem in the actual output port set can be determined to obtain a first problem port set, and the first problem port set is quantized to obtain a first problem coefficient.
For example: the actual output port sets in the process of performing the three-way intersection test are port 2, port 3 and port 4, but the preset port sets in the three-way intersection test are port 1, port 2 and port 3 in theory, so that the first problem port set is determined to be port 4 and port 1.
In some embodiments, (if the second test code is relatively inconsistent with the class pair of the output port set obtained by testing and the preset port set, determining that the port with the class problem in the output port set obtains a first problem port set, and performing quantization processing on the first problem port set to obtain a first problem coefficient) includes:
determining target output ports which exist in the output port set and do not exist in the preset port set as a first type of target output ports, and determining target output ports which do not exist in the output port set and do not exist in the preset port set as a second type of target output ports.
It can be understood that when a port exists in the actual output port set and a corresponding port does not exist in the theoretical preset port set, determining that the port is the first type of target output port; if a port does not exist in the actual output port set and exists in the theoretical preset port set, the port is taken as a second type of target output port.
For example: the actual output port sets in the process of performing the three-way intersection test are port 2, port 3 and port 4, but the preset port sets in the three-way intersection test theory are port 1, port 2 and port 3, and the first type of target output port is: port 4, the second type of target output port is: port 1.
And counting the first type of target output ports and the second type of target output ports to obtain a first problem port set.
It will be appreciated that statistics are performed on the first type of target output port and the second type of target output port to obtain all the first problem port sets, for example: the first problem port set is { Port 4, port 1}
Performing quantization calculation according to the first kind number of the first type of target output ports and the second kind number of the second type of target output ports to obtain a first problem coefficient, calculating the first problem coefficient by the following formula,
wherein, the liquid crystal display device comprises a liquid crystal display device,
for the first problem coefficient, +.>
For the first category number->
For the first category weight->
For the second category number->
For the second category weight->
For the question number weight, it is understood that the first question coefficient +. >
And the first kind of quantity->
Proportional, first question factor->
And the second kind of quantity->
In proportion to the purpose of the first typeThe target output port is a problem port which should not exist, so the first category weight +.>
Greater than the second category weight->
。
It can be understood that the first problem coefficient is obtained by performing quantization calculation on the first type number of the first type of target output ports and the second type number of the second type of target output ports, so that the simulation verification code can be conveniently selected according to the first problem coefficient and other problem coefficients.
After the category comparison is completed, comparing the port output sequence of the preset port set with the port output sequence of the output port set, determining the port with the sequence problem in the output port set to obtain a second problem port set, and carrying out quantization processing on the second problem port set to obtain a second problem coefficient.
It can be understood that after the class comparison is completed, comparing the port output sequence of the theoretical preset port set with the port output sequence of the actual output port set, checking whether a port with a sequence problem exists in the actual output port set, if so, taking the output port as a second problem port set, and carrying out quantization processing on the second problem port set to obtain a second problem coefficient.
For example: the traffic light detection theory of the three-fork intersection presets that the port output sequence of the port set is port 1 (1 s) -port 2 (2 s) -port 3 (3 s), and the port output sequence of the actual output port set is port 1 (1 s) -port 3 (2 s) -port 2 (3 s), so that the second problem port set is { port 3, port 2}.
In some embodiments, the steps of (after the category comparison is completed, comparing the port output sequence of the preset port set with the port output sequence of the output port set, determining the port having the sequence problem in the output port set to obtain a second problem port set, and performing quantization processing on the second problem port set to obtain a second problem coefficient) include:
labeling each preset output port in the port output sequence of the preset port set to obtain a preset output port with a first label, and labeling each target output port in the port output sequence of the output port set to obtain a target output port with a second label.
It may be appreciated that labeling each preset output port in the port output sequence of the preset port set to obtain a preset output port with a first label, and labeling each target output port in the port output sequence of the output port set to obtain a target output port with a second label, where the first label and the second label may be port 1, port a, etc. are not limited herein.
And counting the same number of preset output ports and target output ports corresponding to the first label and the second label with the same number respectively to obtain the same number of ports.
It can be understood that the number of the same labels of the theoretical output ports and the actual output ports is counted, and the same number of the ports is obtained, so that the subsequent quantization is convenient.
And counting different numbers of preset output ports and target output ports corresponding to the first label and the second label of the same number respectively to obtain different numbers of ports.
It can be understood that the number of different labels of the theoretical output port and the actual output port is counted to obtain the different numbers of the ports, so that the subsequent quantization is convenient.
Calculating according to the same number of ports and different numbers of ports to obtain a second problem coefficient of the quantization processing of the second problem port set, calculating the second problem coefficient by the following formula,
wherein, the liquid crystal display device comprises a liquid crystal display device,
is the second questionQuestion factors, & gt>
For different numbers of ports +.>
For the same number of ports->
As the port number weight, it can be understood that the second problem coefficient +.>
Different number from port->
Proportional, port number weight +.>
It may be set manually in advance, the larger the number of different numbers the larger the corresponding second problem coefficient.
After the port output sequence comparison is completed, determining a target output port which does not correspond to preset output information in the output port set based on a simulation verification table, obtaining a third problem port set, and carrying out quantization processing on the third problem port set to obtain a third problem coefficient.
It may be appreciated that after the port output sequence comparison is completed, determining, based on the simulation verification table, a preset output port of the output target information that does not correspond to the preset output information in the actual output port set, for example: the preset output information of the port 1 theory is high level, but the actual output target information is low level, so that a third problem port set is obtained, and the third problem port set is quantized to obtain a third problem coefficient.
In some embodiments, the (after the port output sequence comparison is completed, determining, based on the simulation verification table, a target output port in the output port set, which does not correspond to the preset output information, to obtain a third problem port set, and performing quantization processing on the third problem port set to obtain a third problem coefficient) includes:
and counting the same quantity of output target information of the target output port as corresponding output target information to obtain the same quantity of information.
It can be understood that the same quantity of the output target information of the actual target output port and the corresponding theoretical preset output information is counted, so that the same quantity of the information is obtained, and the subsequent quantization processing is convenient.
And counting the different amounts of the output target information of the target output port and the corresponding preset output information to obtain the different amounts of the information.
It can be understood that the different amounts of the output target information of the actual target output port and the corresponding theoretical preset output information are counted to obtain the different amounts of the information, so that the subsequent quantization processing is convenient.
Calculating according to the same quantity of the information and different quantities of the information to obtain a third problem coefficient by carrying out quantization processing on a third problem port set, calculating the third problem coefficient by the following formula,
wherein, the liquid crystal display device comprises a liquid crystal display device,
for the third problem coefficient, +.>
For different numbers of ports +.>
For the same number of ports->
For the information quantity weight, it is understood that the third problem coefficient +.>
Different number from port->
Become positiveThe greater the number of ports is, the greater the corresponding third problem coefficient.
And counting the first problem coefficient, the second problem coefficient and the third problem coefficient corresponding to each second test code, determining the code selection number of the third test codes corresponding to the second test codes, and selecting the third test codes corresponding to the code selection number to simulate the chip again.
It can be understood that, according to statistics on the first problem coefficient, the second problem coefficient and the third problem coefficient corresponding to each second test code, the code selection number of the corresponding third test code is determined, the larger the problem coefficient is, the larger the corresponding selection number is, and the third test code corresponding to the code selection number is selected to simulate the chip again.
In some embodiments, the step of (counting the first problem coefficient, the second problem coefficient, and the third problem coefficient corresponding to each second test code, determining the code picking number of the third test code corresponding to the second test code, and selecting the third test code corresponding to the code picking number to simulate the chip again) includes:
and counting the first problem coefficient, the second problem coefficient and the third problem coefficient corresponding to each second test code, and performing comprehensive calculation to obtain a comprehensive problem coefficient.
It can be understood that the first problem coefficient, the second problem coefficient and the third problem coefficient corresponding to each second test code are comprehensively calculated so as to obtain the comprehensive problem coefficient, so that the code selection quantity can be conveniently generated according to the comprehensive problem coefficient.
Comparing the comprehensive problem coefficient with a preset problem coefficient to obtain a coefficient difference value, calculating according to the coefficient difference value and the preset code quantity to obtain the code selection quantity of the third test code, calculating the code selection quantity of the third test code by the following formula,
wherein, the liquid crystal display device comprises a liquid crystal display device,
selecting a number, < > -for the code of the third test code>
For the preset problem coefficient, +.>
Normalized value for coefficient>
For the preset code quantity, ++>
For the number weight value, it is understood that the code of the third test code picks the number +.>
And third problem coefficient->
Proportional, number of code picks of third test code +.>
Coefficient of second problem
Proportional, number of code picks of third test code +.>
And the first question factor->
Proportional, preset code quantity
The method can be set manually in advance, and the larger the problem coefficient is, the larger the corresponding code selection quantity is.
If the code selection number is not an integer, rounding the code selection number, and selecting a third test code of the same type as the second test code in a code database according to the code selection number.
It can be understood that if the number of codes selected is not an integer, the number of codes selected is integer-processed by rounding, a third test code of the same type as the second test code is selected in the code database based on the number of codes selected, and a code which is easy to cause a problem is selected for simulation verification again.
After judging that the user corrects the target chip again, simulating the target chip again based on the selected third test code.
It can be understood that, after the problem of the target chip is found in the simulation process, correction is performed, and after correction, a third test code which is easy to cause the problem is selected to simulate the target chip again.
On the basis of the above embodiment, the method further comprises:
and if the user is judged to adjust the code selection quantity of the third test code, comparing the code selection quantity adjusted by the user with the calculated code selection quantity to obtain a code quantity adjustment value.
It can be understood that if the user finds that the number of the code choices of the third test code is too large or too small, the corresponding adjustment is performed, the number of the code choices is increased or decreased, the code quantity adjustment value is obtained by comparing the number of the code choices adjusted by the user with the number of the code choices automatically calculated by the system, and the weight is conveniently trained according to the code quantity adjustment value.
If the code quantity adjusting value is larger than 0, the weight training model carries out increasing training on the digital weight value according to the code quantity adjusting value, and the number weight value after increasing training is used for adjusting the number weight value before increasing training.
It can be understood that if the code quantity adjustment value is greater than 0, the code selection quantity of the third test code is too small, the user performs the process of increasing the corresponding code quantity, and the weight training model performs the increasing training on the digital weight value according to the code quantity adjustment value.
If the code quantity adjusting value is smaller than 0, the weight training model carries out reduction training on the digital weight value according to the code quantity adjusting value, and the quantity weight value after the reduction training is used for adjusting the quantity weight value before the reduction training.
It can be understood that if the code quantity adjustment value is smaller than 0, the code selection quantity of the third test code is excessive, the user performs the reduction processing on the corresponding code quantity, and the weight training model performs the reduction training on the weight value of the number according to the code quantity adjustment value.
The weight training model trains the number of weight values by the following formula,
wherein, the liquid crystal display device comprises a liquid crystal display device,
to increase the number weight value after training, +.>
The number of codes adjusted for the user is chosen,
to increase training coefficient->
To reduce the number weight value after training, +.>
To reduce the training coefficient, it is understood that the number weight value +. >
And code quantity adjustment value->
Proportional, decreasing the number weight value +.>
And code quantity adjustment value->
Inversely proportional.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (6)
1. The chip simulation acceleration system with the automatic configuration optimizing function is characterized by comprising the following components:
the identification configuration module is used for identifying the chip specification to obtain first key information of the chip when receiving the simulation instruction of the target chip, and obtaining first configuration information of the chip simulation equipment to the target chip according to the first key information;
when receiving a simulation instruction for a target chip, identifying a chip specification to obtain first key information of the chip, and obtaining first configuration information of chip simulation equipment for the target chip according to the first key information, wherein the method comprises the following steps:
When a simulation instruction for a target chip is received, a chip specification corresponding to the target chip is called, and the chip specification is identified to obtain first key information of the chip, wherein the first key information at least comprises chip area information, highest frequency information, CPU type information, interface type information, core function information, IP information and PVT information;
the first key information is sent to a control device of the chip simulation equipment so that the chip simulation equipment carries out chip simulation according to the first configuration information;
the statistics module is used for determining a first test code corresponding to the target chip, segmenting the first test code according to the code segment function to obtain a plurality of second test codes, and counting a test preset result corresponding to each second test code;
the determining module is used for determining a plurality of preset output ports of the target chip, counting all preset output ports corresponding to each second test code to obtain preset port sets, and counting preset output information of the preset output ports in each preset port set to obtain a simulation verification table;
determining a plurality of preset output ports of the target chip, counting all preset output ports corresponding to each second test code to obtain a preset port set, and counting preset output information of preset output ports in each preset port set to obtain a simulation verification table, wherein the method comprises the following steps:
Counting all preset output ports corresponding to each second test code to obtain a preset port set, and sequencing the signal output sequence of the preset output ports in the preset port set to obtain a port output sequence of each preset port set;
counting preset output information of preset output ports in each preset port set according to the sequence of the preset output ports in the port output sequence to obtain a simulation verification table;
the acquisition module is used for acquiring output target information of each target output port according to the time sequence when simulating the target chip, and counting the target output ports with corresponding time sequences to obtain an output port set;
when simulating a target chip, obtaining output target information of each target output port according to a time sequence, and counting the target output ports with corresponding time sequences to obtain an output port set, wherein the method comprises the following steps:
when the target chip is simulated, monitoring target output ports of the target chip to obtain output target information of each target output port, and determining a time sequence label corresponding to each output target information;
according to the time sequence labels of all output target information, carrying out statistical sorting on the output target information of all target output ports, and sorting all target output ports based on the statistical sorting of the output target information to obtain a port output sequence of an output port set;
The verification simulation module is used for verifying the output port set based on the simulation verification table to obtain a problem port set, determining a plurality of third test codes corresponding to the second test codes according to the problem port set, and simulating the chip again based on the third test codes;
the step of verifying the output port set based on the simulation verification table to obtain a problem port set, determining a plurality of third test codes corresponding to the second test codes according to the problem port set, and simulating the target chip again based on the third test codes, wherein the step of simulating comprises the steps of:
if the second test code is relatively inconsistent with the class pair of the preset port set in the output port set obtained by the test, determining the port with the class problem in the output port set to obtain a first problem port set, and carrying out quantization processing on the first problem port set to obtain a first problem coefficient;
after the category comparison is completed, comparing the port output sequence of the preset port set with the port output sequence of the output port set, determining the port with sequence problem in the output port set to obtain a second problem port set, and carrying out quantization processing on the second problem port set to obtain a second problem coefficient;
After port output sequence comparison is completed, determining a target output port which does not correspond to preset output information in an output port set based on a simulation verification table to obtain a third problem port set, and carrying out quantization processing on the third problem port set to obtain a third problem coefficient;
and counting the first problem coefficient, the second problem coefficient and the third problem coefficient corresponding to each second test code, determining the code selection number of the third test codes corresponding to the second test codes, and selecting the third test codes corresponding to the code selection number to simulate the chip again.
2. The chip simulation acceleration system with automatic configuration optimization function of claim 1, wherein,
if the class pair of the output port set obtained by testing the second test code is relatively inconsistent with that of the preset port set, determining that the port with the class problem in the output port set obtains a first problem port set, and performing quantization processing on the first problem port set to obtain a first problem coefficient, wherein the method comprises the following steps:
determining target output ports which exist in the output port set and do not exist in the preset port set as first type target output ports, and determining target output ports which do not exist in the output port set and do not exist in the preset port set as second type target output ports;
Counting the first type of target output ports and the second type of target output ports to obtain a first problem port set;
performing quantization calculation according to the first kind number of the first type of target output ports and the second kind number of the second type of target output ports to obtain a first problem coefficient, calculating the first problem coefficient by the following formula,
3. The chip simulation acceleration system with automatic configuration optimization function of claim 2, wherein,
after the category comparison is completed, comparing the port output sequence of the preset port set with the port output sequence of the output port set, determining the port with the sequence problem in the output port set to obtain a second problem port set, and performing quantization processing on the second problem port set to obtain a second problem coefficient, wherein the method comprises the following steps:
labeling each preset output port in the port output sequence of the preset port set to obtain a preset output port with a first label, and labeling each target output port in the port output sequence of the output port set to obtain a target output port with a second label;
Counting the same number of preset output ports and target output ports corresponding to the first label and the second label of the same number respectively to obtain the same number of ports;
counting different numbers of preset output ports and target output ports corresponding to the first label and the second label of the same number respectively to obtain different numbers of ports;
calculating according to the same number of ports and different numbers of ports to obtain a second problem coefficient of the quantization processing of the second problem port set, calculating the second problem coefficient by the following formula,
4. The chip simulation acceleration system with automatic configuration optimization function of claim 3, wherein,
after the port output sequence comparison is completed, determining a target output port which does not correspond to preset output information in the output port set based on a simulation verification table to obtain a third problem port set, and performing quantization processing on the third problem port set to obtain a third problem coefficient, wherein the method comprises the following steps:
counting the same quantity of output target information of the target output port and corresponding preset output information to obtain the same quantity of information;
Counting the different numbers of the output target information of the target output port and the corresponding preset output information to obtain the different numbers of the information;
calculating according to the same quantity of the information and different quantities of the information to obtain a third problem coefficient by carrying out quantization processing on a third problem port set, calculating the third problem coefficient by the following formula,
5. The chip simulation acceleration system with automatic configuration optimization function of claim 4, wherein,
the statistics of the first problem coefficient, the second problem coefficient and the third problem coefficient corresponding to each second test code is performed, the code selection number of the third test codes corresponding to the second test codes is determined, the third test codes corresponding to the code selection number are selected, and the target chip is simulated again, including:
counting the first problem coefficient, the second problem coefficient and the third problem coefficient corresponding to each second test code, and performing comprehensive calculation to obtain a comprehensive problem coefficient;
comparing the comprehensive problem coefficient with a preset problem coefficient to obtain a coefficient difference value, calculating according to the coefficient difference value and the preset code quantity to obtain the code selection quantity of the third test code, calculating the code selection quantity of the third test code by the following formula,
if the code selection number is not an integer, rounding the code selection number, and selecting a third test code of the same type as the second test code in a code database according to the code selection number;
after judging that the user corrects the target chip again, simulating the target chip again based on the selected third test code.
6. The chip simulation acceleration system with automatic configuration optimization function according to claim 5, further comprising:
if the user is judged to adjust the code selection quantity of the third test code, comparing the code selection quantity adjusted by the user with the calculated code selection quantity to obtain a code quantity adjustment value;
if the code quantity adjusting value is larger than 0, the weight training model carries out increasing training on the digital weight value according to the code quantity adjusting value, and the number weight value after increasing training is used for adjusting the number weight value before increasing training;
If the code quantity adjusting value is smaller than 0, the weight training model carries out reduction training on the digital weight value according to the code quantity adjusting value, adjusts the quantity weight value before the reduction training on the quantity weight value after the reduction training, the weight training model carries out training on the quantity weight value through the following formula,
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