CN114564911A - Routing method, device and equipment of high-speed signal line and readable storage medium - Google Patents
Routing method, device and equipment of high-speed signal line and readable storage medium Download PDFInfo
- Publication number
- CN114564911A CN114564911A CN202210178392.5A CN202210178392A CN114564911A CN 114564911 A CN114564911 A CN 114564911A CN 202210178392 A CN202210178392 A CN 202210178392A CN 114564911 A CN114564911 A CN 114564911A
- Authority
- CN
- China
- Prior art keywords
- speed signal
- signal line
- target program
- routing
- program
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 54
- 238000001514 detection method Methods 0.000 claims abstract description 39
- 230000004044 response Effects 0.000 claims abstract description 21
- 230000015654 memory Effects 0.000 claims description 30
- 238000007689 inspection Methods 0.000 claims description 17
- 238000013461 design Methods 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 10
- 238000004891 communication Methods 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 239000011889 copper foil Substances 0.000 description 7
- 238000004088 simulation Methods 0.000 description 6
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000012935 Averaging Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
- G06F30/3953—Routing detailed
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention relates to the technical field of PCB design and discloses a high-speed signal line routing method, a high-speed signal line routing device, high-speed signal line routing equipment and a readable storage medium. Wherein, the method comprises the following steps: acquiring a target program for detecting a high-speed signal line of a board card; in response to an operation on a target program, determining avoidance information corresponding to the operation; and executing the target program based on the avoidance information, and determining the wiring area of the high-speed signal wire. By implementing the invention, the automatic detection of the high-speed signal line is realized, a wiring/layout engineer is not required to spend a large amount of time for detection, the labor is saved, the time cost is reduced, the detection efficiency is improved, the omission of manual detection is avoided by detecting the high-speed signal line through the target program, and the detection accuracy is improved.
Description
Technical Field
The invention relates to the technical field of PCB design, in particular to a high-speed signal line routing method, a high-speed signal line routing device, high-speed signal line routing equipment and a readable storage medium.
Background
Along with the performance of the current mainboard/server is better and faster, in the process of research and development of the server, no matter a mainboard or other functional boards are usually designed with high-speed signal lines, signals, copper foils and the like are difficult to avoid through the high-speed signal lines and the power plane, but the signals and the copper foils are easily interfered when passing through the high-speed signal lines and the power plane, the stability of the system is influenced, meanwhile, the high-speed signal lines are also interfered by the power and the signals, the overall performance of the system is influenced, and even data misjudgment can be caused.
In order to meet the signal quality requirement, the layout or wiring needs to be continuously modified in the PCB design, however, as long as there is any modification (including mechanism board type, schematic diagram update, device movement/deletion, device material replacement, etc.), the wiring/layout engineer needs to re-confirm whether each high-speed signal line between the stacked layers and the power plane is affected, and whether the design is still in compliance, which not only takes a lot of inspection time, increases time cost, wastes manpower, but also has the possibility of omission.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method, an apparatus, a device and a readable storage medium for routing a high-speed signal line, so as to solve the problem that a routing/layout engineer manually confirms that there is manpower waste and inspection omission in each high-speed signal line between a stacked layer and a power plane.
According to a first aspect, an embodiment of the present invention provides a method for routing a high-speed signal line, including: acquiring a target program for detecting a high-speed signal line of a board card; responding to the running operation of the target program, and determining avoidance information corresponding to the running operation; and executing the target program based on the avoidance information, and determining a routing area of the high-speed signal wire.
According to the high-speed signal wire routing method provided by the embodiment of the invention, the target program for detecting the board card high-speed signal wire is obtained, the avoidance information corresponding to the running operation is determined in response to the running operation of the target program, then the target program is executed according to the avoidance information, and the routing area of the high-speed signal wire is determined, so that other routing or copper foils are prevented from being arranged in the routing area, and the signal quality of the high-speed signal wire is ensured not to be influenced. According to the method, the routing area of the high-speed signal line is detected by executing the target program, a wiring/layout engineer does not need to spend a large amount of time for checking, the time cost is reduced, the manpower is saved, the automatic detection of the high-speed signal line is realized, the detection efficiency is improved, the target program is used for detecting the high-speed signal line, the omission of manual checking is avoided, and the detection accuracy is improved.
With reference to the first aspect, in a first implementation manner of the first aspect, the acquiring a target program for detecting a high-speed signal of a board includes: in response to a selection operation on a list of detection programs, the target program is determined based on the selection operation.
With reference to the first embodiment of the first aspect, in a second embodiment of the first aspect, the method further includes: responding to the writing operation of a program, and obtaining a detection program corresponding to the writing operation, wherein the detection program is a kill program; in response to an adding operation to the list of detection programs, adding the detection program to the list of detection programs based on the adding operation.
According to the high-speed signal line routing method provided by the embodiment of the invention, the target program is determined based on the selection operation by responding to the selection operation of the detection program list. The detection program list comprises a kill program used for detecting the layout of the board card high-speed signal line, and when the layout of the high-speed signal line is detected, the needed kill program can be selected from the kill program.
With reference to the first aspect, in a third implementation manner of the first aspect, the determining, in response to a running operation on the target program, avoidance information corresponding to the running operation includes: acquiring adjacent layer information and avoidance space corresponding to the high-speed signal line; responding to the input operation of the adjacent layer information, and obtaining adjacent layer avoidance data corresponding to the input operation; and determining the information of the adjacent layer and the avoidance interval as the avoidance information.
With reference to the third embodiment of the first aspect, in a fourth embodiment of the first aspect, the avoidance gap is 10 mils or 20 mils.
According to the routing method of the high-speed signal line, the adjacent layer information and the avoidance distance corresponding to the high-speed signal line are obtained, the adjacent layer avoidance data corresponding to the input operation is obtained in response to the input operation of the adjacent layer information, and the adjacent layer information and the avoidance distance are determined as the avoidance information. The method supports the wiring/layout engineer to input relevant information for detection, and is not limited by the experience of the wiring/layout engineer.
With reference to the first aspect, in a fifth implementation of the first aspect, the method further comprises: outputting a wiring result of the high-speed signal line; loading an inspection specification corresponding to the routing result based on the routing result; whether wiring of the high-speed signal line is in compliance is confirmed based on the inspection specification.
According to the wiring method of the high-speed signal line, provided by the embodiment of the invention, the wiring result of the high-speed signal line is output after detection is finished, and the inspection standard corresponding to the wiring result is loaded based on the wiring result, so that whether the wiring of the high-speed signal line is in compliance is confirmed according to the inspection standard, and the wiring of the high-speed signal line is conveniently adjusted in time when the wiring is not in compliance, so that the working stability of a system is ensured.
With reference to the fifth embodiment of the first aspect, in a sixth embodiment of the first aspect, the method further comprises: and outputting a command of finishing the running of the target program.
According to the wiring method of the high-speed signal line provided by the embodiment of the invention, the wiring/layout engineer is reminded to finish the wiring improvement of the high-speed signal line by outputting the command of finishing the operation of the target program.
According to a second aspect, an embodiment of the present invention provides a routing apparatus for a high-speed signal line, including: the acquisition module is used for acquiring a target program for detecting the high-speed signal line of the board card; the response module is used for responding to the running operation of the target program and determining avoidance information corresponding to the running operation; and the determining module is used for executing the target program based on the avoidance information and determining the routing area of the high-speed signal line.
According to the high-speed signal line routing device provided by the embodiment of the invention, the routing area of the high-speed signal line is detected by executing the target program, a routing/layout engineer does not need to spend a large amount of time for checking, the time cost is reduced, the manpower is saved, the automatic detection of the high-speed signal line is realized, the detection efficiency is improved, the high-speed signal line is detected by the target program, the omission of manual detection is avoided, and the detection accuracy is improved.
According to a third aspect, an embodiment of the present invention provides an electronic device, including: a memory and a processor, the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the method for routing the high-speed signal line according to the first aspect or any embodiment of the first aspect.
According to a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, where computer instructions are stored, and the computer instructions are configured to cause a computer to perform the method for routing a high-speed signal line according to the first aspect or any implementation manner of the first aspect.
It should be noted that, for corresponding beneficial effects of the electronic device and the computer-readable storage medium provided in the embodiments of the present invention, please refer to the description of corresponding contents in the method for routing the high-speed signal line, which is not described herein again.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a method for routing a high-speed signal line according to an embodiment of the invention;
fig. 2 is another flow chart of a method for routing a high-speed signal line according to an embodiment of the invention;
fig. 3 is another flow chart of a method for routing a high-speed signal line according to an embodiment of the invention;
FIG. 4 is a schematic physical structure diagram of a ribbon wire according to an embodiment of the invention;
FIG. 5 is a simulated schematic of high noise power supplies of adjacent tiers according to an embodiment of the invention;
FIG. 6 is a schematic diagram of a differential signal line according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a simulation of adjacent layer signal lines according to an embodiment of the invention;
FIG. 8 is a schematic diagram of the selection of adjacent layer power names according to an embodiment of the invention;
FIG. 9 is a schematic diagram illustrating the selection of adjacent layer signal names according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of an output table according to an embodiment of the invention;
fig. 11 is a block diagram of a routing apparatus for high-speed signal lines according to an embodiment of the invention;
fig. 12 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In accordance with an embodiment of the present invention, there is provided an embodiment of a method for routing high-speed signal lines, it should be noted that the steps shown in the flowchart of the drawings may be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in an order different from that shown.
In this embodiment, a method for routing a high-speed signal line is provided, which can be used in electronic devices, such as servers, computers, tablet computers, and the like, and fig. 1 is a flowchart of a method for routing a high-speed signal line according to an embodiment of the present invention, as shown in fig. 1, the flowchart includes the following steps:
and S11, acquiring a target program for detecting the high-speed signal line of the board.
The target program is a program written by technicians for detecting the high-speed signal line of the board card, and in the Cadence Layout design, the target program can be a written kill program. The target program comprises signal line and copper foil setting, angle setting, space setting, wiring layer forbidden design and the like, can assist a wiring/layout engineer in automatic detection and debugging during design on a PCB, and can prevent other signal lines, copper foils, parts and the like from entering the area where the high-speed signal line is located.
The target program may be selected from the detection program list by a routing/layout engineer, may be called locally from the electronic device, may be called from an external storage device, or may be obtained in other manners, which is not limited herein.
And S12, responding to the running operation of the target program, and determining avoidance information corresponding to the running operation.
After determining the target program, the wiring/layout engineer may operate the electronic device to execute the target program, and input adjacent layer information corresponding to the high-speed signal line to the electronic device, so that the electronic device can determine avoidance information of the high-speed signal line according to the adjacent layer information. The avoidance information is used for representing avoidance of a power supply or a signal of an adjacent layer to the high-speed signal wire.
Specifically, if the electronic device has a touch display screen, the wiring/layout engineer may touch a detection tag (such as "start detection", "start", and the like) on a display interface of the electronic device to run a target program, and input power information of an adjacent layer and signal information of the adjacent layer through the touch display screen; the detection tag can be selected by a peripheral device such as a keyboard or a mouse to execute the target program, and the adjacent layer power supply information and the adjacent layer signal information can be input to the electronic device by the peripheral device such as the keyboard. Accordingly, the electronic device may respond to the operation of the routing/layout engineer on the target program, execute a corresponding detection process according to the operation, and determine avoidance information corresponding to the operation.
And S13, executing a target program based on the avoidance information, and determining the routing area of the high-speed signal wire.
The electronic equipment executes the target program according to the obtained avoidance information, and the wiring position of the high-speed signal line between the stacks and the power plane can be detected through the target program, namely, the wiring area of the high-speed signal line between the stacks and the power plane is determined, so that other signal lines, copper foils and parts are prevented from entering the wiring area again.
According to the wiring method of the high-speed signal line, the wiring area of the high-speed signal line is detected by executing the target program, a wiring/layout engineer does not need to spend a large amount of time to check, the time cost is reduced, the manpower is saved, the automatic detection of the wiring area of the high-speed signal line is realized, the detection efficiency is improved, the wiring area of the high-speed signal line is detected by the target program, the omission of manual detection is avoided, and the detection accuracy is improved.
In this embodiment, a method for routing a high-speed signal line is provided, which can be used in electronic devices, such as servers, computers, tablet computers, and the like, and fig. 2 is a flowchart of a method for routing a high-speed signal line according to an embodiment of the present invention, as shown in fig. 2, the flowchart includes the following steps:
and S21, acquiring a target program for detecting the high-speed signal line of the board.
Specifically, the step S21 may include: in response to a selection operation on the detection program list, a target program is determined based on the selection operation.
The detection program list is a twist program menu, the detection program list comprises a plurality of twist programs, and different twist programs have different functions, such as a twist program for detecting a wiring distance, a twist program for detecting a differential line width and a line distance, a twist program for detecting a high-speed signal line and the like. The routing/layout engineer may select a corresponding drill program from the list of detection programs according to the PCB design requirements, for example, click the corresponding drill program through a mouse; or selecting the corresponding drill program by using the keyboard moving key. Accordingly, the electronic device may determine, in response to a selection operation of the routing/placement engineer on the list of detection programs, a target program corresponding to the selection operation from the list of detection programs.
Optionally, the target program is a drill program, and before performing step S21, the method may further include:
s201, responding to the program writing operation, and obtaining a detection program corresponding to the program writing operation, wherein the detection program is a kill program.
A technical developer may write a test program corresponding to the high-speed signal line according to the requirements of a wiring/layout engineer, a simulation engineer, and the like, and after the test program passes the test, the test program is used as a detection program for the high-speed signal line. When a technician writes a kill program, the electronic device may respond to the writing operation of the technician to generate a detection program corresponding to the writing operation.
S202, in response to the adding operation of the detection program list, the detection program is added to the detection program list based on the adding operation.
After the completion of the writing of the test program, the technical developer may add the test program to the test program list to enable the routing/placement engineer to invoke the program for high speed signal line testing. Accordingly, the electronic device may add the written detection program to the detection program list in response to an addition operation of the technical developer to the detection program list, for example, the technical developer may drag the detection program to the detection program list, and the electronic device may add the written detection program to the detection program list in response to the drag operation.
S22, in response to the execution operation on the target program, determining avoidance information corresponding to the execution operation.
Specifically, the step S22 may include:
and S221, acquiring adjacent layer information and avoidance distance corresponding to the high-speed signal line.
The adjacent layer is an adjacent wiring layer of the layer where the high-speed signal line is located, and the electronic device can determine the wiring layer adjacent to the electronic device according to the layer where the high-speed signal line is located. The avoidance distance is a wiring distance between the set high-line signal line and the main body of another object, and may be 10 mils or 20 mils, but may also be determined according to actual needs, and is not particularly limited herein.
S222, responding to the input operation of the information of the adjacent layer, and obtaining adjacent layer avoidance data corresponding to the input operation.
In order to avoid the influence of power supplies or other signals on the high-speed signal line, a routing/layout engineer can avoid the high-noise power supply name and the signal name, and can input the power supply name of the adjacent layer and the signal name of the adjacent layer into the electronic equipment. Accordingly, the electronic device can determine the adjacent layer back-off power supply and the adjacent layer back-off signal corresponding to the high-speed signal line in response to the input operation of the routing/layout engineer on the adjacent layer power supply name and the adjacent layer signal name.
S223, the adjacent layer information and the avoidance interval are determined as avoidance information.
The electronic equipment takes an adjacent layer avoidance power supply, an adjacent layer avoidance signal and an avoidance distance corresponding to the high-speed signal wire as routing avoidance information.
The principle of avoiding the adjacent layer high noise power supply and the adjacent layer signal is explained here.
(1) For high noise power supplies (e.g., high voltage 12V, 24V supplies) of adjacent layers: as shown in fig. 4, the physical structure of the strip line (strip line) is that the definition of the strip line (strip line) requires a ground plane (ground plane) regardless of the far layer (far layer) or the near layer (near layer), and the far layer is usually changed to a power plane (power plane) in consideration of the cost. According to the equivalent circuit, the signal line is connected to the ground or the power supply through the capacitor, the ground plane is at 0 potential, but the power plane can be suddenly dropped due to the unstable power supply in the board, so the phenomenon can be transmitted to the signal line through the capacitor, and the 12V can be determined as the most unstable power supply in the board according to experience, so the far layer cannot be set at 12V.
The high speed signal line is far from P12V due to cost and design considerations, and therefore needs to be far away to avoid noise interference. Taking a microstrip with a line width of 5 mils and a characteristic impedance of 50 Ω as an example, the simulation is performed according to the 3W principle, and as shown in the simulation result shown in fig. 5, the larger the distance between the signal line and the high voltage is, the voltage waveform is sagged (v × k)f) The less crosstalk, the better the impedance match and therefore the need to avoid high noise power supplies in adjacent layers.
(2) For adjacent layer signal lines: the high-speed signal lines of adjacent signal layers need to be crossed with tracks to avoid crosstalk interference. The amount of coupling will typically have an effect on the pitch and thickness, and the stripine makes turns every 100 mils (mils), an angle greater than 30 degrees. As shown in fig. 6, the interleaving distance between the Pair # 1 differential signal line and the Pair # 2 differential signal line affects the coupling amount, and theoretically, the coupling amount is better as it approaches 0. As shown in fig. 6, S1 represents the staggered distance (i.e., pitch) between the center point of the Pair # 1 differential signal line and the center point of the Pair # 2 differential signal line, and H2 represents the adjacent distance (i.e., thickness) between the Pair # 1 differential signal line and the Pair # 2 differential signal line.
The simulation result is shown in fig. 7, where H denotes the thickness and the number denotes a specific value, for example, H9 denotes that the adjacent distance of the Pair # 1 differential signal line and the Pair # 2 differential signal line is 9 mil; spacing represents the pitch. As can be seen from the simulation result shown in fig. 7, the larger H is, the smaller the coupling amount is, and the larger the differential signal interleaving pitch is, the smaller the coupling amount is, so that it is necessary to avoid the signal lines of adjacent layers.
And S23, executing a target program based on the avoidance information, and determining the routing area of the high-speed signal wire. For a detailed description, refer to the corresponding related description of the above embodiments, and are not repeated herein.
In the routing method for the high-speed signal line provided by this embodiment, the target program is determined based on the selection operation by responding to the selection operation on the detection program list. The detection program list comprises a kill program for detecting the layout of the board card high-speed signal line, and when the layout of the high-speed signal line is detected, the needed kill program can be selected from the kill program list; meanwhile, the method supports a routing/layout engineer to input relevant information for detection, and is not limited by the experience of the routing/layout engineer.
In this embodiment, a method for routing a high-speed signal line is provided, which can be used in electronic devices, such as servers, computers, tablet computers, and the like, fig. 3 is a flowchart of a method for routing a high-speed signal line according to an embodiment of the present invention, and as shown in fig. 3, the flowchart includes the following steps:
and S31, acquiring a target program for detecting the high-speed signal line of the board. For a detailed description, refer to the corresponding related description of the above embodiments, and are not repeated herein.
S32, in response to the execution operation on the target program, determining avoidance information corresponding to the execution operation. For a detailed description, refer to the corresponding related description of the above embodiments, and are not repeated herein.
And S33, executing a target program based on the avoidance information, and determining the routing area of the high-speed signal wire. For a detailed description, refer to the corresponding related description of the above embodiments, and are not repeated herein.
S34, the result of the wiring for the high-speed signal line is output.
After the target program in the electronic device completes the detection of the high-speed signal line, it may output the current wiring result of the high-speed signal line, for example, output a table containing the wiring information of the high-speed signal line, and represent the wiring position and the wiring area of the high-speed signal line with the wiring result.
S35, loading the checking specification corresponding to the wiring result based on the wiring result.
The electronic device may determine an inspection specification corresponding to the wiring result according to the currently output wiring result, and then load the corresponding inspection specification to inspect the current high-speed signal line.
S36, whether the wiring of the high-speed signal line is in compliance is confirmed based on the inspection specification.
The electronic equipment further detects whether the wiring of the high-speed signal wire meets the wiring specification according to the inspection specification, and if the wiring of the current high-speed signal wire is not in compliance, the electronic equipment can send out prompt information so that a wiring/layout engineer can adjust the wiring/layout engineer in time.
S37, a command to end the operation of the target program is output.
After completing the detection of the high-speed signal line, the electronic device may output an end instruction, such as Done, to remind the routing/layout engineer that the detection has been completed, which is convenient for the routing/layout engineer to proceed with other designs.
In the routing method for the high-speed signal line provided by this embodiment, after the detection is completed, the routing result of the high-speed signal line is output, and the inspection specification corresponding to the routing result is loaded based on the routing result, so as to confirm whether the routing of the high-speed signal line is in compliance according to the inspection specification, and it is convenient to adjust the routing of the high-speed signal line in time when the routing is not in compliance so as to ensure the working stability of the system. And reminding a wiring/layout engineer of finishing the wiring improvement of the high-speed signal wire by outputting a command of finishing the running of the target program.
The above method is explained here with a specific example: 1) running a written kill program for improving the noise suppression capability of the high-speed signal line between the laminated layers and the power plane; 2) inputting the name of avoiding the power supply of the adjacent layer: high Noise Shape, as shown in fig. 8, the High-speed signal line is set to avoid the P12V _ AUX copper foil, and after the [ Automatic averaging ] is executed, the signal line is automatically avoided by the adjacent power supply of P12V _ AUX, so as to avoid the interference of the High-speed signal line by the High Noise voltage of the adjacent layer; 3) inputting the names of the avoidance signals of adjacent layers: high Speed Overlap, as shown in fig. 9, the signal of the L7 layer and the signal of the L8 layer are set to avoid for the High Speed signal line, and the signal will automatically avoid after executing the Automatic averaging to avoid the High Speed signal crosstalk; 4) outputting a routing table, as shown in FIG. 10, with which specifications can be loaded for inspection; 5) and (5) running a Skill program ending instruction and outputting a Done command.
In this embodiment, a high-speed signal line routing device is further provided, and the device is used to implement the foregoing embodiments and preferred embodiments, and the description of the device is omitted for brevity. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.
The present embodiment provides a high-speed signal line routing apparatus, as shown in fig. 11, including:
and an obtaining module 41, configured to obtain an object program for detecting a board high-speed signal line. For detailed description, reference is made to the corresponding related description of the above method embodiments, and details are not repeated herein.
A response module 42 is configured to determine avoidance information corresponding to the run operation in response to the run operation on the target program. For a detailed description, reference is made to the related description corresponding to the above method embodiment, which is not repeated herein.
And the determining module 43 is configured to execute a target program based on the avoidance information, and determine a routing area of the high-speed signal line. For a detailed description, reference is made to the related description corresponding to the above method embodiment, which is not repeated herein.
The high-speed signal line that this embodiment provided walks the line device detects high-speed signal line through carrying out the object program, need not to lay wire/overall arrangement engineer and spend a large amount of time to inspect, has reduced the time cost, has saved the manpower, has realized the automated inspection of high-speed signal line, has improved detection efficiency, and detects high-speed signal line through the object program, has avoided the omission of artifical inspection, has improved the detection accuracy.
The routing of the high-speed signal lines in this embodiment is in the form of functional units, where a unit refers to an ASIC circuit, a processor and a memory executing one or more software or fixed programs, and/or other devices that can provide the above-described functionality.
Further functional descriptions of the modules are the same as those of the corresponding embodiments, and are not repeated herein.
An embodiment of the invention further provides an electronic device, which has the routing apparatus for high-speed signal lines shown in fig. 11.
Referring to fig. 12, fig. 12 is a schematic structural diagram of an electronic device according to an alternative embodiment of the present invention, and as shown in fig. 12, the electronic device may include: at least one processor 501, such as a CPU (Central Processing Unit), at least one communication interface 503, memory 504, and at least one communication bus 502. Wherein a communication bus 502 is used to enable connective communication between these components. The communication interface 503 may include a Display (Display) and a Keyboard (Keyboard), and the optional communication interface 503 may also include a standard wired interface and a standard wireless interface. The Memory 504 may be a Random Access Memory (RAM) or a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. The memory 504 may optionally be at least one storage device located remotely from the processor 501. Wherein the processor 501 may be in connection with the apparatus described in fig. 11, an application program is stored in the memory 504, and the processor 501 calls the program code stored in the memory 504 for performing any of the above-mentioned method steps.
The communication bus 502 may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus 502 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown in FIG. 12, but that does not indicate only one bus or one type of bus.
The memory 504 may include a volatile memory (RAM), such as a random-access memory (RAM); the memory may also include a non-volatile memory (english: non-volatile memory), such as a flash memory (english: flash memory), a hard disk (english: hard disk drive, abbreviated: HDD) or a solid-state drive (english: SSD); the memory 504 may also comprise a combination of the above types of memory.
The processor 501 may be a Central Processing Unit (CPU), a Network Processor (NP), or a combination of CPU and NP.
The processor 501 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof.
Optionally, the memory 504 is also used to store program instructions. The processor 501 may call a program instruction to implement the method for routing the high-speed signal line as shown in the embodiments of fig. 1 to fig. 3 of the present application.
The embodiment of the present invention further provides a non-transitory computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions may execute the processing method of the routing method for a high-speed signal line in any of the above method embodiments. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, abbreviated as HDD), a Solid State Drive (SSD), or the like; the storage medium may also comprise a combination of memories of the kind described above.
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.
Claims (10)
1. A method for routing a high-speed signal line includes:
acquiring a target program for detecting a high-speed signal line of a board card;
responding to the running operation of the target program, and determining avoidance information corresponding to the running operation;
and executing the target program based on the avoidance information, and determining a routing area of the high-speed signal wire.
2. The method of claim 1, wherein obtaining the target program for detecting the board high-speed signal comprises:
in response to a selection operation on a list of detection programs, the target program is determined based on the selection operation.
3. The method of claim 2, further comprising:
responding to the writing operation of a program, and obtaining a detection program corresponding to the writing operation, wherein the detection program is a kill program;
in response to an adding operation to the list of detection programs, adding the detection program to the list of detection programs based on the adding operation.
4. The method of claim 1, wherein determining back-off information corresponding to a running operation of the target program in response to the running operation comprises:
acquiring adjacent layer information and avoidance space corresponding to the high-speed signal line;
responding to the input operation of the information of the adjacent layer, and obtaining the avoidance data of the adjacent layer corresponding to the input operation;
and determining the information of the adjacent layer and the avoidance interval as the avoidance information.
5. The method of claim 4, wherein the relief spacing is 10 mils or 20 mils.
6. The method of claim 1, further comprising:
outputting a wiring result of the high-speed signal line;
loading an inspection specification corresponding to the routing result based on the routing result;
whether wiring of the high-speed signal line is in compliance is confirmed based on the inspection specification.
7. The method of claim 6, further comprising:
and outputting a command of finishing the running of the target program.
8. A high-speed signal line routing device is characterized by comprising:
the acquisition module is used for acquiring a target program for detecting the high-speed signal line of the board card;
the response module is used for responding to the running operation of the target program and determining avoidance information corresponding to the running operation;
and the determining module is used for executing the target program based on the avoidance information and determining the routing area of the high-speed signal line.
9. An electronic device, comprising:
a memory and a processor, the memory and the processor are communicatively connected with each other, the memory stores computer instructions, and the processor executes the computer instructions to execute the high-speed signal line routing method according to any one of claims 1 to 7.
10. A computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions for causing a computer to execute the method for routing a high-speed signal line according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210178392.5A CN114564911A (en) | 2022-02-25 | 2022-02-25 | Routing method, device and equipment of high-speed signal line and readable storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210178392.5A CN114564911A (en) | 2022-02-25 | 2022-02-25 | Routing method, device and equipment of high-speed signal line and readable storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114564911A true CN114564911A (en) | 2022-05-31 |
Family
ID=81715870
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210178392.5A Withdrawn CN114564911A (en) | 2022-02-25 | 2022-02-25 | Routing method, device and equipment of high-speed signal line and readable storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114564911A (en) |
-
2022
- 2022-02-25 CN CN202210178392.5A patent/CN114564911A/en not_active Withdrawn
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104573243B (en) | PCB design layout auditing device | |
| US8413097B2 (en) | Computing device and method for checking design of printed circuit board layout file | |
| US20110185332A1 (en) | Model based simulation and optimization methodology for design checking | |
| CN111770637A (en) | Routing method, routing device and routing equipment for pins on PCB | |
| CN115544604A (en) | Application software layer model generation method and device and electronic equipment | |
| CN115329712A (en) | PCB (printed circuit board) routing generation method, device and equipment and server board card | |
| CN113466733A (en) | Power performance testing method and device, electronic equipment and storage medium | |
| CN114564911A (en) | Routing method, device and equipment of high-speed signal line and readable storage medium | |
| CN112446182A (en) | Method and equipment for optimizing signal integrity | |
| CN113939091B (en) | Impedance matching design method and device of link electrostatic impedance device and printed circuit board | |
| US8495537B1 (en) | Timing analysis of an array circuit cross section | |
| US8434050B2 (en) | Printed circuit board layout system and method | |
| US8484840B2 (en) | Leading wiring method, leading wiring program, and leading wiring apparatus | |
| JP2000020573A (en) | System for processing printed board wiring and its method | |
| CN112685992A (en) | Skill-based method and system for quickly searching cross-plane routing | |
| CN115392175B (en) | Circuit design error processing method, device and medium | |
| US20080155341A1 (en) | Application level testing of instruction caches in multi-processor/multi-core systems | |
| US7844408B2 (en) | System and method for time domain reflectometry testing | |
| US12045554B2 (en) | Circuit simulation method and device | |
| US7321967B2 (en) | System and method for configuring capabilities of printed circuit boards | |
| US20080028346A1 (en) | Method and system for determining required quantity of testing points on a circuit layout diagram | |
| CN111929495B (en) | Memory power consumption testing device, system and application method thereof | |
| US10445459B1 (en) | Interactive routing with poly vias | |
| US7761835B2 (en) | Semiconductor device design method, semiconductor device design system, and computer program for extracting parasitic parameters | |
| CN113312770A (en) | Display panel design method and device and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20220531 |
|
| WW01 | Invention patent application withdrawn after publication |