CN114564910A

CN114564910A - Method for balancing time sequence

Info

Publication number: CN114564910A
Application number: CN202210185981.6A
Authority: CN
Inventors: 周喆
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2022-02-28
Filing date: 2022-02-28
Publication date: 2022-05-31

Abstract

The invention provides a method for balancing time sequence, which comprises the steps of providing a design layout, wherein the design layout comprises a plurality of design modules, and each design module comprises a plurality of ports; defining a design module needing time sequence balance; setting a design rule of time sequence balance, wherein the design rule comprises that the defined design modules are arranged in parallel at a set distance, so that when ports among the defined design modules are connected, the bus length of the connection is shortest; and resetting the positions of the plurality of design modules according to the design rules, and connecting the ports among the design modules. The method of the invention finds out modules related to address and data, and places units related to timing sequence balance close to ensure that bus connection is balanced and routing is short, and the bus connection is balanced and short due to the redesigned layout, the data register corresponds to a memory port.

Description

Method for balancing time sequence

Technical Field

The invention relates to the technical field of semiconductors, in particular to a method for balancing time sequences.

Background

The memory design kit needs to provide a timing model, and the precision of the timing model is related to the speed of the memory application when the address establishment time and the access time are modeled. Typically, the address setup time is only within 1ns (130 below process), and errors between address buses directly affect the address setup modeling accuracy. Conventional bus circuits and corresponding layouts are shown in fig. 1 to 4, and because the positions of modules or units are different, the connection lengths between buses are greatly different, and corresponding parasitic capacitances are also different.

When the modules or units are placed, the lengths of paths between high and low bits of the bus are not fully considered, which causes unbalanced connection between high and low bits of the bus (data and address bus), thereby causing the difference of capacitive load to affect the path delay, even when the load difference is large, the driving units are added, causing the path delay difference between high and low bits of the bus to be larger, i.e. it is difficult to balance the time sequence between buses.

Therefore, a method for balancing timing is needed to reduce errors between address buses, so as to improve the modeling precision of address establishment and reduce the address establishment time.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for balancing timing, which is used to solve the problem that when a module or a unit is placed in the prior art, the lengths of paths between high and low bits of a bus are not fully considered, so that the connection between the high and low bits of the bus is unbalanced, and thus the difference of capacitive loads affects the path delay, and even when the load difference is large, a driving unit is added, so that the difference of the path delay between the high and low bits of the bus is large.

To achieve the above and other related objects, the present invention provides a method for balancing timing, comprising:

providing a design layout, wherein the design layout comprises a plurality of design modules, and each design module comprises a plurality of ports;

step two, defining the design module needing time sequence balance;

step three, formulating a design rule of the time sequence balance, wherein the design rule comprises the following steps: the defined design modules are arranged in parallel relatively at a set distance, so that when ports among the defined design modules are connected, the length of a bus of the connection is smaller than that of buses at other positions;

and step four, resetting the positions of the plurality of design modules according to the design rule, and connecting the ports among the design modules.

Preferably, a plurality of the design modules in the first step include a combinational logic circuit, a sequential logic circuit and a memory.

Preferably, the sequential logic circuit in the first step is a circuit of a register.

Preferably, the registers in step one include an address register and a data register.

Preferably, the design module that needs to perform the timing balance in step two is the register.

Preferably, the set distance in step three is: the distance between two of the design modules is less than the size of the smallest of the design modules.

Preferably, the total line length in step three includes: the total length of a connecting line between an address port of the memory and an output port of the address register; and the total length of a connecting line between the data port of the memory and the input port of the data register.

Preferably, in step four, the port connections between the memory and the address register and the port connections between the memory and the data register are reset according to the setting rule.

Preferably, the method further comprises a fifth step of performing circuit timing simulation verification on the design layout rearranged by the design rule.

Preferably, in the fifth step, after the connection lines between the memory and the ports between the address register and the data register are reset according to the setting rule, circuit timing simulation verification is performed, so that the delay difference of data transmission between the address register and the data register is less than 0.05 ns.

As described above, the timing sequence balancing method of the present invention has the following beneficial effects:

the invention finds out modules related to addresses and data, places units related to timing sequence balance close to ensure that bus connection is balanced and routing is short, redesigns the layout, the data register corresponds to a memory port, and the bus connection is balanced and short.

Drawings

FIG. 1 is a schematic diagram of a prior art bus circuit;

FIG. 2 is a schematic diagram of a layout of the prior art;

FIG. 3 is a diagram illustrating a prior art memory and address register connection;

FIG. 4 is a schematic diagram of a prior art memory and data register connection;

FIG. 5 is a schematic diagram of the layout of the present invention;

FIG. 6 is a schematic diagram illustrating circuit timing simulation verification according to the present invention;

FIG. 7 is a schematic process flow diagram of the present invention.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Referring to fig. 7, the present invention provides a method for balancing timing, including:

providing a design layout, wherein the design layout comprises a plurality of design modules, each design module comprises a plurality of ports, and the ports between two adjacent design modules need to be connected in the design layout under the normal condition;

in an alternative embodiment, the plurality of design modules in the first step include a combinational logic circuit including an encoder, a decoder, a data selector, an adder, a numerical comparator, etc., a sequential logic circuit including a register, a counter, a sequential pulse generator, a sequential signal generator, etc., and a memory including a Read Only Memory (ROM) and a Random Access Memory (RAM).

In an alternative embodiment, the sequential logic circuit in the first step is a register.

In an alternative embodiment, the registers in step one include an address register and a data register.

In an alternative embodiment, the design module to be time sequence balanced in step two is a register circuit.

The register functions to store binary codes and is formed by combining flip-flops having a storage function. One flip-flop can store 1-bit binary codes, so a register for storing n-bit binary codes needs to be formed by n flip-flops.

The memory cell is actually one type of sequential logic circuit. The functions of the memory can be divided into a Read Only Memory (ROM) and a Random Access Memory (RAM) according to the use types of the memory, and the functions of the memory are greatly different, so that the description is different. The memory is a collection of many memory cells, arranged in order of cell number. Each cell is made up of a number of binary bits to represent the value stored in the memory cell.

Step two, defining a design module which needs to be subjected to time sequence balance in a plurality of design modules;

in an alternative embodiment, the design module requiring timing balance in step two is a module for finding out addresses and data, and may be a register.

Step three, formulating a design rule of time sequence balance, wherein the design rule comprises the following steps: the defined design modules are arranged in parallel relatively at a set distance, namely the positions of the defined design modules are continuously adjusted, so that when ports among the defined design modules are connected, the length of a bus of the connection is smaller than that of buses at other positions;

in an alternative embodiment, the set distance in step three is: the distance between the two design modules is less than the minimum size of the design modules.

In an alternative embodiment, referring to FIG. 6, the bus length in step three includes: total length of connecting line between address port of the memory and output port of the address register; and the total length of the connection line between the data port of the memory and the input port of the data register, the bus length of which is the shortest compared with that of fig. 2 to 4.

In an alternative embodiment, in step four, the port connection between the memory and the address register and the data register is reset according to the setting rule.

In an optional implementation, the method further includes a fifth step of performing circuit timing simulation verification on the design layout rearranged by the design rule.

In an alternative embodiment, referring to fig. 6, in step five, after the connection lines between the memory and the ports between the address register and the data register are reset according to the setting rule, the circuit timing simulation verification is performed, so that the delay difference of data transmission between the address register and the data register is less than 0.05 ns.

It should be noted that the drawings provided in this embodiment are only for schematically illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings and not drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of each component in actual implementation may be arbitrarily changed, and the component layout may be more complicated.

In summary, the present invention finds out the modules related to address and data, and places the units related to timing balance close to each other, so as to ensure balanced bus connection and short routing, and the redesigned layout has the data register corresponding to the memory port and balanced and short bus connection. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. A method for balancing timing, comprising:

step two, defining the design module needing time sequence balance;

2. The method of claim 1, wherein: the plurality of design modules in the first step comprise a combinational logic circuit, a sequential logic circuit and a memory.

3. The method of claim 2, wherein: the sequential logic circuit in the first step is a register circuit.

4. The method of claim 3, wherein: the registers in step one comprise address registers and data registers.

5. The method of claim 4, wherein: and in the second step, the design module which needs to perform the time sequence balance is the register.

6. The method of claim 1, wherein: the set distance in step three is: the distance between two of the design modules is less than the design module of the smallest size among the design modules.

7. The method of claim 4, wherein: the bus length in step three includes: the total length of a connecting line between an address port of the memory and an output port of the address register; and the total length of a connecting line between the data port of the memory and the input port of the data register.

8. The method of claim 4, wherein: in the fourth step, the port connection lines between the memory and the address register and between the memory and the data register are reset according to the setting rule.

9. The method of claim 8, wherein: and fifthly, performing circuit time sequence simulation verification on the design layout reset according to the design rule.

10. The method of claim 9, wherein: and verifying the time sequence simulation in the step five, so that the delay difference of data transmission between the address register and the data register is less than 0.05 ns.