CN115169270A - Memory conversion method, system, equipment and storage medium - Google Patents
Memory conversion method, system, equipment and storage medium Download PDFInfo
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Abstract
The invention discloses a memory conversion method, which comprises the following steps: obtaining an initial netlist; traversing the initial netlist to determine a plurality of first memories and a plurality of second memories that can be mapped as BSRAMs; acquiring the number and the address size of the read-write ports of each first memory and each second memory; and mapping the first memory into BSRAMs of corresponding types and numbers according to the number, data width and address width of the read-write ports of each first memory, or mapping the second memory into BSRAMs of corresponding types and numbers according to the number, data width and address width of the read-write ports of each second memory. The invention also discloses a system, a computer device and a readable storage medium. The scheme provided by the invention can be applied to chip design or FPGA design, when the design comprises a logic-expressed memory, the memory can be replaced by 1 or a plurality of BSRAMs, and the chip area occupied by the memory can be effectively reduced.
Description
Technical Field
The invention relates to the field of chip design, in particular to a memory conversion method, a system, equipment and a storage medium.
Background
With the development of modern EDA technology, programmable logic devices have been widely used in digital signal processing, network communication, industrial control, and computer related products. FPGA technology has become more and more widely used in electronic design in recent years. The FPGA has the characteristics of hardware logic programmability, large capacity, high speed, embedded storage array and the like, so that the FPGA is particularly suitable for the application of occasions such as high-speed data acquisition, complex control logic, accurate sequential logic and the like. The memory is an essential module in digital application systems.
Because the BSRAM memory models of FPGA chips of different manufacturers or different models are slightly different, in the FPGA design, a user uses a logic language to describe a memory to adapt to the FPGAs of different models, and the memory is mapped into different memories in the comprehensive process.
When a memory exists in the design, the memory IP core is directly used for mapping the memory after the integration is finished, if the mapping is improper, or the address width or the data width of the memory exceeds the input width of the IP core of the memory, more memory resources are occupied or more logic resources and wiring resources are generated in the integration process, and the subsequent layout and wiring are influenced.
Therefore, when unreasonable memories or logic resources are used for expressing the memories, the circuits are complex, the occupied area of a chip is large, layout and wiring are affected, and power consumption is increased accordingly.
Disclosure of Invention
In view of the above, in order to overcome at least one aspect of the above problems, an embodiment of the present invention provides a memory translation method, including the following steps:
obtaining an initial netlist;
traversing the initial netlist to determine a plurality of first memories and a plurality of second memories that can be mapped as BSRAMs;
acquiring the number and the address size of the read-write ports of each first memory and each second memory;
and mapping the first memory into BSRAMs of corresponding types and numbers according to the number, data width and address width of the read-write ports of each first memory, or mapping the second memory into BSRAMs of corresponding types and numbers according to the number, data width and address width of the read-write ports of each second memory.
In some embodiments, traversing the initial netlist to determine a plurality of first memories and a plurality of second memories that can be mapped as BSRAMs further comprises:
in response to the attribute constraint of the memory in the initial netlist being BSRAM, determining that the memory is a first memory capable of being mapped as BSRAM;
and in response to the fact that the memory in the initial netlist has no attribute constraint and the data width or the address width is larger than a preset value, determining that the memory is a second memory capable of being mapped into the BSRAM.
In some embodiments, further comprising:
obtaining attribute constraints of other memories which cannot be mapped into the BSRAM in the initial netlist;
mapping the attribute constraint of the other memory to SRAM in response to the attribute constraint;
mapping the other memory to a register in response to the attribute constraint of the other memory being a register.
In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs according to the number of read/write ports of the first memory, or mapping each second memory to a corresponding type and number of BSRAMs according to the number of read/write ports of the second memory, further includes:
mapping the first memory to a ROM in response to the first memory having only one read port;
mapping the second memory to a ROM in response to the second memory having only one read port.
In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs according to the number of read/write ports of the first memory, or mapping each second memory to a corresponding type and number of BSRAMs according to the number of read/write ports of the second memory, further includes:
mapping a read port and a write port of the first memory into a SP (service provider) in response to the first memory having the read port and the write port with the same address;
and mapping the second memory to be SP in response to the second memory having a read port and a write port and the read port and the write port having the same address.
In some embodiments, mapping each first memory into a corresponding type and number of BSRAMs according to the number of read/write ports of the first memory, or mapping each second memory into a corresponding type and number of BSRAMs according to the number of read/write ports of the second memory, further comprises:
in response to the first memory having a read port and a write port and the addresses of the read port and the write port being different, mapping the first memory to be an SDP;
and mapping the second memory to be SDP in response to that the second memory has a read port and a write port, and the addresses of the read port and the write port are different.
In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs according to the number of read/write ports of the first memory, or mapping each second memory to a corresponding type and number of BSRAMs according to the number of read/write ports of the second memory, further includes:
mapping the first memory into a DP in response to the first memory having one read port and two write ports and the read port and one of the write ports having the same address, or the first memory having two read ports and one write port and the write port and one of the read ports having the same address, or the first memory having two read ports and two write ports and the two write ports having the same address as one of the read ports, respectively;
and mapping the DP into a second memory in response to the second memory having one read port and two write ports and the read port and one of the write ports having the same address, or the second memory having two read ports and one write port and the write port and one of the read ports having the same address, or the second memory having two read ports and two write ports and the two write ports having the same address as one of the read ports, respectively.
In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs according to the data width and address width thereof, or mapping each second memory to a corresponding type and number of BSRAMs according to the data width and address width thereof, further comprises:
in response to that the address width and the data width of the BSRAM to be mapped are both larger than those of the first memory, directly mapping the first memory to the BSRAM;
and directly mapping the second memory to the BSRAM in response to that the address width and the data width of the BSRAM to be mapped are larger than those of the second memory.
In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs according to the data width and address width thereof, or mapping each second memory to a corresponding type and number of BSRAMs according to the data width and address width thereof, further comprises:
in response to the fact that the address width of the BSRAM to be mapped is larger than that of the first memory, and the data width is smaller than that of the first memory, mapping the first memory into a plurality of BSRAMs, wherein the sum of the data widths of the BSRAMs is larger than that of the first memory;
and mapping the second memory into a plurality of BSRAMs in response to the fact that the address width of the BSRAM to be mapped is larger than that of the second memory and the data width is smaller than that of the second memory, wherein the sum of the data widths of the BSRAMs is larger than that of the second memory.
In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs according to the data width and address width thereof, or mapping each second memory to a corresponding type and number of BSRAMs according to the data width and address width thereof, further comprises:
in response to the address width of the BSRAM to be mapped being smaller than the address width of the first memory and the data width being larger than the data width of the first memory, mapping the first memory into a plurality of BSRAMs, wherein the plurality of BSRAMs are enabled by a number of preset address bits to determine the used BSRAMs, and selecting the output of data by a number of preset address bits;
in response to the address width of the BSRAM to be mapped being smaller than the address width of the second memory and the data width being larger than the data width of the second memory, mapping the second memory into a plurality of BSRAMs, wherein the plurality of BSRAMs are enabled by a number of preset address bits to determine the used BSRAMs, and selecting the output of data by a number of preset address bits.
In some embodiments, the plurality of BSRAMs enabled by a number of preset address bits to determine the BSRAM used and the output of the data selected by the number of preset address bits further comprises:
utilizing a logic circuit to operate the plurality of preset address bits to determine the used BSRAM;
and selecting the output of the data by utilizing the multi-stage MUX, wherein the preset address bits are respectively used as a conducting signal of each MUX in the multi-stage MUX.
In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs according to the data width and address width thereof, or mapping each second memory to a corresponding type and number of BSRAMs according to the data width and address width thereof, further comprises:
in response to that the address width of the BSRAM to be mapped is smaller than that of the first memory and the data width is smaller than that of the first memory, mapping the first memory into a plurality of BSRAMs, wherein the plurality of BSRAMs can be enabled through a plurality of preset address bits to determine the used BSRAMs, and selecting the output of data through the plurality of preset address bits, remapping each of the mapped BSRAMs into a plurality of BSRAMs, wherein the sum of the data widths of the plurality of BSRAMs remapped by each BSRAM is larger than that of the first memory;
in response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the second memory, the data width is smaller than the data width of the second memory, the second memory is mapped into a plurality of BSRAMs, the BSRAMs are enabled through a plurality of preset address bits to determine the used BSRAMs, the data are selected through the preset address bits, each BSRAM obtained through mapping is mapped into a plurality of BSRAMs again, and the sum of the data widths of the BSRAMs obtained through remapping of each BSRAM is larger than the data width of the second memory.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a memory conversion system, including:
a first obtaining module configured to obtain an initial netlist;
a traversal module configured to traverse the initial netlist to determine a plurality of first memories and a plurality of second memories that can be mapped as BSRAMs;
the second acquisition module is configured to acquire the number and the address size of the read-write ports of each first memory and each second memory;
and the mapping module is configured to map the number, the data width and the address width of the read-write ports of each first memory into the BSRAMs of corresponding types and numbers, or map the number, the data width and the address width of the read-write ports of each second memory into the BSRAMs of corresponding types and numbers.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer apparatus, including:
at least one processor; and
a memory storing a computer program operable on the processor, wherein the processor executes the program to perform any of the steps of the memory conversion method described above.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer-readable storage medium storing a computer program, which when executed by a processor performs the steps of any of the memory conversion methods described above.
The invention has one of the following beneficial technical effects: the scheme provided by the invention can be applied to chip design or FPGA design, when the design comprises a logic-expressed memory, the memory can be replaced by 1 or a plurality of BSRAMs, and the chip area occupied by the memory can be effectively reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a flow chart illustrating a memory translation method according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a mapping process when d0< = d1 and a0< = a1 provided by an embodiment of the present invention;
fig. 3 is a schematic diagram of a mapping process when d0> d1 and a0< = a1, provided by an embodiment of the present invention;
fig. 4 is a schematic diagram of a mapping process when d0< = d1 and a0> a1, provided by an embodiment of the present invention;
FIG. 5 is a block diagram of a memory translation system according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a computer device provided in an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In an embodiment of the present invention, RAM: random Access Memory, random Access Memory; BSRAM: block SRAM, block SRAM; ROM: read only memory; SP: single Port, single Port RAM; SDP, simple Dual Port, pseudo-Dual Port RAM; DP: dual Port, dual Port RAM.
According to an aspect of the present invention, an embodiment of the present invention provides a memory conversion method, as shown in fig. 1, which may include the steps of:
s1, obtaining an initial netlist;
s2, traversing the initial netlist to determine a plurality of first memories and a plurality of second memories which can be mapped into BSRAMs;
s3, acquiring the number and the address size of the read-write ports of each first memory and each second memory;
and S4, mapping the read-write ports of each first memory into BSRAMs of corresponding types and numbers according to the number, the data width and the address width of the read-write ports of each first memory, or mapping the read-write ports of each second memory into BSRAMs of corresponding types and numbers according to the number, the data width and the address width of the read-write ports of each second memory.
The scheme provided by the invention can be applied to chip design or FPGA design, when the design comprises a logic-expressed memory, the memory can be replaced by 1 or a plurality of BSRAMs, and the chip area occupied by the memory can be effectively reduced.
In some embodiments, traversing the initial netlist to determine a plurality of first memories and a plurality of second memories that can be mapped as BSRAMs further comprises:
in response to the attribute constraint of the memory in the initial netlist being BSRAM, determining that the memory is a first memory capable of being mapped as BSRAM;
and in response to the fact that the memory in the initial netlist has no attribute constraint and the data width or the address width is larger than a preset value, determining that the memory is a second memory capable of being mapped into the BSRAM.
In some embodiments, further comprising:
obtaining attribute constraints of other memories which cannot be mapped into the BSRAM in the initial netlist;
mapping the attribute constraint of the other memory to SRAM in response to the attribute constraint;
mapping the other memory to a register in response to the attribute constraint of the other memory being a register.
Specifically, the BSRAM is divided into a read only memory ROM, a single port RAM SP, a pseudo dual port RAM SDP, a dual port RAM DP, and the like. The memory is mapped according to the relation among the number of read-write ports, the address width and the data width in the mapping process. For example, the memory has attribute constraints in the mapping process, when the attribute constraints are registers, the memory is directly split into register representations, when the attribute constraints are SRAM, the memory is mapped into SRAM, and when the attribute constraints are BSRAM or the memory size exceeds a certain size and no attribute constraints exist, the memory is mapped into BSRAM.
In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs according to the number of read/write ports of the first memory, or mapping each second memory to a corresponding type and number of BSRAMs according to the number of read/write ports of the second memory, further includes:
mapping the first memory to a ROM in response to the first memory having only one read port;
mapping the second memory to a ROM in response to the second memory having only one read port.
In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs according to the number of read/write ports of the first memory, or mapping each second memory to a corresponding type and number of BSRAMs according to the number of read/write ports of the second memory, further includes:
mapping a read port and a write port of the first memory into an SP in response to the first memory having the read port and the write port with the same address;
and mapping the second memory to be SP in response to the second memory having a read port and a write port and the read port and the write port having the same address.
In some embodiments, mapping each first memory into a corresponding type and number of BSRAMs according to the number of read/write ports of the first memory, or mapping each second memory into a corresponding type and number of BSRAMs according to the number of read/write ports of the second memory, further comprises:
in response to the first memory having a read port and a write port and the addresses of the read port and the write port being different, mapping the first memory to be an SDP;
and mapping the second memory to be SDP in response to that the second memory has a read port and a write port, and the addresses of the read port and the write port are different.
In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs according to the number of read/write ports of the first memory, or mapping each second memory to a corresponding type and number of BSRAMs according to the number of read/write ports of the second memory, further includes:
mapping a DP in response to the first memory having one read port and two write ports and the read port and one of the write ports having the same address, or the first memory having two read ports and one write port and the write port and one of the read ports having the same address, or the first memory having two read ports and two write ports and the two write ports having the same address as one of the read ports, respectively;
and mapping the DP into the DP in response to that the second memory has one read port and two write ports and the addresses of the read port and one of the write ports are the same, or the second memory has two read ports and one write port and the addresses of the write port and one of the read ports are the same, or the second memory has two read ports and two write ports and the addresses of the two write ports are respectively the same as the addresses of one of the read ports.
Specifically, when the first memory or the second memory has only one read port, the memory is mapped as a ROM. When the first memory or the second memory has a read port and a write port, and the addresses of the read and write ports are the same, mapping the read and write ports to SP. When the first memory or the second memory has a read port and a write port and the addresses of the read and write ports are different, the SDP is mapped to the first memory or the second memory. When the first memory or the second memory has one read port and two write ports, and the address of the read port is the same as the address of one of the write ports, the read port and the write port are mapped to DP. When the first memory or the second memory has two read ports, one write port, and the address of the write port is the same as the address of one of the read ports, it is mapped to a DP. When the first memory or the second memory has two read ports and two write ports, and the addresses of the two write ports are respectively the same as the addresses of the read ports, the two write ports are mapped into DP.
In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs according to the data width and address width thereof, or mapping each second memory to a corresponding type and number of BSRAMs according to the data width and address width thereof, further comprises:
in response to that the address width and the data width of the BSRAM to be mapped are both larger than those of the first memory, directly mapping the first memory to the BSRAM;
and directly mapping the second memory to the BSRAM in response to that the address width and the data width of the BSRAM to be mapped are larger than those of the second memory.
Specifically, it is assumed that the data width of the first memory or the second memory is d0, the address width is a0, the data width of the BSRAM to be mapped is d1, and the address width is a1.
As shown in fig. 2, when d0< = d1 and a0< = a1, that is, both the address width and the data width of the BSRAM to be mapped are greater than those of the first memory or the second memory, the replacement is directly performed using the BSRAM elements.
In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs according to the data width and address width thereof, or mapping each second memory to a corresponding type and number of BSRAMs according to the data width and address width thereof, further comprises:
in response to the fact that the address width of the BSRAM to be mapped is larger than that of the first memory, and the data width is smaller than that of the first memory, mapping the first memory into a plurality of BSRAMs, wherein the sum of the data widths of the BSRAMs is larger than that of the first memory;
and in response to the fact that the address width of the BSRAM to be mapped is larger than that of the second memory and the data width is smaller than that of the second memory, mapping the second memory into a plurality of BSRAMs, wherein the sum of the data widths of the BSRAMs is larger than that of the second memory.
Specifically, similarly, it is assumed that the data width of the first memory or the second memory is d0, the address width is a0, and the data width of the BSRAM to be mapped is d1, and the address width is a1. When d0> d1 and a0< = a1, namely the address width of the BSRAM to be mapped is larger than the address width of the first memory or the second memory, the data width is smaller than the data width of the first memory or the second memory, the mapping is performed by using a plurality of BSRAMs, and the sum of the data widths of the plurality of BSRAMs is larger than the data width of the first memory or the second memory.
For example, as in the case when d0> d1 and d0< =2d1 shown in fig. 3, two BSRAMs may be used for data expansion. Wherein BSRAM0 can output data for d0-1 d, and BSRAM1 can output data for d 1-1.
In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs according to the data width and address width thereof, or mapping each second memory to a corresponding type and number of BSRAMs according to the data width and address width thereof, further comprises:
in response to the address width of the BSRAM to be mapped being smaller than the address width of the first memory and the data width being larger than the data width of the first memory, mapping the first memory into a plurality of BSRAMs, wherein the plurality of BSRAMs are enabled by a number of preset address bits to determine the used BSRAMs, and selecting the output of data by a number of preset address bits;
in response to the address width of the BSRAM to be mapped being smaller than the address width of the second memory and the data width being larger than the data width of the second memory, mapping the second memory into a plurality of BSRAMs, wherein the plurality of BSRAMs are enabled by a number of preset address bits to determine the used BSRAMs, and selecting the output of data by a number of preset address bits.
In some embodiments, the plurality of BSRAMs are enabled by a number of preset address bits to determine the BSRAM used, and the output of the data is selected by a number of preset address bits, further comprising:
utilizing a logic circuit to operate the plurality of preset address bits to determine the used BSRAM;
and selecting the output of the data by utilizing the multi-stage MUX, wherein the preset address bits are respectively used as a conducting signal of each MUX in the multi-stage MUX.
Specifically, similarly, it is assumed that the data width of the first memory or the second memory is d0, the address width is a0, and the data width of the BSRAM to be mapped is d1, and the address width is a1. When d0< = d1 and a0> a1, namely, the address width of the BSRAM to be mapped is smaller than that of the first memory or the second memory, the data width is larger than that of the first memory or the second memory, a plurality of BSRAMs are also used for mapping, and simultaneously, the BSRAMs which are enabled to determine the use can be performed through a plurality of preset address bits, and the output of data is selected through a plurality of preset address bits.
For example, as shown in fig. 4, when a0=3 and a1=2 (a 0= a1+ 1), the number of the plurality of BSRAMs at this time is 2. The address bits of the BSRAM to be mapped are respectively the 0 th bit and the 1 st bit, and the address bits of the first memory or the second memory are respectively the 0 th bit, the 1 st bit and the 2 nd bit, so that the address bits of the first memory or the second memory are one bit more than the address bits of the BSRAM to be mapped, and which BSRAM is enabled can be determined by the value (0 or 1) of the bit address (the 2 nd bit, namely the a1 st bit or the a0-1 st bit). And conducting the MUX through the bit address.
Likewise, when a0=3 and a1=1 (a 0= a1+ 2), the number of the plurality of BSRAMs at this time is 4. The address bits of the BSRAMs to be mapped are respectively the 0 th bit, and the address bits of the first memory or the second memory are respectively the 0 th bit, the 1 st bit and the 2 nd bit, so that the address bits of the first memory or the second memory are two more than the address bits of the BSRAMs to be mapped, and which BSRAM is enabled can be determined by the values (00, 01,10, 11) of the two-bit addresses (the 2 nd bit, the 1 st bit, namely the a0-1 th bit and the a0-2 th bit). And determining a conducting signal for enabling each MUX in two levels (one-out-of-four) according to the values (00, 01,10 and 11) of the two-bit addresses (2 nd bit, 1 st bit, namely a0-1 th bit and a0-2 th bit).
It can be seen that, when the address width of the BSRAM to be mapped is smaller than the address width of the first memory or the second memory, the number of the plurality of BSRAMs is 2 a0-a1 The plurality of preset address bits are (a 0-1 bit, a0-2 bit,.. And a1 bit), respectively.
In some embodiments, mapping each first memory to a corresponding type and number of BSRAMs according to the data width and address width thereof, or mapping each second memory to a corresponding type and number of BSRAMs according to the data width and address width thereof, further comprises:
in response to that the address width of the BSRAM to be mapped is smaller than that of the first memory and the data width is smaller than that of the first memory, mapping the first memory into a plurality of BSRAMs, wherein the plurality of BSRAMs can be enabled through a plurality of preset address bits to determine the used BSRAMs, and selecting the output of data through the plurality of preset address bits, remapping each of the mapped BSRAMs into a plurality of BSRAMs, wherein the sum of the data widths of the plurality of BSRAMs remapped by each BSRAM is larger than that of the first memory;
in response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the second memory, the data width is smaller than the data width of the second memory, the second memory is mapped into a plurality of BSRAMs, the BSRAMs are enabled through a plurality of preset address bits to determine the used BSRAMs, the data are selected through the preset address bits, each BSRAM obtained through mapping is mapped into a plurality of BSRAMs again, and the sum of the data widths of the BSRAMs obtained through remapping of each BSRAM is larger than the data width of the second memory.
Specifically, when the address width of the BSRAM to be mapped is smaller than the address width of the first memory or the second memory, and the data width is smaller than the data width of the first memory or the second memory, the first memory or the second memory may be mapped into a plurality of BSRAMs, and then each of the plurality of BSRAMs may be mapped into a plurality of BSRAMs again. I.e., each of the BSRAMs of fig. 4 is mapped into a plurality of BSRAMs, again according to the rules shown in fig. 3.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a memory conversion system 400, as shown in fig. 5, including:
a first obtaining module 401 configured to obtain an initial netlist;
a traversal module 402 configured to traverse the initial netlist to determine a plurality of first memories and a plurality of second memories that can be mapped as BSRAMs;
a second obtaining module 403, configured to obtain the number and address size of the read/write ports of each first memory and each second memory;
the mapping module 404 is configured to map the number, data width, and address width of the read/write ports of each first memory to the corresponding type and number of BSRAMs, or map the number, data width, and address width of the read/write ports of each second memory to the corresponding type and number of BSRAMs.
In some embodiments, traversal module 402 is further configured to:
in response to the attribute constraint of the memory in the initial netlist being BSRAM, determining that the memory is a first memory capable of being mapped into BSRAM;
and in response to the fact that the memory in the initial netlist has no attribute constraint and the size is larger than a preset value, determining that the memory is a second memory capable of being mapped into BSRAM.
In some embodiments, the system further comprises a third obtaining module configured to:
obtaining attribute constraints of other memories which cannot be mapped into the BSRAM in the initial netlist;
mapping the attribute constraint of the other memory to SRAM in response to the attribute constraint;
mapping the other memory to a register in response to the attribute constraint of the other memory being a register.
In some embodiments, the mapping module 404 is further configured to:
mapping the first memory to a ROM in response to the first memory having only one read port;
mapping the second memory to a ROM in response to the second memory having only one read port.
In some embodiments, the mapping module 404 is further configured to:
mapping a read port and a write port of the first memory into an SP in response to the first memory having the read port and the write port with the same address;
and mapping the second memory to be SP in response to the second memory having a read port and a write port and the read port and the write port having the same address.
In some embodiments, the mapping module 404 is further configured to:
in response to the first memory having a read port and a write port and the addresses of the read port and the write port being different, mapping the first memory to be an SDP;
and mapping the second memory to be SDP in response to that the second memory has a read port and a write port, and the addresses of the read port and the write port are different.
In some embodiments, the mapping module 404 is further configured to:
mapping the first memory into a DP in response to the first memory having one read port and two write ports and the read port and one of the write ports having the same address, or the first memory having two read ports and one write port and the write port and one of the read ports having the same address, or the first memory having two read ports and two write ports and the two write ports having the same address as one of the read ports, respectively;
and mapping the DP into a second memory in response to the second memory having one read port and two write ports and the read port and one of the write ports having the same address, or the second memory having two read ports and one write port and the write port and one of the read ports having the same address, or the second memory having two read ports and two write ports and the two write ports having the same address as one of the read ports, respectively.
In some embodiments, the mapping module 404 is further configured to:
in response to that the address width and the data width of the BSRAM to be mapped are both larger than those of the first memory, directly mapping the first memory into the BSRAM;
and directly mapping the second memory to the BSRAM in response to that the address width and the data width of the BSRAM to be mapped are larger than those of the second memory.
In some embodiments, mapping each first memory or each second memory to a corresponding number of BSRAMs according to the data width and address width thereof, further comprises:
in response to the fact that the address width of the BSRAM to be mapped is larger than that of the first memory, and the data width is smaller than that of the first memory, mapping the first memory into a plurality of BSRAMs, wherein the sum of the data widths of the BSRAMs is larger than that of the first memory;
and mapping the second memory into a plurality of BSRAMs in response to the fact that the address width of the BSRAM to be mapped is larger than that of the second memory and the data width is smaller than that of the second memory, wherein the sum of the data widths of the BSRAMs is larger than that of the second memory.
In some embodiments, the mapping module 404 is further configured to:
in response to the address width of the BSRAM to be mapped being smaller than the address width of the first memory and the data width being larger than the data width of the first memory, mapping the first memory into a plurality of BSRAMs, wherein the plurality of BSRAMs are enabled by a number of preset address bits to determine the used BSRAMs, and selecting the output of data by a number of preset address bits;
in response to the address width of the BSRAM to be mapped being less than the address width of the second memory and the data width being greater than the data width of the second memory, mapping the second memory into a plurality of BSRAMs, wherein the plurality of BSRAMs are enabled by a number of preset address bits to determine the BSRAM to be used, and selecting the output of data by a number of preset address bits.
In some embodiments, the mapping module 404 is further configured to:
utilizing a logic circuit to operate the plurality of preset address bits to determine the used BSRAM;
and selecting the output of the data by utilizing the multi-stage MUX, wherein the preset address bits are respectively used as a conducting signal of each MUX in the multi-stage MUX.
In some embodiments, the mapping module 404 is further configured to:
in response to that the address width of the BSRAM to be mapped is smaller than that of the first memory and the data width is smaller than that of the first memory, mapping the first memory into a plurality of BSRAMs, wherein the plurality of BSRAMs are enabled through a plurality of preset address bits to determine the used BSRAMs, and selecting the output of data through the plurality of preset address bits, remapping each of the mapped BSRAMs into a plurality of BSRAMs, wherein the sum of the data widths of the plurality of BSRAMs remapped by each BSRAM is larger than that of the first memory;
in response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the second storage, the data width is smaller than the data width of the second storage, the second storage is mapped into a plurality of BSRAMs, the BSRAMs are enabled through a plurality of preset address bits to determine the used BSRAM, and the data are selected through the plurality of preset address bits to be output, each BSRAM obtained through mapping is mapped into a plurality of BSRAMs again, wherein the sum of the data widths of the BSRAMs obtained through remapping of each BSRAM is larger than the data width of the second storage.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 6, an embodiment of the present invention further provides a computer apparatus 501, comprising:
at least one processor 520; and
the memory 510, the memory 510 storing a computer program 511 executable on the processor, the processor 520 executing the program to perform the steps of any of the above memory conversion methods.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 7, an embodiment of the present invention further provides a computer-readable storage medium 601, where the computer-readable storage medium 601 stores a computer program 610, and the computer program 610, when executed by a processor, performs the steps of any of the above memory conversion methods.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The foregoing are exemplary embodiments of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the above embodiments of the present invention are merely for description, and do not represent the advantages or disadvantages of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also combinations between technical features in the above embodiments or in different embodiments are possible, and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (15)
1. A memory translation method, comprising the steps of:
obtaining an initial netlist;
traversing the initial netlist to determine a plurality of first memories and a plurality of second memories that can be mapped as BSRAMs;
acquiring the number and the address size of the read-write ports of each first memory and each second memory;
and mapping each first memory into BSRAMs of corresponding types and numbers according to the number, data width and address width of the read-write ports of each first memory, or mapping each second memory into BSRAMs of corresponding types and numbers according to the number, data width and address width of the read-write ports of each second memory.
2. The method of claim 1, wherein traversing the initial netlist to determine a plurality of first memories and a plurality of second memories that can be mapped to BSRAM further comprises:
in response to the attribute constraint of the memory in the initial netlist being BSRAM, determining that the memory is a first memory capable of being mapped into BSRAM;
and in response to the fact that the memory in the initial netlist has no attribute constraint and the data width or the address width is larger than a preset value, determining that the memory is a second memory capable of being mapped into the BSRAM.
3. The method of claim 1, further comprising:
obtaining attribute constraints of other memories which cannot be mapped into the BSRAM in the initial netlist;
mapping the attribute constraint of the other memory to SRAM in response to the attribute constraint;
mapping the other memory to a register in response to the attribute constraint of the other memory being a register.
4. The method of claim 1, wherein mapping each first memory to a corresponding type and number of BSRAMs based on the number of read/write ports of the first memory, or mapping each second memory to a corresponding type and number of BSRAMs based on the number of read/write ports of the second memory, further comprising:
mapping the first memory to a ROM in response to the first memory having only one read port;
mapping the second memory to ROM in response to the second memory having only one read port.
5. The method of claim 1, wherein mapping each first memory to a corresponding type and number of BSRAMs based on the number of read/write ports of the first memory, or mapping each second memory to a corresponding type and number of BSRAMs based on the number of read/write ports of the second memory, further comprising:
mapping a read port and a write port of the first memory into an SP in response to the first memory having the read port and the write port with the same address;
and mapping the second memory to be SP in response to the second memory having a read port and a write port and the read port and the write port having the same address.
6. The method of claim 1, wherein mapping each first memory to a corresponding type and number of BSRAMs based on the number of read/write ports of the first memory, or mapping each second memory to a corresponding type and number of BSRAMs based on the number of read/write ports of the second memory, further comprising:
in response to the first memory having a read port and a write port and the addresses of the read port and the write port being different, mapping the first memory to be an SDP;
and in response to the second memory having a read port and a write port and the addresses of the read port and the write port being different, mapping the second memory to be an SDP.
7. The method of claim 1, wherein mapping each first memory to a corresponding type and number of BSRAMs based on the number of read/write ports of the first memory, or mapping each second memory to a corresponding type and number of BSRAMs based on the number of read/write ports of the second memory, further comprising:
mapping the first memory into a DP in response to the first memory having one read port and two write ports and the read port and one of the write ports having the same address, or the first memory having two read ports and one write port and the write port and one of the read ports having the same address, or the first memory having two read ports and two write ports and the two write ports having the same address as one of the read ports, respectively;
and mapping the DP into a second memory in response to the second memory having one read port and two write ports and the read port and one of the write ports having the same address, or the second memory having two read ports and one write port and the write port and one of the read ports having the same address, or the second memory having two read ports and two write ports and the two write ports having the same address as one of the read ports, respectively.
8. The method of claim 1, wherein each first memory is mapped to a corresponding type and number of BSRAMs based on a data width and an address width of the first memory, or each second memory is mapped to a corresponding type and number of BSRAMs based on a data width and an address width of the second memory, further comprising:
in response to that the address width and the data width of the BSRAM to be mapped are both larger than those of the first memory, directly mapping the first memory into the BSRAM;
and directly mapping the second memory to the BSRAM in response to that the address width and the data width of the BSRAM to be mapped are larger than those of the second memory.
9. The method of claim 1, wherein each first memory is mapped to a corresponding type and number of BSRAMs based on a data width and an address width of the first memory, or each second memory is mapped to a corresponding type and number of BSRAMs based on a data width and an address width of the second memory, further comprising:
in response to the fact that the address width of the BSRAM to be mapped is larger than that of the first memory, and the data width is smaller than that of the first memory, mapping the first memory into a plurality of BSRAMs, wherein the sum of the data widths of the BSRAMs is larger than that of the first memory;
and mapping the second memory into a plurality of BSRAMs in response to the fact that the address width of the BSRAM to be mapped is larger than that of the second memory and the data width is smaller than that of the second memory, wherein the sum of the data widths of the BSRAMs is larger than that of the second memory.
10. The method of claim 1, wherein each of the first memories is mapped to a corresponding type and number of BSRAMs according to its data width and address width, or each of the second memories is mapped to a corresponding type and number of BSRAMs according to its data width and address width, further comprising:
in response to the address width of the BSRAM to be mapped being smaller than the address width of the first memory and the data width being larger than the data width of the first memory, mapping the first memory into a plurality of BSRAMs, wherein the plurality of BSRAMs are enabled by a number of preset address bits to determine the used BSRAMs, and selecting the output of data by a number of preset address bits;
in response to the address width of the BSRAM to be mapped being less than the address width of the second memory and the data width being greater than the data width of the second memory, mapping the second memory into a plurality of BSRAMs, wherein the plurality of BSRAMs are enabled by a number of preset address bits to determine the BSRAM to be used, and selecting the output of data by a number of preset address bits.
11. The method of claim 10, wherein the plurality of BSRAMs are enabled by a plurality of predetermined address bits to determine the BSRAM used and the output of the data is selected by a plurality of predetermined address bits, further comprising:
utilizing a logic circuit to operate the plurality of preset address bits to determine the used BSRAM;
and selecting the output of the data by utilizing the multi-stage MUX, wherein the plurality of preset address bits are respectively used as the conducting signals of each MUX in the multi-stage MUX.
12. The method of claim 1, wherein each first memory is mapped to a corresponding type and number of BSRAMs based on a data width and an address width of the first memory, or each second memory is mapped to a corresponding type and number of BSRAMs based on a data width and an address width of the second memory, further comprising:
in response to that the address width of the BSRAM to be mapped is smaller than that of the first memory and the data width is smaller than that of the first memory, mapping the first memory into a plurality of BSRAMs, wherein the plurality of BSRAMs can be enabled through a plurality of preset address bits to determine the used BSRAMs, and selecting the output of data through the plurality of preset address bits, remapping each of the mapped BSRAMs into a plurality of BSRAMs, wherein the sum of the data widths of the plurality of BSRAMs remapped by each BSRAM is larger than that of the first memory;
in response to the fact that the address width of the BSRAM to be mapped is smaller than the address width of the second storage, the data width is smaller than the data width of the second storage, the second storage is mapped into a plurality of BSRAMs, the BSRAMs are enabled through a plurality of preset address bits to determine the used BSRAM, and the data are selected through the plurality of preset address bits to be output, each BSRAM obtained through mapping is mapped into a plurality of BSRAMs again, wherein the sum of the data widths of the BSRAMs obtained through remapping of each BSRAM is larger than the data width of the second storage.
13. A memory translation system, comprising:
a first obtaining module configured to obtain an initial netlist;
a traversal module configured to traverse the initial netlist to determine a plurality of first memories and a plurality of second memories that can be mapped as BSRAMs;
the second acquisition module is configured to acquire the number and the address size of the read-write ports of each first memory and each second memory;
and the mapping module is configured to map the number, the data width and the address width of the read-write ports of each first memory into the BSRAMs of corresponding types and numbers, or map the number, the data width and the address width of the read-write ports of each second memory into the BSRAMs of corresponding types and numbers.
14. A computer device, comprising:
at least one processor; and
memory storing a computer program operable on the processor, wherein the processor executes the program to perform the steps of the method according to any of claims 1-12.
15. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the method according to any one of claims 1-12.
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