CN114564063A

CN114564063A - Voltage stabilizer and control method thereof

Info

Publication number: CN114564063A
Application number: CN202210246743.1A
Authority: CN
Inventors: 陈啸宸
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-03-14
Filing date: 2022-03-14
Publication date: 2022-05-31
Anticipated expiration: 2042-03-14
Also published as: CN114564063B; WO2023173595A1

Abstract

The embodiment of the disclosure relates to the technical field of semiconductors, and provides a voltage stabilizer and a control method thereof, wherein the voltage stabilizer comprises: a comparison module configured to compare a reference voltage and a feedback voltage and generate an error voltage based on the comparison; an output voltage regulating module coupled to the output end of the comparing module at a first node and configured to adjust the input voltage received by the output voltage regulating module based on the error voltage to provide an output voltage to the output node; a feedback circuit coupled between the output node and a ground voltage, the feedback circuit configured to divide the output voltage to provide a feedback voltage; and the driving voltage regulating module is coupled with the first node and used for regulating the potential at the first node in the starting stage of the operation of the voltage stabilizer. The disclosed embodiments facilitate at least the startup of the acceleration voltage regulator.

Description

Voltage stabilizer and control method thereof

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a voltage stabilizer and a control method thereof.

Background

With the widespread use of electronic technology, higher performance requirements are also placed on electronic systems. The voltage stabilizer is a power supply circuit or power supply equipment capable of automatically adjusting output voltage, and has the function of stabilizing power supply voltage which has large fluctuation and cannot meet the requirements of electrical equipment within a set value range of the power supply voltage, so that various circuits or electrical equipment can normally work under rated working voltage.

However, in order to obtain a stable output voltage in a range of values more quickly to reduce transient voltage drop, a voltage regulator with a faster response speed is required.

Disclosure of Invention

The embodiment of the disclosure provides a voltage stabilizer and a control method thereof, which are at least beneficial to accelerating the starting of the voltage stabilizer.

According to some embodiments of the present disclosure, an aspect of the embodiments of the present disclosure provides a voltage regulator including: a comparison module configured to compare a reference voltage and a feedback voltage and generate an error voltage based on the comparison; an output voltage regulation module coupled to the output of the comparison module at a first node and configured to adjust the input voltage received by the output voltage regulation module based on the error voltage to provide an output voltage to an output node; a feedback circuit coupled between the output node and a ground voltage, the feedback circuit configured to divide the output voltage to provide the feedback voltage; and the driving voltage regulating module is coupled with the first node and used for regulating the potential at the first node in the starting stage of the operation of the voltage stabilizer.

In some embodiments, the drive voltage adjustment module is configured to: reducing a time taken to adjust the input voltage received by the output voltage regulation module.

In some embodiments, the driving voltage adjusting module includes: the starting unit is coupled with the control end of the output voltage regulating module and stops regulating the potential of the first node based on a starting signal so as to start the voltage stabilizer; and the adjusting unit is coupled with the control end of the output voltage adjusting module and adjusts the potential of the first node based on an adjusting signal so as to accelerate the starting of the voltage stabilizer.

In some embodiments, the output voltage regulating module includes a first PMOS transistor, a control terminal of the first PMOS transistor is coupled to the first node, a first terminal of the first PMOS transistor is coupled to an operating power supply, and a second terminal of the first PMOS transistor is coupled to the output node.

In some embodiments, the starting unit includes a second PMOS transistor, and the adjusting unit includes a second NMOS transistor, a control terminal of the second PMOS transistor receives the starting signal, a first terminal of the second PMOS transistor is coupled to the working power supply, a second terminal of the second PMOS transistor is coupled to the first node, a control terminal of the second NMOS transistor receives the adjusting signal, a first terminal of the second NMOS transistor is coupled to ground, and a second terminal of the second NMOS transistor is coupled to the first node.

In some embodiments, the start-up unit includes a second NMOS transistor, and the adjusting unit includes a second PMOS transistor, a control terminal of the second NMOS transistor receives the start-up signal, a first terminal of the second NMOS transistor is coupled to the operating power supply, a second terminal of the second NMOS transistor is coupled to the first node, a control terminal of the second PMOS transistor receives the adjusting signal, a first terminal of the second PMOS transistor is coupled to ground, and a second terminal of the second PMOS transistor is coupled to the first node.

In some embodiments, the output voltage regulating module includes a first NMOS transistor, a control terminal of the first NMOS transistor is coupled to the first node, a first terminal of the first NMOS transistor is coupled to an operating power supply, and a second terminal of the first NMOS transistor is coupled to the output node.

In some embodiments, the start-up unit includes a second PMOS transistor, and the adjusting unit includes a second NMOS transistor, a control terminal of the second PMOS transistor receives the start-up signal, a first terminal of the second PMOS transistor is coupled to ground, a second terminal of the second PMOS transistor is coupled to the first node, a control terminal of the second NMOS transistor receives the adjusting signal, a first terminal of the second NMOS transistor is coupled to the operating power supply, and a second terminal of the second NMOS transistor is coupled to the first node.

In some embodiments, the start-up unit includes a second NMOS transistor, and the adjusting unit includes a second PMOS transistor, a control terminal of the second NMOS transistor receives the start-up signal, a first terminal of the second NMOS transistor is coupled to ground, a second terminal of the second NMOS transistor is coupled to the first node, a control terminal of the second PMOS transistor receives the adjusting signal, a first terminal of the second PMOS transistor is coupled to the working power supply, and a second terminal of the second PMOS transistor is coupled to the first node.

In some embodiments, the voltage regulator further comprises: a signal generation module for generating the adjustment signal based on the start signal; and generating the adjusting signal based on the starting signal, wherein the generating of the adjusting signal comprises performing logical AND operation on a signal obtained by sequentially performing phase inversion and time delay processing on the starting signal and the starting signal to generate the adjusting signal.

In some embodiments, the signal generation module comprises: the input end of the inverting unit receives the starting signal; the input end of the delay unit is coupled with the output end of the inverting unit; and the first input end of the AND gate circuit is coupled with the output end of the delay unit, the second input end of the AND gate circuit receives the starting signal, and the output end of the AND gate circuit outputs the adjusting signal.

In some embodiments, the voltage regulator further comprises: a signal generation module for generating the adjustment signal based on the start signal; generating the adjustment signal based on the start signal includes performing a logical or operation on a signal obtained by sequentially performing phase inversion and time delay on the start signal and the start signal to generate the adjustment signal.

In some embodiments, the signal generation module comprises: the input end of the inverting unit receives the starting signal; the input end of the delay unit is coupled with the output end of the inverting unit; the first input end of the OR gate circuit is coupled with the output end of the delay unit, the second input end of the OR gate circuit receives the starting signal, and the output end of the OR gate circuit outputs the adjusting signal.

In some embodiments, the feedback circuit comprises: a first voltage division module coupled between the output node and the comparison module; the second voltage division module is coupled between the first voltage division module and a ground terminal, and the feedback voltage is a potential at a coupling position of the first voltage division module and the second voltage division module.

In some embodiments, the comparison module comprises: the third PMOS tube, the fourth PMOS tube, the third NMOS tube and the fourth NMOS tube; the control end of the third PMOS tube is coupled with the control end of the fourth PMOS tube, and a third node is arranged between the control ends of the third PMOS tube and the fourth PMOS tube; a first end of the third PMOS transistor and a third end of the fourth PMOS transistor are coupled to a working power supply, a second end of the third PMOS transistor is coupled to a fifth end of the third NMOS transistor, a fourth end of the fourth PMOS transistor is coupled to a seventh end of the fourth NMOS transistor, a fourth node is arranged between the second end and the fifth end, the fourth node is coupled to the first node, a fifth node is arranged between the fourth end and the seventh end, and the fifth node is coupled to the third node; the sixth end of the third NMOS transistor is coupled to the eighth end of the fourth NMOS transistor, the control end of the third NMOS transistor is the first input end of the comparison module, the control end of the fourth NMOS transistor is the second input end of the comparison module, and the fourth node is the output end of the comparison module.

In some embodiments, there is a sixth node between the sixth terminal and the eighth terminal, the voltage regulator further comprising: a control end of the fifth NMOS transistor receives a bias voltage, a first end of the fifth NMOS transistor is coupled to the sixth node, and a second end of the fifth NMOS transistor is coupled to the ground.

According to some embodiments of the present disclosure, in another aspect, there is provided a control method of a voltage regulator, including: providing a voltage regulator according to any one of the preceding claims; and providing a reference voltage and a driving voltage, wherein in a starting stage of the operation of the voltage stabilizer, the driving voltage adjusting module adjusts the potential at the first node based on the driving voltage so as to enable the feedback circuit to generate a feedback voltage, and enable the comparing module to generate an error voltage based on the reference voltage and the feedback voltage, and enable the output voltage adjusting module to generate an output voltage based on the error voltage.

In some embodiments, the output voltage regulating module comprises a first PMOS transistor or a first NMOS transistor; the driving voltage includes an enable signal and a regulation signal.

In some embodiments, the step of providing the driving voltage comprises: providing a start signal; generating the adjustment signal based on the activation signal.

In some embodiments, the control method of the voltage regulator further includes: providing a bias voltage, the comparison module receiving the bias voltage.

The technical scheme provided by the embodiment of the disclosure has at least the following advantages:

set up drive voltage regulation module in the stabiliser for at the start-up stage of stabiliser work, can adjust the electric potential of first node to the required electric potential of start output voltage regulation module through drive voltage regulation module fast, thereby accelerate the start-up of output voltage regulation module, provide output voltage's speed to output node with improving output voltage regulation module, thereby be favorable to accelerating the start-up of stabiliser.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified; in order to more clearly illustrate the embodiments of the present disclosure or technical solutions in the conventional technologies, the drawings required to be used in the embodiments will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 to 4 are schematic diagrams of four circuit structures of a voltage regulator according to an embodiment of the present disclosure;

FIG. 5 is a waveform diagram of an enable signal and a adjust signal provided by an embodiment of the present disclosure;

fig. 6 is a schematic circuit structure diagram of a signal generating module corresponding to fig. 5;

FIG. 7 is a schematic circuit diagram of a signal generating module corresponding to FIG. 6;

fig. 8 and 9 are schematic diagrams of another two circuit structures of a voltage regulator according to an embodiment of the present disclosure;

FIG. 10 is another waveform diagram of an enable signal and a adjust signal provided by an embodiment of the present disclosure;

fig. 11 is a schematic circuit diagram of a signal generating module corresponding to fig. 10;

FIG. 12 is a schematic circuit diagram of a signal generating module corresponding to FIG. 11;

fig. 13 is a schematic circuit diagram of another circuit structure of a voltage regulator according to an embodiment of the present disclosure.

Detailed Description

As is known in the art, the response speed of the voltage regulator needs to be improved.

The disclosed implementation provides a voltage stabilizer and a control method thereof, wherein a driving voltage adjusting module is arranged in the voltage stabilizer, so that in the starting stage of the working of the voltage stabilizer, the driving voltage adjusting module can be used for rapidly adjusting the potential at a first node to the potential required by the starting of an output voltage adjusting module, so that the starting of the output voltage adjusting module is accelerated, the speed of the output voltage adjusting module for providing the output voltage to an output node is increased, and the starting of the voltage stabilizer is accelerated.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the embodiments of the disclosure, numerous technical details are set forth in order to provide a better understanding of the embodiments of the disclosure. However, the claimed embodiments of the present disclosure may be practiced without these specific details or with various changes and modifications based on the following embodiments.

The present disclosure provides a voltage regulator, which will be described in detail below with reference to the accompanying drawings. Fig. 1 to 4 are schematic diagrams of four circuit structures of a voltage regulator according to an embodiment of the present disclosure; FIG. 5 is a waveform diagram of an enable signal and a adjust signal provided by an embodiment of the present disclosure; fig. 6 is a schematic circuit structure diagram of a signal generating module corresponding to fig. 5; FIG. 7 is a schematic circuit diagram of a signal generating module corresponding to FIG. 6; fig. 8 and 9 are schematic diagrams of another two circuit structures of a voltage regulator according to an embodiment of the present disclosure; FIG. 10 is another waveform diagram of an enable signal and a adjust signal provided by an embodiment of the present disclosure; fig. 11 is a schematic circuit diagram of a signal generating module corresponding to fig. 10;

FIG. 12 is a schematic circuit diagram of a signal generating module corresponding to FIG. 11; fig. 13 is a schematic circuit diagram of another circuit structure of a voltage regulator according to an embodiment of the present disclosure.

Referring to fig. 1, the voltage regulator includes: a comparison module 100 configured to compare the reference voltage 10a and the feedback voltage 10b and generate an error voltage 10c based on the comparison; an output voltage regulation module 101, coupled to the output of the comparison module 100 at a first node 102, configured to adjust the input voltage received by the output voltage regulation module 101 based on the error voltage 10c to provide an output voltage 10d to an output node 103; a feedback circuit 104 coupled between the output node 103 and a ground voltage, the feedback circuit 104 being configured to divide the output voltage 10d to provide a feedback voltage 10 b; and a driving voltage adjusting module 105, coupled to the first node 102, for adjusting a potential at the first node 102 during a start-up phase of the operation of the voltage regulator.

At the starting stage of the operation of the voltage stabilizer, the driving voltage adjusting module 105 adjusts the potential at the first node 102, so that the potential at the first node 102 quickly reaches the potential required by the starting output voltage adjusting module 101, the output voltage adjusting module 101 is started quickly, the speed of the output voltage adjusting module 101 for providing the output voltage 10d to the output node 103 is increased, and the starting of the voltage stabilizer is accelerated. Further, after the output voltage regulating module 101 provides the output voltage 10d to the output node 103 for the first time, the feedback circuit 104 divides the output voltage 10d to provide the feedback voltage 10b to the comparison module 100, the comparison module 100 compares the reference voltage 10a and the feedback voltage 10b and generates the error voltage 10c, and the output voltage regulating module 101 adjusts the input voltage received by the output voltage regulating module 101 based on the error voltage 10c to provide the output voltage 10d to the output node 103.

In some embodiments, the drive voltage adjustment module 105 is configured to: reducing the time taken to adjust the input voltage received by the output voltage regulation module 101. Wherein, the input voltage that output voltage adjusting module 101 received is the electric potential of first node 102 department promptly, output voltage adjusting module 101 starts or closes based on the electric potential of first node 102 department, drive voltage adjusting module 105 is favorable to reducing the consuming time of adjusting the input voltage that output voltage adjusting module 101 received, at the start-up stage of stabiliser work promptly, drive voltage adjusting module 105 can be quick with the electric potential of first node 102 department adjust to the required electric potential of start-up output voltage adjusting module 101 to accelerate the start-up of output voltage adjusting module 101, thereby further accelerate the start-up of stabiliser.

Embodiments of the present disclosure will be described in more detail below with reference to fig. 2 to 13.

In some embodiments, the driving voltage adjustment module 105 includes: a start unit 115 coupled to the control terminal of the output voltage regulating module 101, wherein the start unit 115 stops regulating the potential of the first node 102 based on the start signal 11a to start the voltage regulator; and an adjusting unit 125 coupled to the control terminal of the output voltage adjusting module 101, wherein the adjusting unit 125 adjusts the potential of the first node 102 based on the adjusting signal 11b to accelerate the start-up of the voltage regulator.

It should be noted that, when the voltage regulator is in the non-operating stage, the starting unit 115 may adjust the potential at the first node 102 based on the starting signal 11a, so that the output voltage adjusting module 101 is in the off state based on the potential at the first node 102 at this time, that is, the starting unit 115 controls the output voltage adjusting module 101 not to provide the output voltage 10d to the output node 103, and the comparing module 100 is also in the non-operating state, so that the whole voltage regulator is in the non-operating state.

The specific configurations of the output voltage regulating module 101, the starting unit 115, and the regulating unit 125 are described in detail by four embodiments below.

In some embodiments, referring to fig. 3, the output voltage regulating module 101 includes a first PMOS transistor 111, a control terminal of the first PMOS transistor 111 is coupled to the first node 102, a first terminal of the first PMOS transistor 111 is coupled to the operating power VDD, and a second terminal of the first PMOS transistor 111 is coupled to the output node 103.

The start unit 115 includes a second PMOS transistor 135, and the adjusting unit 125 includes a second NMOS transistor 145, a control terminal of the second PMOS transistor 135 receives the start signal 11a, a first terminal of the second PMOS transistor 135 is coupled to the working power VDD, a second terminal of the second PMOS transistor 135 is coupled to the first node 102, a control terminal of the second NMOS transistor 145 receives the adjusting signal 11b, a first terminal of the second NMOS transistor 145 is coupled to ground, and a second terminal of the second NMOS transistor 145 is coupled to the first node 102.

Thus, in the non-operation stage of the voltage regulator, the second PMOS transistor 135 may be in a conducting state based on the start signal 11a, and the second NMOS transistor 145 may be in a blocking state based on the adjusting signal 11b, and then the first node 102 is coupled to the operating power VDD, that is, the potential at the first node 102 may be pulled up to a higher value by the second PMOS transistor 135 that is in the conducting state at this time, so that the first PMOS transistor 111 that receives the voltage at the first node 102 is in the blocking state, that is, the output voltage adjusting module 101 is in the blocking state, and the output voltage 10d is not provided to the output node 103.

Then, at the start-up stage of the operation of the voltage regulator, the second PMOS transistor 135 may be in an off state based on the start signal 11a, and the second NMOS transistor 145 may be in an on state based on the adjustment signal 11b, so that the first node 102 with a higher potential is coupled to the ground, that is, the potential at the first node 102 may be quickly pulled down to the potential required to start the first PMOS transistor 111 through the second NMOS transistor 145 in the on state at this time, thereby achieving the purpose of adjusting the potential at the first node 102 by the driving voltage adjustment module 105, so that the potential at the first node 102 quickly reaches the potential required to start the output voltage adjustment module 101, so as to quickly turn on the first PMOS transistor 111, thereby increasing the speed at which the output voltage adjustment module 101 provides the output voltage 10d to the output node 103, and facilitating the acceleration of the start-up of the voltage regulator.

Then, after the output voltage regulating module 101 provides the output voltage 10d to the output node 103 for the first time, the second PMOS transistor 135 may be in an off state based on the enable signal 11a, the second NMOS transistor 145 may also be in an off state based on the regulating signal 11b, at this time, the feedback circuit 104 divides the output voltage 10d to provide the feedback voltage 10b to the comparison module 100, the comparison module 100 compares the reference voltage 10a and the feedback voltage 10b and generates an error voltage 10c, and the output voltage regulating module 101 adjusts the input voltage received by the output voltage regulating module 101 based on the error voltage 10c, that is, adjusts the potential at the first node 102 by using the comparison module 100, so that the potential at the first node 102 is within a stable value range, so that the first PMOS transistor 111 is in an on state, and provides the stable output voltage 10d to the output node 103.

In still other embodiments, the output voltage regulating module 101 includes a first NMOS transistor 121, a control terminal of the first NMOS transistor 121 is coupled to the first node 102, a first terminal of the first NMOS transistor 121 is coupled to the operating power VDD, and a second terminal of the first NMOS transistor 121 is coupled to the output node 103.

The start unit 115 includes a second PMOS transistor 135, and the adjusting unit 125 includes a second NMOS transistor 145, a control terminal of the second PMOS transistor receives the start signal 11a, a first terminal of the second PMOS transistor 135 is coupled to ground, a second terminal of the second PMOS transistor 135 is coupled to the first node 102, a control terminal of the second NMOS transistor 145 receives the adjusting signal 11b, a first terminal of the second NMOS transistor 145 is coupled to the working power VDD, and a second terminal of the second NMOS transistor 145 is coupled to the first node 102.

Thus, in the non-operation stage of the voltage regulator, the second PMOS transistor 135 may be in a conducting state based on the start signal 11a, and the second NMOS transistor 145 may be in a blocking state based on the adjusting signal 11b, and then the first node 102 is equivalently coupled to the ground, that is, the potential at the first node 102 may be pulled down to a lower value by the second PMOS transistor 135 that is in the conducting state at this time, so that the first NMOS transistor 121 that receives the voltage at the first node 102 is in the blocking state, that is, the output voltage adjusting module 101 is in the blocking state, and the output voltage 10d is not provided to the output node 103.

Then, at the start-up stage of the operation of the voltage regulator, the second PMOS transistor 135 may be in an off state based on the start signal 11a, and the second NMOS transistor 145 may be in an on state based on the adjustment signal 11b, so that the first node 102 with a lower potential is coupled to the working power VDD, that is, the potential at the first node 102 may be quickly pulled up to the potential required to start the first NMOS transistor 121 through the second NMOS transistor 145 in the on state at this time, thereby achieving the purpose of adjusting the potential at the first node 102 by driving the voltage adjustment module 105, so that the potential at the first node 102 quickly reaches the potential required to start the output voltage adjustment module 101, so as to quickly turn on the first NMOS transistor 121, thereby increasing the speed at which the output voltage adjustment module 101 provides the output voltage 10d to the output node 103, and facilitating acceleration of the start-up of the voltage regulator.

Then, after the output voltage regulating module 101 provides the output voltage 10d to the output node 103 for the first time, the second PMOS transistor 135 may be in an off state based on the enable signal 11a, the second NMOS transistor 145 may be also in an off state based on the regulating signal 11b, at this time, the feedback circuit 104 divides the output voltage 10d to provide the feedback voltage 10b to the comparison module 100, the comparison module 100 compares the reference voltage 10a and the feedback voltage 10b and generates an error voltage 10c, and the output voltage regulating module 101 adjusts the input voltage received by the output voltage regulating module 101 based on the error voltage 10c, that is, adjusts the potential at the first node 102 by using the comparison module 100, so that the potential at the first node 102 is within a stable value range, so that the first NMOS transistor 121 is in an on state, and provides the stable output voltage 10d to the output node 103.

In both embodiments, the waveforms of the start signal 11a and the adjustment signal 11b can be as shown in fig. 5. In the first stage I, the potentials represented by the start signal 11a and the adjustment signal 11b are both at a lower value, the second PMOS transistor 135 may be in a conducting state based on the start signal 11a, and the second NMOS transistor 145 may be in a blocking state based on the adjustment signal 11 b; in the second stage II, the potentials represented by the start signal 11a and the adjustment signal 11b are both at a higher value, the second PMOS transistor 135 may be in an off state based on the start signal 11a, and the second NMOS transistor 145 may be in an on state based on the adjustment signal 11 b; in the third phase III, the potential represented by the start signal 11a is at a higher value, and the potential represented by the adjustment signal 11b is at a lower value, then the second PMOS transistor 135 may be in the off state based on the start signal 11a, and the second NMOS transistor 145 may also be in the off state based on the adjustment signal 11 b.

It should be noted that the potential at a lower value and the potential at a higher value are distinguished from the magnitudes of the actuation signal 11a and the adjustment signal 11b presented in the first phase I, the second phase II and the third phase III, for example, if the value of the potential characterized by the actuation signal 11a in the first phase I is smaller than the value of the potential characterized by the second phase II, the potential characterized by the actuation signal 11a in the first phase I can be considered to be at a lower value, and the potential characterized by the actuation signal 11a in the second phase II is considered to be at a higher value.

In the above two embodiments, referring to fig. 6, the voltage regulator may further include: a signal generation module 106 for generating an adjustment signal 11b based on the start signal 11 a; the generation of the adjustment signal 11b based on the start signal 11a includes performing a logical and operation on a signal obtained by sequentially performing an inversion and a delay on the start signal 11a and the start signal 11a to generate the adjustment signal 11 b.

In some embodiments, with continued reference to fig. 6, the signal generation module 106 may include: an inverting unit 116, an input terminal of the inverting unit 116 receiving the start signal 11 a; a delay unit 126, an input terminal of the delay unit 126 being coupled to an output terminal of the inverting unit 116; and an and circuit 136, a first input terminal of the and circuit 136 being coupled to the output terminal of the delay unit 126, a second input terminal of the and circuit 136 receiving the enable signal 11a, and an output terminal of the and circuit 136 outputting the adjustment signal 11 b.

In some examples, referring to fig. 7, the and circuit 136 may include a nand gate 146 and a not gate 156 connected in series, and it should be noted that fig. 7 only illustrates that the and circuit 136 includes the nand gate 146 and the not gate 156 connected in series, in practical applications, the and circuit 136 may be formed by a single and gate, or may be formed by a combination of other logic gate circuits, and it is only necessary that the and circuit 136 can perform a logical and operation on the two received signals.

For convenience of description, when the potential represented by the start signal 11a or the adjustment signal 11b is low, it means that the potential represented by the start signal 11a or the adjustment signal 11b in the circuit is 0; when the value of the potential represented by the start signal 11a or the adjustment signal 11b is high, it means that the potential represented by the start signal 11a or the adjustment signal 11b in the circuit is 1.

With combined reference to fig. 5 to 7, in the first phase I, the enable signal 11a is represented as 0, the signal received at the first input terminal of the and circuit 136 is represented as 1, the enable signal 11a received at the second input terminal of the and circuit 136 is represented as 0, and the adjustment signal 11b output at the output terminal of the and circuit 136 is represented as 0; in the second phase II, the enable signal 11a is represented as 1, and due to the delay effect of the delay unit 126 on the received signal output by the inverting unit 116, in the second phase II, the signal received at the first input terminal of the and circuit 136 still represents as 1, the enable signal 11a received at the second input terminal of the and circuit 136 represents as 1, and the adjustment signal 11b output by the output terminal of the and circuit 136 represents as 1; in the third phase III, the enable signal 11a is represented by 1, the first input terminal of the and circuit 136 has received the change of the signal received by the first input terminal of the and circuit 136 due to the change of the enable signal 11a in the second phase II, the signal received by the first input terminal of the and circuit 136 is represented by 0, the enable signal 11a received by the second input terminal of the and circuit 136 is represented by 1, and the adjustment signal 11b output by the output terminal of the and circuit 136 is represented by 0.

In still other embodiments, referring to fig. 8, the output voltage regulating module 101 includes a first PMOS transistor 111, a control terminal of the first PMOS transistor 111 is coupled to the first node 102, a first terminal of the first PMOS transistor 111 is coupled to the operating power VDD, and a second terminal of the first PMOS transistor 111 is coupled to the output node 103.

The start unit 115 includes a second NMOS 145, and the adjusting unit 125 includes a second PMOS 135, a control terminal of the second NMOS 145 receives the start signal 11a, a first terminal of the second NMOS 145 is coupled to the working power VDD, a second terminal of the second NMOS 145 is coupled to the first node 102, a control terminal of the second PMOS 135 receives the adjusting signal 11b, a first terminal of the second PMOS 135 is coupled to ground, and a second terminal of the second PMOS 135 is coupled to the first node 102.

Thus, in the non-operation stage of the voltage regulator, the second NMOS transistor 145 may be in the on state based on the start signal 11a, and the second PMOS transistor 135 may be in the off state based on the adjustment signal 11b, and then the first node 102 is coupled to the operating power VDD, that is, the potential at the first node 102 may be pulled up to a higher value by the second NMOS transistor 145 in the on state, so that the first PMOS transistor 111 receiving the voltage at the first node 102 is in the off state, that is, the output voltage adjusting module 101 is in the off state, and the output voltage 10d is not provided to the output node 103.

Then, at the start-up stage of the operation of the voltage regulator, the second NMOS transistor 145 may be in an off state based on the start signal 11a, and the second PMOS transistor 135 may be in an on state based on the adjustment signal 11b, so that the first node 102 with a higher potential is coupled to the ground, that is, the potential at the first node 102 may be quickly pulled down to the potential required to start the first PMOS transistor 111 through the second PMOS transistor 135 in the on state at this time, thereby achieving the purpose of adjusting the potential at the first node 102 by the driving voltage adjustment module 105, so that the potential at the first node 102 quickly reaches the potential required to start the output voltage adjustment module 101, so as to quickly turn on the first PMOS transistor 111, thereby increasing the speed at which the output voltage adjustment module 101 provides the output voltage 10d to the output node 103, and facilitating the acceleration of the start-up of the voltage regulator.

Then, after the output voltage regulating module 101 provides the output voltage 10d to the output node 103 for the first time, the second NMOS transistor 145 may be in an off state based on the enable signal 11a, the second PMOS transistor 135 may be in an off state based on the regulating signal 11b, at this time, the feedback circuit 104 divides the output voltage 10d to provide the feedback voltage 10b to the comparing module 100, the comparing module 100 compares the reference voltage 10a and the feedback voltage 10b and generates an error voltage 10c, and the output voltage regulating module 101 adjusts the input voltage received by the output voltage regulating module 101 based on the error voltage 10c, that is, adjusts the potential at the first node 102 by using the comparing module 100, so that the potential at the first node 102 is within a stable value range, so that the first PMOS transistor 111 is in an on state, and provides the stable output voltage 10d to the output node 103.

In still other embodiments, referring to fig. 9, the output voltage regulating module 101 includes a first NMOS transistor 121, a control terminal of the first NMOS transistor 121 is coupled to the first node 102, a first terminal of the first NMOS transistor 121 is coupled to the operating power VDD, and a second terminal of the first NMOS transistor 121 is coupled to the output node 103.

The starting unit 115 includes a second NMOS transistor 145, the adjusting unit 125 includes a second PMOS transistor 135, a control terminal of the second NMOS transistor 145 receives the starting signal 11a, a first terminal of the second NMOS transistor 145 is coupled to ground, a second terminal of the second NMOS transistor 145 is coupled to the first node 102, a control terminal of the second PMOS transistor 135 receives the adjusting signal 11b, a first terminal of the second PMOS transistor 135 is coupled to the working power VDD, and a second terminal of the second PMOS transistor 135 is coupled to the first node 102.

Thus, in the non-operation stage of the voltage regulator, the second NMOS transistor 145 may be in the on state based on the start signal 11a, and the second PMOS transistor 135 may be in the off state based on the adjustment signal 11b, and then the first node 102 is equivalently coupled to the ground, that is, the potential at the first node 102 may be pulled down to a lower value by the second NMOS transistor 145 in the on state at this time, so that the first NMOS transistor 121 receiving the voltage at the first node 102 is in the off state, that is, the output voltage adjustment module 101 is in the off state, and the output voltage 10d is not provided to the output node 103.

Then, at a start-up stage of the operation of the voltage regulator, the second NMOS transistor 145 may be in an off state based on the start signal 11a, and the second PMOS transistor 135 may be in an on state based on the adjustment signal 11b, so that the first node 102 with a lower potential is coupled to the working power VDD, that is, the potential at the first node 102 may be quickly pulled up to a potential required to start the first NMOS transistor 121 by the second PMOS transistor 135 that is in the on state at this time, thereby implementing adjustment of the potential at the first node 102 by the driving voltage adjustment module 105, so that the potential at the first node 102 quickly reaches a potential required to start the output voltage adjustment module 101, so as to quickly turn on the first NMOS transistor 121, thereby increasing a speed at which the output voltage adjustment module 101 provides the output voltage 10d to the output node 103, and facilitating acceleration of start-up of the voltage regulator.

Then, after the output voltage regulating module 101 provides the output voltage 10d to the output node 103 for the first time, the second NMOS transistor 145 may be in an off state based on the enable signal 11a, the second PMOS transistor 135 may be in an off state based on the regulating signal 11b, at this time, the feedback circuit 104 divides the output voltage 10d to provide the feedback voltage 10b to the comparison module 100, the comparison module 100 compares the reference voltage 10a and the feedback voltage 10b and generates an error voltage 10c, and the output voltage regulating module 101 adjusts the input voltage received by the output voltage regulating module 101 based on the error voltage 10c, that is, adjusts the potential at the first node 102 by using the comparison module 100, so that the potential at the first node 102 is within a stable value range, so that the first NMOS transistor 121 is in an on state, and provides the stable output voltage 10d to the output node 103.

In the above two embodiments, the waveform diagrams of the start signal 11a and the adjustment signal 11b can be as shown in fig. 10. In the first stage I, the potentials represented by the start signal 11a and the adjustment signal 11b are both at a higher value, and then the second NMOS transistor 145 may be in a conducting state based on the start signal 11a, and the second PMOS transistor 135 may be in a blocking state based on the adjustment signal 11 b; in the second stage II, the potentials represented by the start signal 11a and the adjustment signal 11b are both at a lower value, the second NMOS transistor 145 may be in an off state based on the start signal 11a, and the second PMOS transistor 135 may be in an on state based on the adjustment signal 11 b; in the third phase III, the potential represented by the start signal 11a is at a lower value, and the potential represented by the adjustment signal 11b is at a higher value, so that the second NMOS transistor 145 may be in an off state based on the start signal 11a, and the second PMOS transistor 135 may also be in an off state based on the adjustment signal 11 b.

It should be noted that the potential at a lower value and the potential at a higher value are distinguished from the magnitudes of the actuation signal 11a and the adjustment signal 11b presented in the first phase I, the second phase II and the third phase III, for example, if the value of the potential characterized by the actuation signal 11a in the first phase I is greater than the value of the potential characterized by the second phase II, the potential characterized by the actuation signal 11a in the first phase I can be considered as being at a higher value, and the potential characterized by the actuation signal 11a in the second phase II is considered as being at a lower value.

In the above two embodiments, referring to fig. 11, the voltage regulator may further include: a signal generation module 106 for generating an adjustment signal 11b based on the start signal 11 a; the generation of the adjustment signal 11b based on the start signal 11a includes performing a logical or operation on a signal obtained by sequentially performing an inversion and a delay on the start signal 11a and the start signal 11a to generate the adjustment signal 11 b.

In some embodiments, with continued reference to fig. 11, the signal generation module 106 may include: an inverting unit 116, an input terminal of the inverting unit 116 receiving the start signal 11 a; a delay unit 126, an input terminal of the delay unit 126 being coupled to an output terminal of the inverting unit 116; the or gate 166, a first input of the or gate 166 is coupled to the output of the delay unit 126, a second input of the or gate 166 receives the enable signal 11a, and an output of the or gate 166 outputs the adjustment signal 11 b.

In some examples, referring to fig. 12, the or gate 166 may include the nor gate 176 and the not gate 156 connected in series, it should be noted that fig. 12 only illustrates that the or gate 166 includes the nor gate 176 and the not gate 156 connected in series, in practical applications, the or gate 166 may be formed by a single or gate, or may be formed by a combination of other logic gates, and it is only necessary that the or gate 166 performs a logical or operation on two received signals.

For convenience of description, when the potential represented by the start signal 11a or the adjustment signal 11b is low, it means that the potential represented by the start signal 11a or the adjustment signal 11b in the circuit is 0; when the value of the potential represented by the start signal 11a or the adjustment signal 11b is higher, it means that the potential represented by the start signal 11a or the adjustment signal 11b in the circuit is 1.

With combined reference to fig. 10 to 12, in the first phase I, the enable signal 11a is represented by 1, the signal received at the first input terminal of the and circuit 136 is represented by 0, the enable signal 11a received at the second input terminal of the and circuit 136 is represented by 1, and the adjustment signal 11b output at the output terminal of the and circuit 136 is represented by 1; in the second stage II, the enable signal 11a is represented as 0, and due to the delay effect of the delay unit 126 on the received signal output by the inverting unit 116, in the second stage II, the signal received by the first input terminal of the and circuit 136 is still represented as 0, the enable signal 11a received by the second input terminal of the and circuit 136 is represented as 0, and the adjustment signal 11b output by the output terminal of the and circuit 136 is represented as 0; in the third phase III, the enable signal 11a is represented by 0, the first input terminal of the and circuit 136 has received the change of the signal received at the first input terminal of the and circuit 136 due to the change of the enable signal 11a in the second phase II, the signal received at the first input terminal of the and circuit 136 is represented by 1, the enable signal 11a received at the second input terminal of the and circuit 136 is represented by 0, and the adjustment signal 11b output at the output terminal of the and circuit 136 is represented by 1.

In the above four embodiments, referring to fig. 7 and 12, the inverting unit 116 may include: a first switching unit 186, wherein the first switching unit 186 is coupled between the operating power supply VDD and the input terminal of the delay unit 126, and a second node 107 is provided between the first switching unit 186 and the input terminal of the delay unit 126; a second switching unit 196 coupled between ground and the second node 107; the control terminal of the first switch unit 186 and the control terminal of the second switch unit 196 both receive the start signal 11 a. In some examples, the first switching unit 186 may be one of a PMOS transistor and an NMOS transistor, and the second switching unit 196 may be the other of a PMOS transistor and an NMOS transistor, for example, referring to fig. 7 and 12, the first switching unit 186 may be a PMOS transistor, and the second switching unit 196 may be an NMOS transistor. In other examples, the first switch unit may be an NMOS transistor, and the second switch unit may be a PMOS transistor. In addition, in practical applications, the first switch unit 186 and the second switch unit 196 may be other switch devices that can be turned on or off based on the start signal 11a, and only needs to be satisfied that, for the start signal 11a at the same time, one of the first switch unit 186 and the second switch unit 196 is turned on based on the start signal 11a at the time, and the other of the first switch unit 186 and the second switch unit 196 is turned off based on the start signal 11a at the time.

In the above four embodiments, referring to fig. 7 and 12, the delay unit 126 may include: an even number of inverters 118 connected in series. In fig. 7 and fig. 12, only the delay unit 126 includes two inverters 118 connected in series as an example, and in practical applications, it is only necessary that the number of the inverters 118 is even. Referring to fig. 5 and 10, an even number of inverters 118 connected in series are used to delay the signal received by the delay unit 126 from the output terminal of the inverting unit 116. In this way, it is advantageous that in the second phase II, the value of the potential represented by the enable signal 11a has changed, but the value of the potential represented by the signal received by the delay unit 126 from the output terminal of the inverting unit 116 has not yet changed, so that the values of the potentials represented by the adjustment signal 11b and the enable signal 11a in the second phase II are at the same level, that is, the potentials represented by the adjustment signal 11b and the enable signal 11a in the circuit both represent 1 or 0; then, in the third phase II, the value of the potential represented by the signal received by the delay unit 126 from the output terminal of the inverting unit 116 is also changed, so that the values of the potentials represented by the adjustment signal 11b and the start signal 11a in the third phase II are at different levels, that is, the potential represented by one of the adjustment signal 11b and the start signal 11a in the circuit is represented by 1, and the potential represented by the other of the adjustment signal 11b and the start signal 11a in the circuit is represented by 0.

In some embodiments, with continued reference to fig. 7 and 12, the delay unit 126 may further include, on the basis of an even number of inverters 118 connected in series: the charge/discharge unit 108 is coupled between the second node 107 and ground. Among other things, the charging and discharging unit 108 is advantageous to enhance the delay effect of the delay unit 126 on the signal received from the output terminal of the inverting unit 116.

In some embodiments, referring to fig. 3, 4, 8, and 9, the feedback circuit 104 may include: a first voltage division module 114 coupled between the output node 103 and the comparison module 100; the second voltage divider module 124 is coupled between the first voltage divider module 114 and ground, and the feedback voltage 10b is the voltage at the coupling of the first voltage divider module 114 and the second voltage divider module 124. In this way, when the output voltage 10d meeting the numerical requirement is output through the output voltage adjusting module 101, the first voltage dividing module 114 and the second voltage dividing module 124 are used to control the magnitude of the feedback voltage 10b provided to the comparing module 100, so that the magnitude of the feedback voltage 10b is consistent with the magnitude of the reference voltage 10a, that is, the difference between the feedback voltage 10b and the reference voltage 10a is small or 0, so that the comparing module 100 can output the error voltage 10c with a stable numerical value based on the reference voltage 10a and the feedback voltage 10b, and further, the output voltage adjusting module 101 is used to output the output voltage 10d with a stable numerical value based on the error voltage 10 c.

In some embodiments, referring to fig. 13, the comparison module 100 includes: a third PMOS transistor 110, a fourth PMOS transistor 120, a third NMOS transistor 130, and a fourth NMOS transistor 140; a control end of the third PMOS transistor 110 is coupled to a control end of the fourth PMOS transistor 120, and a third node 109 is disposed between the control end of the third PMOS transistor 110 and the control end of the fourth PMOS transistor 120; a first end of the third PMOS transistor 110 and a third end of the fourth PMOS transistor 120 are coupled to the working power VDD, a second end of the third PMOS transistor 110 is coupled to a fifth end of the third NMOS transistor 130, a fourth end of the fourth PMOS transistor 120 is coupled to a seventh end of the fourth NMOS transistor 140, a fourth node 119 is provided between the second end and the fifth end, the fourth node 119 is coupled to the first node 102, a fifth node 129 is provided between the fourth end and the seventh end, and the fifth node 129 is coupled to the third node 109; the sixth terminal of the third NMOS transistor 130 is coupled to the eighth terminal of the fourth NMOS transistor 140, the control terminal of the third NMOS transistor 130 is a first input terminal of the comparison module 100, the control terminal of the fourth NMOS transistor 140 is a second input terminal of the comparison module 100, and the fourth node 119 is an output terminal of the comparison module.

In some embodiments, the control terminal of the third NMOS transistor 130 receives the reference voltage 10a, and the control terminal of the fourth NMOS transistor 140 receives the feedback voltage 10 b. The comparison module 100 generates the error voltage 10c based on the reference voltage 10a and the feedback voltage 10b, which will be described in detail below.

When the comparing module 100 is in the operating state, the third PMOS transistor 110, the fourth PMOS transistor 120, the third NMOS transistor 130, and the fourth NMOS transistor 140 are all in the conducting state.

If the reference voltage 10a is greater than the feedback voltage 10b, the conduction degree of the third NMOS transistor 130 is greater than the conduction degree of the fourth NMOS transistor 140, i.e., the voltage drop generated by the third NMOS transistor 130 is smaller than the voltage drop generated by the fourth NMOS transistor 140, so that the potential at the fourth node 119 is lower than the potential at the fifth node 129. Since the potential at the fifth node 129 is the potential at the control terminals of the third PMOS transistor 110 and the fourth PMOS transistor 120, if the potential at the fifth node 129 is increased, the conduction degree of the third PMOS transistor 110 and the fourth PMOS transistor 120 is decreased, that is, the voltage drop generated by the third PMOS transistor 110 is increased, the potential at the fourth node 119 is decreased, that is, the error voltage 10c output by the comparison module 100 is decreased, the potential at the first node 102 is decreased, the conduction degree of the first PMOS transistor 111 is increased, that is, the voltage drop generated by the first PMOS transistor 111 is decreased, which is beneficial to increasing the output voltage 10d provided by the output voltage adjustment module 101 to the output node 103, so as to increase the feedback voltage 10b provided by the feedback circuit 104 by dividing the voltage based on the output voltage 10d, so as to decrease the difference between the reference voltage 10a and the feedback voltage 10 b.

If the reference voltage 10a is smaller than the feedback voltage 10b, the conduction degree of the third NMOS transistor 130 is smaller than the conduction degree of the fourth NMOS transistor 140, i.e. the voltage drop generated by the third NMOS transistor 130 is larger than the voltage drop generated by the fourth NMOS transistor 140, so that the potential at the fourth node 119 is higher than the potential at the fifth node 129. Since the potential at the fifth node 129 is the potential at the control terminals of the third PMOS transistor 110 and the fourth PMOS transistor 120, if the potential at the fifth node 129 is lowered, the conduction degree of the third PMOS transistor 110 and the fourth PMOS transistor 120 is increased, that is, the voltage drop generated by the third PMOS transistor 110 is reduced, so that the potential at the fourth node 119 is increased, that is, the error voltage 10c output by the comparison module 100 is increased, so that the potential at the first node 102 is increased, so that the conduction degree of the first PMOS transistor 111 is reduced, that is, the voltage drop generated by the first PMOS transistor 111 is increased, which is beneficial to reducing the output voltage 10d provided by the output voltage adjustment module 101 to the output node 103, thereby reducing the feedback voltage 10b provided by the feedback circuit 104 by dividing the voltage based on the output voltage 10d, so as to reduce the difference between the reference voltage 10a and the feedback voltage 10 b.

In some embodiments, with continued reference to fig. 13, with a sixth node 139 between the sixth terminal and the eighth terminal, the voltage regulator may further include: and one end of the bias voltage module 150 is coupled to the sixth node 139, and the other end of the bias voltage module 150 is coupled to the ground. The bias voltage module 150 may be used as a power supply module of the voltage regulator, which is beneficial to the voltage regulator working based on the reference voltage 10a with a larger value. In one example, the bias voltage module 150 may include a fifth NMOS transistor, a control terminal of the fifth NMOS transistor receives the bias voltage 10e, a first terminal of the fifth NMOS transistor is coupled to the sixth node 139, and a second terminal of the fifth NMOS transistor is coupled to the ground terminal.

In summary, in the start-up phase of the operation of the voltage regulator, the driving voltage adjusting module 105 adjusts the potential at the first node 102, so that the potential at the first node 102 quickly reaches the potential required for starting the output voltage adjusting module 101, and the output voltage adjusting module 101 is started quickly, thereby increasing the speed at which the output voltage adjusting module 101 provides the output voltage 10d to the output node 103, and facilitating the speed of starting up the voltage regulator. Further, after the output voltage regulating module 101 provides the output voltage 10d to the output node 103 for the first time, the feedback circuit 104 divides the output voltage 10d to provide the feedback voltage 10b to the comparison module 100, the comparison module 100 compares the reference voltage 10a and the feedback voltage 10b and generates the error voltage 10c, and the output voltage regulating module 101 adjusts the input voltage received by the output voltage regulating module 101 based on the error voltage 10c to provide the output voltage 10d to the output node 103.

Another embodiment of the present disclosure further provides a control method of a voltage regulator, which is used for controlling the voltage regulator provided in the foregoing embodiment. A control method of a voltage regulator according to another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as those in the foregoing embodiments are not described in detail herein.

Referring to fig. 13, a control method of the voltage regulator includes: providing a voltage regulator according to any one of the preceding claims; the reference voltage 10a and the driving voltage are provided, and in a start-up phase of the operation of the voltage regulator, the driving voltage adjusting module 105 adjusts the potential at the first node 102 based on the driving voltage to cause the feedback circuit 104 to generate the feedback voltage 10b, and to cause the comparing module 100 to generate the error voltage 10c based on the reference voltage 10a and the feedback voltage 10b, and to cause the output voltage adjusting module 101 to generate the output voltage 10d based on the error voltage 10 c.

So, at the start-up stage of stabiliser work, adjust the electric potential of first node 102 department based on drive voltage earlier for the electric potential of first node 102 department reaches the required electric potential of start output voltage regulation module 101 fast, with quick start output voltage regulation module 101, thereby improve output voltage regulation module 101 and provide output voltage 10 d's speed to output node 103, thereby be favorable to accelerating the start-up of stabiliser.

In some embodiments, the output voltage regulating module 101 includes a first PMOS transistor or a first NMOS transistor; the driving voltage includes an enable signal 11a and an adjust signal 11 b. How the driving voltage adjusting module 105 adjusts the potential at the first node 102 based on the driving voltage is described with reference to the foregoing embodiments, and is not repeated herein.

In some embodiments, the step of providing the driving voltage comprises: providing an enable signal 11 a; the adjustment signal 11b is generated based on the start signal 11 a. As to how to generate the adjustment signal 11b based on the start signal 11a, reference is made to the related description of the foregoing embodiments, which will not be repeated herein.

In some embodiments, the control method of the voltage regulator further includes: the bias voltage 10e is provided, the comparison module 100 receives the bias voltage 10e, and the bias voltage 10e can be used as a power supply of the voltage regulator, so that the voltage regulator can work based on the reference voltage 10a with a larger value.

In summary, the control method of the voltage regulator according to another embodiment of the disclosure is beneficial to quickly start the output voltage regulating module 101 by enabling the potential at the first node 102 to reach the potential required for starting the output voltage regulating module 101 in the start-up phase of the operation of the voltage regulator, so as to increase the speed at which the output voltage regulating module 101 provides the output voltage 10d to the output node 103, thereby being beneficial to accelerating the start-up of the voltage regulator.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the embodiments of the present disclosure in practice. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the embodiments of the present disclosure, and it is therefore intended that the scope of the embodiments of the present disclosure be limited only by the terms of the appended claims.

Claims

1. A voltage regulator, comprising:

a comparison module configured to compare a reference voltage and a feedback voltage and generate an error voltage based on the comparison;

an output voltage regulation module coupled to the output of the comparison module at a first node and configured to adjust the input voltage received by the output voltage regulation module based on the error voltage to provide an output voltage to an output node;

a feedback circuit coupled between the output node and a ground voltage, the feedback circuit configured to divide the output voltage to provide the feedback voltage;

and the driving voltage regulating module is coupled with the first node and used for regulating the potential at the first node in the starting stage of the operation of the voltage stabilizer.

2. The voltage regulator of claim 1, wherein the drive voltage adjustment module is configured to: reducing a time taken to adjust the input voltage received by the output voltage regulation module.

3. The voltage regulator of claim 1, wherein the drive voltage adjustment module comprises:

the starting unit is coupled with the control end of the output voltage regulating module and stops regulating the potential of the first node based on a starting signal so as to start the voltage stabilizer;

and the adjusting unit is coupled with the control end of the output voltage adjusting module and adjusts the potential of the first node based on an adjusting signal so as to accelerate the starting of the voltage stabilizer.

4. The voltage regulator of claim 3, wherein the output voltage regulation module comprises a first PMOS transistor, a control terminal of the first PMOS transistor being coupled to the first node, a first terminal of the first PMOS transistor being coupled to a working power supply, a second terminal of the first PMOS transistor being coupled to the output node.

5. The voltage regulator of claim 4, wherein the start-up unit comprises a second PMOS transistor, wherein the regulation unit comprises a second NMOS transistor, wherein a control terminal of the second PMOS transistor receives the start-up signal, a first terminal of the second PMOS transistor is coupled to the operating power supply, a second terminal of the second PMOS transistor is coupled to the first node, a control terminal of the second NMOS transistor receives the regulation signal, a first terminal of the second NMOS transistor is coupled to ground, and a second terminal of the second NMOS transistor is coupled to the first node.

6. The voltage regulator of claim 4, wherein the start-up unit comprises a second NMOS transistor, and the regulation unit comprises a second PMOS transistor, wherein a control terminal of the second NMOS transistor receives the start-up signal, a first terminal of the second NMOS transistor is coupled to the operating power supply, a second terminal of the second NMOS transistor is coupled to the first node, a control terminal of the second PMOS transistor receives the regulation signal, a first terminal of the second PMOS transistor is coupled to ground, and a second terminal of the second PMOS transistor is coupled to the first node.

7. The voltage regulator of claim 3, wherein the output voltage regulation module comprises a first NMOS transistor, a control terminal of the first NMOS transistor is coupled to the first node, a first terminal of the first NMOS transistor is coupled to an operating power source, and a second terminal of the first NMOS transistor is coupled to the output node.

8. The voltage regulator of claim 7, wherein the start-up unit comprises a second PMOS transistor, wherein the regulation unit comprises a second NMOS transistor, wherein a control terminal of the second PMOS transistor receives the start-up signal, a first terminal of the second PMOS transistor is coupled to ground, a second terminal of the second PMOS transistor is coupled to the first node, a control terminal of the second NMOS transistor receives the regulation signal, a first terminal of the second NMOS transistor is coupled to the operating power supply, and a second terminal of the second NMOS transistor is coupled to the first node.

9. The voltage regulator of claim 7, wherein the enable unit comprises a second NMOS transistor, and the regulation unit comprises a second PMOS transistor, a control terminal of the second NMOS transistor receiving the enable signal, a first terminal of the second NMOS transistor coupled to ground, a second terminal of the second NMOS transistor coupled to the first node, a control terminal of the second PMOS transistor receiving the regulation signal, a first terminal of the second PMOS transistor coupled to the operating power supply, and a second terminal of the second PMOS transistor coupled to the first node.

10. The voltage regulator according to claim 5 or 8, further comprising: a signal generation module for generating the adjustment signal based on the start signal; and generating the adjusting signal based on the starting signal, wherein the generating of the adjusting signal comprises performing logical AND operation on a signal obtained by sequentially performing phase inversion and time delay processing on the starting signal and the starting signal to generate the adjusting signal.

11. The voltage regulator of claim 10, wherein the signal generation module comprises:

the input end of the inverting unit receives the starting signal;

the input end of the delay unit is coupled with the output end of the inverting unit;

and the first input end of the AND gate circuit is coupled with the output end of the delay unit, the second input end of the AND gate circuit receives the starting signal, and the output end of the AND gate circuit outputs the adjusting signal.

12. The voltage regulator according to claim 6 or 9, further comprising: a signal generation module for generating the adjustment signal based on the start signal; and generating the adjusting signal based on the starting signal, wherein the generating of the adjusting signal comprises performing logical OR operation on a signal obtained by sequentially performing phase inversion and time delay processing on the starting signal and the starting signal to generate the adjusting signal.

13. The voltage regulator of claim 12, wherein the signal generation module comprises:

the input end of the inverting unit receives the starting signal;

the first input end of the OR gate circuit is coupled with the output end of the delay unit, the second input end of the OR gate circuit receives the starting signal, and the output end of the OR gate circuit outputs the adjusting signal.

14. The voltage regulator of claim 1, wherein the feedback circuit comprises:

a first voltage division module coupled between the output node and the comparison module;

the second voltage division module is coupled between the first voltage division module and a ground terminal, and the feedback voltage is a potential at a coupling position of the first voltage division module and the second voltage division module.

15. The voltage regulator of claim 1, wherein the comparison module comprises:

the third PMOS tube, the fourth PMOS tube, the third NMOS tube and the fourth NMOS tube;

the control end of the third PMOS tube is coupled with the control end of the fourth PMOS tube, and a third node is arranged between the control ends of the third PMOS tube and the fourth PMOS tube;

a first end of the third PMOS transistor and a third end of the fourth PMOS transistor are coupled to a working power supply, a second end of the third PMOS transistor is coupled to a fifth end of the third NMOS transistor, a fourth end of the fourth PMOS transistor is coupled to a seventh end of the fourth NMOS transistor, a fourth node is arranged between the second end and the fifth end, the fourth node is coupled to the first node, a fifth node is arranged between the fourth end and the seventh end, and the fifth node is coupled to the third node;

the sixth end of the third NMOS transistor and the eighth end of the fourth NMOS transistor are coupled to the ground, the control end of the third NMOS transistor is the first input end of the comparison module, the control end of the fourth NMOS transistor is the second input end of the comparison module, and the fourth node is the output end of the comparison module.

16. The voltage regulator of claim 15, wherein a sixth node is located between the sixth terminal and the eighth terminal, the voltage regulator further comprising: a control end of the fifth NMOS transistor receives a bias voltage, a first end of the fifth NMOS transistor is coupled to the sixth node, and a second end of the fifth NMOS transistor is coupled to the ground.

17. A control method of a voltage regulator, comprising:

providing a voltage regulator according to any one of claims 1 to 16;

and providing a reference voltage and a driving voltage, wherein in a starting stage of the operation of the voltage stabilizer, the driving voltage adjusting module adjusts the potential at the first node based on the driving voltage so as to enable the feedback circuit to generate a feedback voltage, and enable the comparing module to generate an error voltage based on the reference voltage and the feedback voltage, and enable the output voltage adjusting module to generate an output voltage based on the error voltage.

18. The control method of claim 17, wherein the output voltage regulation module comprises a first PMOS transistor or a first NMOS transistor; the driving voltage includes an enable signal and a regulation signal.

19. The control method of claim 18, wherein the step of providing the driving voltage comprises:

providing a start signal;

generating the adjustment signal based on the activation signal.

20. The control method according to claim 17, further comprising: providing a bias voltage, the comparison module receiving the bias voltage.