CN114553357A - Multimode synchronous clock server and frequency compensation method - Google Patents
Multimode synchronous clock server and frequency compensation method Download PDFInfo
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
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Abstract
The application provides a multimode synchronous clock server and a frequency compensation method. The method and the device insert PN sequences by using periodically-appearing position code elements P in the B code, provide synchronization, generate time-frequency integrated signals, and synchronously realize transmission of time reference signals and frequency reference signals. In addition, the method and the device also transmit two paths of orthogonal signals synchronously and independently in the signal sending process, utilize the phase difference between the two paths of signals to realize the fine adjustment of the phase-locked phase of the phase-locked loop at the receiving end, and realize the frequency compensation according to the signal phase difference. The method can accurately realize clock synchronization and phase synchronization before a plurality of receiving ends connected with the server. According to the method and the device, time-frequency integrated transmission can be realized, time and frequency accurate transmission based on B codes is realized through one transmission link, link multiplexing is realized, the self-correlation characteristic of a PN sequence is fully utilized, time-frequency synchronization can be realized in a low-complexity mode under the conditions of strong interference and high dynamic environment, the cost is lower, and the synchronization is more reliable.
Description
Technical Field
The application relates to the technical field of communication engineering, in particular to a multimode synchronous clock server and a frequency compensation method.
Background
The time-frequency synchronization technology plays a vital role in the fields of electric power, communication and the like, and is the basis for normal operation of a power grid and a communication network. In the prior art, time synchronization is relatively mature, but frequency synchronization technology transmission is not popularized yet. The existing time synchronization technology is generally realized by adopting a software protocol to perform clock alignment and timing technology. The existing software synchronization mode has large error, and the dual synchronization of the clock and the frequency can be realized only by independently setting a frequency synchronization module.
Disclosure of Invention
Aiming at the defects of the prior art, the application provides the multimode synchronous clock server and the frequency compensation method, and the time-frequency integrated transmission is directly realized through a coding mode. The technical scheme is specifically adopted in the application.
First, to achieve the above object, a frequency compensation method is provided for a multimode synchronous clock server, including the steps of: firstly, carrying out IRIG-B code encoding on a time reference signal, wherein the code element period of the B code is set to be integral multiple of the frequency reference signal, and obtaining a B code pulse sequence; secondly, adjusting the rising edge of a position code element P in the B code pulse sequence to be synchronous and consistent with the rising edge of the frequency reference signal; thirdly, inserting a PN sequence at the position code element P to obtain a time-frequency integrated signal, wherein the amplitude of the PN sequence is set to be not less than the amplitude of the B code pulse sequence; fourthly, performing negation or orthogonal processing on the time-frequency integrated signal to obtain two paths of signals, and simultaneously transmitting the two paths of signals; and simultaneously receiving the two paths of signals at a receiving end, adjusting the output voltage of a phase discriminator in a phase-locked loop of the receiving end according to the phase difference of the PN sequence between the two paths of signals, and compensating a synchronous result obtained by the receiving end according to the sliding matching of the PN sequence.
Optionally, the method for frequency compensation as described in any above, wherein the B code symbol period is set to be 2 times, 4 times, or 2^ n times of the frequency reference signal, where n is a positive integer.
Optionally, the method for frequency compensation as described in any above, wherein the PN code is a sequence with autocorrelation characteristics and of a specific length composed of equal numbers "-1" and "+ 1", and the symbol rate of the sequence is set to be 2 times, 4 times or 2^ m times of the frequency reference signal, where m is a positive integer and m > n.
Optionally, in the frequency compensation method, after receiving the two signals, the receiving end: firstly, data corresponding to a PN sequence in one path of signal is taken as a synchronous signal, a received signal is in sliding matching with a local synchronous signal, and time domain searching is carried out on the received signal to obtain a synchronous result; and adjusting the output voltage of the phase discriminator in the phase-locked loop according to the phase difference of the PN sequences between the two paths of signals by taking the frequency corresponding to the synchronization result as a reference frequency source, and performing frequency compensation on the synchronization result obtained by the receiving end according to the sliding matching of the PN sequences.
Meanwhile, to achieve the above object, the present application further provides a multimode synchronous clock server, which includes: the B code modulation module is used for carrying out IRIG-B code coding on the time reference signal to obtain a B code pulse sequence, wherein the code element period of the B code is set to be integral multiple of the frequency reference signal; the time-frequency synchronization module is used for carrying out frequency phase modulation on the B code pulse sequence and adjusting the rising edge of the position code element P in the B code pulse sequence to be synchronous with the rising edge of the frequency reference signal; the PN sequence module is used for inserting a PN sequence into a position code element P in the B code pulse output by the time frequency synchronization module to obtain a time frequency integrated signal; and the sending module is used for carrying out inversion or orthogonal processing on the time-frequency integrated signal, and simultaneously sending two paths of signals obtained by the inversion or orthogonal processing so as to trigger the receiving end to adjust the output voltage of a phase discriminator in the phase-locked loop of the receiving end according to the phase difference of the PN sequence between the two paths of signals after receiving the two paths of signals, and compensate the synchronization result obtained by the receiving end according to the sliding matching of the PN sequence.
Optionally, the multimode synchronous clock server according to any of the above, wherein the frequency reference signal is a pulse per second; and the time-frequency synchronization module is used for adjusting the rising edge of the position code element P in the B code pulse sequence to be synchronous with the rising edge of the second pulse.
Optionally, the multimode synchronous clock server as in any of the above, wherein the B-code symbol period is set to be 2 times, 4 times or 2^ n times of the frequency reference signal, where n is a positive integer.
Optionally, the multimode synchronous clock server as described in any of the above, wherein the PN code is a sequence with autocorrelation characteristics of a specific length composed of equal numbers "-1" and "+ 1", and the symbol rate of the sequence is set to be 2 times, 4 times or 2^ m times of the frequency reference signal, where m is a positive integer and m > n.
Optionally, the multimode synchronous clock server as described in any of the above, wherein a receiving end in communication connection with the server is provided with: the difference unit is used for calculating the phase difference of the PN sequences between the two received signals and outputting a regulating voltage according to the phase difference; the synchronization unit takes data corresponding to a PN sequence in one path of signal as a synchronization signal, performs sliding matching on a received signal and a local synchronization signal, and performs time domain search on the received signal to obtain a synchronization result; and the phase-locked loop takes the synchronization result as a reference frequency source, adjusts the output voltage of a phase discriminator in the phase-locked loop of the receiving end according to the phase difference of the PN sequence between the two paths of signals, compensates the synchronization result obtained by sliding matching according to the PN sequence in the receiving end, and outputs a frequency reference signal.
Optionally, the multimode synchronous clock server as described in any of the above, wherein a receiving end in communication connection with the server is further provided with: the P code unit is used for replacing a PN sequence contained in the receiving end with a position code element P according to the frequency reference signal to obtain a B code; and the B code demodulation unit is used for demodulating the B code obtained after the replacement to obtain a time reference signal.
Advantageous effects
The application provides a multimode synchronous clock server and a frequency compensation method. The method and the device insert PN sequences by using periodically-appearing position code elements P in the B code, provide synchronization, generate time-frequency integrated signals, and synchronously realize transmission of time reference signals and frequency reference signals. In addition, the method and the device also transmit two paths of orthogonal signals synchronously and independently in the signal sending process, utilize the phase difference between the two paths of signals to realize the fine adjustment of the phase-locked phase of the phase-locked loop at the receiving end, and realize the frequency compensation according to the signal phase difference. The method can accurately realize clock synchronization and phase synchronization before a plurality of receiving ends connected with the server. According to the method and the device, time-frequency integrated transmission can be realized, time and frequency accurate transmission based on B codes is realized through one transmission link, link multiplexing is realized, the self-correlation characteristic of a PN sequence is fully utilized, time-frequency synchronization can be realized in a low-complexity mode under the conditions of strong interference and high dynamic environment, the cost is lower, and the synchronization is more reliable.
In the application, the period of the code element of the B code and the gesture of the PN code are further set to be integral multiples of the second pulse frequency reference, periodic signal components can be directly extracted from the rising edge or the falling edge of the code element signal and serve as a trigger signal of an auxiliary phase calibration signal or a phase-locked loop reference frequency source, and coarse positioning of signal frequency is provided.
In the application, the PN code is designed into a large amplitude sequence with the autocorrelation characteristic and the specific length, wherein the large amplitude sequence is composed of "-1" and "+ 1" which are equal in number, so that a receiving end can directly identify the PN code in an amplitude filtering mode conveniently, a clock source of the receiving end is roughly calibrated through the interval period between the PN codes, time-frequency synchronization of received signals is further realized through the PN code, and time-frequency accurate synchronization is realized through a differential phase.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not limit the application. In the drawings:
FIG. 1 is a schematic diagram of a frequency compensation system in a multimode synchronous clock server according to the present application;
fig. 2 is a schematic diagram of a reference frequency compensation method performed by a phase-locked loop provided at a receiving end in the present application.
Detailed Description
In order to make the purpose and technical solutions of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings of the embodiments of the present application. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the application without any inventive step, are within the scope of protection of the application.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The term "connected" as used herein may mean either a direct connection between components or an indirect connection between components via other components.
Fig. 1 is a multimode synchronous clock server according to the present application, comprising:
the time reference signal module is used for outputting time synchronization signals and time code information such as seconds, minutes, hours, days and the like;
the frequency reference signal module is used for outputting pulse per second;
the B code modulation module is used for carrying out IRIG-B code coding on time code information of a time reference signal to obtain a B code pulse sequence, and considering that a frequency reference signal in the application is pulse per second, the application can be distinguished from the traditional B code modulation technology, and the B code element period can be flexibly adjusted to be integral multiple of the frequency reference signal, for example, 2, 4, 8 or 2^ n B code elements are corresponding to one pulse per second period, wherein n is a positive integer, so that a rough reference frequency doubling signal is provided through the rising edge or the falling edge of the code elements per se, and a receiving end can conveniently track the frequency of a server;
the time-frequency synchronization module is used for carrying out frequency phase modulation on the B code pulse sequence, adjusting the rising edge of the position code element P in the B code pulse sequence to be synchronous with the rising edge of the frequency reference signal and keeping the pace completely consistent so as to facilitate the rough estimation of the starting time of the rising edge of the frequency reference signal by detecting the position code element P;
a PN sequence module, configured to insert a PN sequence into a position symbol P in a B code pulse output by the time-frequency synchronization module to obtain a time-frequency integrated signal, where the step belongs to adjustment of a time-domain waveform, but in order to facilitate a receiving end to roughly estimate a frequency reference signal, the application may also preferably set a symbol period of the PN sequence to be an integer multiple of the frequency reference signal, but when replacing the P code, the PN sequence is distinguished from an existing B code symbol, and generally it is required to set a symbol rate of the sequence in the PN sequence to exceed the B code, and set the symbol rate to be 2 times, 4 times, or 2^ m times of the frequency reference signal, where m is a positive integer and m > n;
and the sending module is used for carrying out inversion or orthogonal processing on the time-frequency integrated signal and simultaneously sending two paths of signals obtained by the inversion or orthogonal processing.
After receiving the two paths of signals, a receiving end in communication connection with the server:
firstly, data corresponding to a PN sequence in a path of signal is taken as a synchronous signal, the length of an estimation window and the length of a search window positioned in the estimation window are determined, the search window starts sliding search from the initial position of the estimation window in the estimation window, a received signal and a local synchronous signal are subjected to sliding matching, when the search window starts sliding search from the initial position of the estimation window in the estimation window, a first correlation value of the search window is determined in real time, and a first threshold value is determined according to the first correlation value; if the first correlation value of the search window is greater than the first threshold, the signal is detected, sliding search is finished, and meanwhile, the starting point of a time slot corresponding to the first correlation value peak of the search window is taken out to be used as a timing synchronization result to perform time domain search on the received signal to obtain a synchronization result;
and according to the proportion between the phase difference and the signal period corresponding to the synchronization result, the voltage value corresponding to the phase difference is superposed on the output voltage of the phase discriminator so as to adjust the locking phase of the phase-locked loop, and the frequency compensation of the synchronization result obtained according to the sliding matching of the PN sequence in a receiving end is realized.
Specifically referring to fig. 1, each receiving end may be respectively configured to include:
the difference unit is used for calculating the phase difference of the PN sequences between the two received signals and outputting a regulating voltage according to the phase difference;
the synchronization unit takes data corresponding to a PN sequence in one path of signal as a synchronization signal, performs sliding matching on a received signal and a local synchronization signal, and performs time domain search on the received signal to obtain a synchronization result;
a phase-locked loop, which uses the synchronization result as a reference frequency source through the mode of fig. 2, adjusts the output voltage of a phase discriminator in the phase-locked loop of a receiving end according to the phase difference of the PN sequence between two signals, compensates the synchronization result obtained according to the sliding matching of the PN sequence in the receiving end, and outputs a frequency reference signal;
the P code unit is used for replacing a PN sequence contained in the receiving end with a position code element P according to the frequency reference signal to obtain a complete B code signal;
and the B code demodulation unit is used for demodulating the B code obtained after the replacement to obtain a time reference signal.
In the time-frequency synchronization process, in order to further facilitate obtaining the synchronization result through the PN sequence, the PN code can be further set into a sequence with autocorrelation characteristics and a specific length, wherein the sequence is composed of "-1" and "+ 1" in equal number, and the symbol rate of the sequence is set to exceed the code element period of the B code and is 2 times, 4 times or 2^ m times of the frequency reference signal. Therefore, the receiving end can directly obtain periodic pulses consisting of "-1" and "+ 1" through the screening of the amplitude or the signal polarity at the previous stage, extract corresponding frequency multiplication of the reference frequency through the rising edge of the pulse, and perform m frequency division on the frequency multiplication to obtain a preliminary estimation frequency corresponding to the reference frequency. A preliminary estimated frequency can also be obtained by dividing the B-code by the period of the rising edge of the signal in the symbol period. The two preliminarily estimated frequencies can be used for roughly estimating the reference frequency and determining the sliding step length in the process of PN sequence sliding matching.
Therefore, the frequency-multiplied PN sequence is inserted into the B code, so that the frequency reference estimation signal is provided, and the synchronous transmission of the time reference signal and the frequency reference signal is realized. The phase deviation value obtained by difference between two paths of orthogonal or opposite signals can be used for realizing fine adjustment of the output amplitude of the phase-locked loop phase discriminator, so that frequency compensation is correspondingly realized. The method and the device can directly improve the accuracy of time frequency synchronization in the system in a coding and decoding mode. The method and the device make full use of the autocorrelation characteristic of the PN sequence, can realize time-frequency synchronization in a low-complexity mode under strong interference and high dynamic environment, and are lower in cost and more reliable in synchronization.
The above are merely embodiments of the present application, and the description is specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the protection scope of the present application.
Claims (10)
1. A frequency compensation method for a multimode synchronous clock server, comprising the steps of:
firstly, carrying out IRIG-B code encoding on a time reference signal, wherein the code element period of the B code is set to be integral multiple of the frequency reference signal, and obtaining a B code pulse sequence;
secondly, adjusting the rising edge of a position code element P in the B code pulse sequence to be synchronous and consistent with the rising edge of the frequency reference signal;
thirdly, inserting a PN sequence at the position code element P to obtain a time-frequency integrated signal, wherein the amplitude of the PN sequence is set to be not less than the amplitude of the B code pulse sequence;
fourthly, performing negation or orthogonal processing on the time-frequency integrated signal to obtain two paths of signals, and simultaneously transmitting the two paths of signals;
and simultaneously receiving the two paths of signals at a receiving end, adjusting the output voltage of a phase discriminator in a phase-locked loop of the receiving end according to the phase difference of the PN sequence between the two paths of signals, and compensating a synchronous result obtained by the receiving end according to the sliding matching of the PN sequence.
2. The frequency compensation method of claim 1, wherein the B-code symbol period is set to 2 times, 4 times, or 2^ n times the frequency reference signal, where n is a positive integer.
3. The frequency compensation method of claim 2, wherein the PN code is a sequence of a specific length having autocorrelation characteristics consisting of "-1" and "+ 1" in equal numbers, and a symbol rate of the sequence is set to 2 times, 4 times, or 2^ m times the frequency reference signal, where m is a positive integer and m > n.
4. The frequency compensation method of any of claims 1-3, wherein after receiving two signals, the receiving end:
firstly, data corresponding to a PN sequence in one path of signal is taken as a synchronous signal, a received signal is in sliding matching with a local synchronous signal, and time domain searching is carried out on the received signal to obtain a synchronous result;
and adjusting the output voltage of the phase discriminator in the phase-locked loop according to the phase difference of the PN sequences between the two paths of signals by taking the frequency corresponding to the synchronization result as a reference frequency source, and performing frequency compensation on the synchronization result obtained by the receiving end according to the sliding matching of the PN sequences.
5. A multimode synchronous clock server, comprising:
the B code modulation module is used for carrying out IRIG-B code coding on the time reference signal to obtain a B code pulse sequence, wherein the code element period of the B code is set to be integral multiple of the frequency reference signal;
the time-frequency synchronization module is used for carrying out frequency phase modulation on the B code pulse sequence and adjusting the rising edge of the position code element P in the B code pulse sequence to be synchronous with the rising edge of the frequency reference signal;
the PN sequence module is used for inserting a PN sequence into a position code element P in the B code pulse output by the time frequency synchronization module to obtain a time frequency integrated signal;
and the sending module is used for carrying out inversion or orthogonal processing on the time-frequency integrated signal, and simultaneously sending two paths of signals obtained by the inversion or orthogonal processing so as to trigger the receiving end to adjust the output voltage of a phase discriminator in the phase-locked loop of the receiving end according to the phase difference of the PN sequence between the two paths of signals after receiving the two paths of signals, and compensate the synchronization result obtained by the receiving end according to the sliding matching of the PN sequence.
6. The multimode synchronous clock server of claim 5, wherein the frequency reference signal is a pulse-per-second;
and the time-frequency synchronization module is used for adjusting the rising edge of the position code element P in the B code pulse sequence to be synchronous with the rising edge of the second pulse.
7. The multimode synchronous clock server of claim 6, wherein the B-code symbol period is set to 2 times, 4 times, or 2^ n times the frequency reference signal, where n is a positive integer.
8. The multimode synchronous clock server of claim 7, wherein the PN code is a sequence of a specific length having autocorrelation properties consisting of equal numbers of "-1" and "+ 1", the symbol rate of the sequence being set to 2 times, 4 times, or 2^ m times the frequency reference signal, where m is a positive integer and m > n.
9. The multimode synchronized clock server of any of claims 1-8, wherein the server is communicatively coupled to a receiver having:
the difference unit is used for calculating the phase difference of the PN sequences between the two received signals and outputting a regulating voltage according to the phase difference;
the synchronization unit takes data corresponding to a PN sequence in one path of signal as a synchronization signal, performs sliding matching on a received signal and a local synchronization signal, and performs time domain search on the received signal to obtain a synchronization result; and the phase-locked loop takes the synchronization result as a reference frequency source, adjusts the output voltage of a phase discriminator in the phase-locked loop of the receiving end according to the phase difference of the PN sequence between the two paths of signals, compensates the synchronization result obtained by sliding matching according to the PN sequence in the receiving end, and outputs a frequency reference signal.
10. The multimode synchronized clock server of claim 9, wherein the receiver to which the server is communicatively coupled further comprises:
the P code unit is used for replacing a PN sequence contained in the receiving end with a position code element P according to the frequency reference signal to obtain a B code;
and the B code demodulation unit is used for demodulating the B code obtained after the replacement to obtain a time reference signal.
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| EP1193934A2 (en) * | 2000-09-29 | 2002-04-03 | Samsung Electronics Co., Ltd. | Frequency offset correction in multicarrier receivers |
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