CN206100006U - Electric power system is high accuracy IRIG for time lock device is realized to B code signal - Google Patents
Electric power system is high accuracy IRIG for time lock device is realized to B code signal Download PDFInfo
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- CN206100006U CN206100006U CN201621057824.3U CN201621057824U CN206100006U CN 206100006 U CN206100006 U CN 206100006U CN 201621057824 U CN201621057824 U CN 201621057824U CN 206100006 U CN206100006 U CN 206100006U
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Abstract
The utility model relates to an electric power system time synchronization technology field, concretely relates to electric power system is high accuracy IRIG for time lock device is realized to B code signal, including big dipper satellite receiver and IRIG B sign indicating number modulation generation module, big dipper satellite system receiver is installed in power system operation on -the -spotly, is big dipper satellite receiver output connected to IRIG B sign indicating number modulation generation module and MCU, IRIG does B sign indicating number modulation generation module include frequency division signal synchronization treatment circuit and IRIG the B code character becomes cell formation and the synthetic output circuit of code element. The utility model discloses an is nanosecond level high accuracy IRIG carried out to big dipper satellite system time information source does the design of B sign indicating number improve IRIG reliably B sign indicating number time synchronization signal to the time the precision, the time synchronization signal of high accuracy can satisfy under the different occasions timing tracking accuracy requirement of various operation equipment and system.
Description
Technical field
This utility model is related to power system Time synchronization technique field, and in particular to a kind of power system time synchronized is used
High accuracy IRIG-B code signal realizes device.
Background technology
Power system Time synchronization technique plays increasingly consequence in power system power generation.In mistake
Go, time synchronized carry no weight in power system, the respective run time low precision of the secondary device of power system, disunity,
It is that power generation and Power System Events analysis bring inconvenience, it is impossible to timely and effectively carry out event summary and anatomy, with
The requirement more and more higher of Operation of Electric Systems, the technology of secondary system equipment is constantly upgraded development, and run time is synchronously had
Extensive requirement, has further harsh requirement, the original method of operation and signal to the precision of signal during time synchronized pair
Precision can not meet the needs of power system development, and original time precision can not cover all devices of operation in power system
And system.With the broad development of intelligent Power Station digitizing technique, power system is for time synchronized and the precision of clock monitor
Require will more and more higher, this is accomplished by the further raising of Time synchronization technique, to meet the need of the continuous development of power system
Will.
Utility model content
To solve above-mentioned technical problem, the purpose of this utility model is：There is provided a kind of power system time synchronized high
Precision IRIG-B code signal realizes device, provides split-second precision guarantee to power generation.
The technical scheme that this utility model is adopted by solution its technical problem for：
The power system time synchronized high accuracy IRIG-B code signal realizes device, including big-dipper satellite receptor and
IRIG-B codes modulate generation module, and Beidou satellite system receptor is installed on Operation of Electric Systems scene, big-dipper satellite receptor
Outfan is connected to IRIG-B codes modulation generation module and MCU, and the IRIG-B codes modulation generation module includes that fractional frequency signal is same
Step process circuit and IRIG-B codes composition cell are generated and code element synthesis output circuit.
Continuous development and power system more application scenario pair of this utility model for Power System Intelligent technology
The requirements at the higher level of Time synchronization technique, with reference to the operation reality of power system engineering site, it is proposed that utilize Beidou satellite system
The time information source of output improves the scheme of power system time synchronizing signal IRIG-B code precision.This device is by power system
Operation in-site installation Beidou satellite system receptor, introduces split-second precision information source.
Wherein, preferred version is：
The Beidou satellite system receptor correspondence installs antenna, strengthens Beidou satellite system receptor reception signal strong
Degree, it is ensured that signal source precision.
The fractional frequency signal synchronous processing circuit includes NAND gate, frequency dividing information source and 10 branch frequency counting circuits, MCU outputs
T1 ends enter 10 frequency division counters electricity by two-stage NAND gate 1D22A and 1D22B logic controls and after opening frequency dividing information source 10MHz
Road, produces 1MHz, 100kHz, 10kHz, 1kHz and 1Hz signal respectively, and 10 branch frequency counting circuit includes the frequency dividing core for cascading
Piece and the counting chip of cascade, Big Dipper 1PPS signals respectively divide chip and the MR ends of counting chip provide set signal；Institute
State frequency dividing information source and adopt constant-temperature crystal oscillator, the signal stabilization opened into frequency dividing information source is ensured during being easy to long-play；It is described
IRIG-B codes composition cell is generated and code element synthesis output circuit includes that cell generative circuit, data selector and data are latched
Device, cell generative circuit outfan are connected to data selector input, and data selector control end is controlled by the P17 that MCU is exported
Line processed, 1Hz signals and 10Hz signal co- controllings, the outfan of data selector connect an input of data latches, Jing
Cross the accurately complete IRIG-B time encodings of the outfan output of data latches.
This device course of work is as follows：
First, big-dipper satellite receptor receives satellite-signal, and locking keeps tracking mode, obtains satellite time information, carries
The time information source information of taking is exported to IRIG-B codes and modulates generation module and MCU；
Second step, it is same to fractional frequency signal that IRIG-B codes modulation generation module introduces split-second precision benchmark Big Dipper 1PPS signals
Step process circuit carries out signal synchronization process so that the signal accuracy for participating in encoding in IRIG-B codes reaches nanosecond, divides
Signal synchronous processing circuit produces 1kHz, 10kHz, 100kHz fractional frequency signal, and cell generative circuit produces the cell 1 of IRIG-B codes
(5ms), cell 0 (2ms) and location recognition mark cell P (8ms)；
3rd step, the tri- kinds of signals of P17 control lines and 1Hz, 10Hz exported by MCU are precisely controlled data selector together
Three kinds of cell outputs of IRIG-B codes are chronologically gated, and IRIG-B code signal outputs are combined through data latches.
The signal period of IRIG-B codes is 1 second, is divided into 10 groups of code elements, and each group of code element begins with a tick lables Pn
(P1-P9).The control line P17 of MCU outputs, carries out set (0 or 1) by programme-control according to the temporal information that MCU is received, week
Phase is 10ms, and MCU receives pulse per second (PPS) to interrupt.When pulse per second (PPS) arrives, hardware produces the punctual mark P of secondr, data selector
Control signal is divided into 10 groups 1 second duration carries out block encoding, every group of code element start time control data selector strobe position
Recognition marks cell P, subsequently by MCU according to second time, point, when, the temporal information such as day change Synchronization Control P17 produce the second, point,
When, the data processing of the temporal information such as day, P17 correspondingly carries out bit count, and the code-element period of P17 output signals is 10ms,
P in first group of code elementr4 code elements (BCD codings) afterwards represent 1,2,4, the 8 of the second respectively, and the common individual position for representing the second counts, with
Be afterwards the second and point spacing element, 3 code elements afterwards represent 10,20 and the 40 of the second respectively, and the information of such second is by P17 controls
Line traffic control data selector processed realizes the BCD codings of second in IRIG-B codes, same reason in packet code element afterwards according to
It is secondary realize point, when, the BCD codings of the IRIG-B of temporal information such as day.
MCU is inquired about and management and control to the input state and output signal accuracy of Big Dipper information source, institute during device use
The calculation procedure of dependence belongs to technology as well known to those skilled in the art.
Compared with prior art, this utility model has the advantages that：
This utility model carries out the design of nanosecond high accuracy IRIG-B code using Beidou satellite system time information source, reliably
Precision during IRIG-B code time synchronizing signals pair is improved, output signal accuracy reaches 50nS, high-precision time synchronizing signal
The timing tracking accuracy requirement of various operation equipment and system under different occasions can be met.
This device can be widely applied to field of power, and Beidou satellite system signal is received and is easy to peace in engineering site
Dress is implemented, while Beidou satellite system signal can be applied to the fields such as transformer station, power plant, system call using safe and reliable
Power system clock system, can set with the secondary of place such as transformer station, power plant when project is designed
Standby contemporary designs and enforcement, reach the secondary device category for covering power system application comprehensively, reliable to improve the secondary device time
Synchronous running precision, especially to Intelligent transformer station equipment operation there is provided time precision guarantee, effective guarantee electricity
The safety and stability of Force system operation.
In addition, adopting Beidou satellite system provide power-assisted for the development of Chinese dipper system, also further can promote
The development in an all-round way of domestic Beidou satellite system and extensively application.
Description of the drawings
Fig. 1 is this utility model block diagram.
Fig. 2 is fractional frequency signal synchronous processing circuit schematic diagram.
Fig. 3 is that IRIG-B codes composition cell is generated and code element synthesis output circuit schematic diagram.
Fig. 4 is IRIG-B codes modulation generation module signal modulation theory diagram.
Specific embodiment
Below in conjunction with the accompanying drawings this utility model embodiment is described further：
Embodiment 1：
As shown in figure 1, power system time synchronized high accuracy IRIG-B code signal described in the utility model realizes device,
Including big-dipper satellite receptor and IRIG-B codes modulation generation module, Beidou satellite system receptor is installed on Operation of Electric Systems
Scene, big-dipper satellite receptor outfan are connected to IRIG-B codes modulation generation module and MCU, and the IRIG-B codes modulation is generated
Module includes that fractional frequency signal synchronous processing circuit and IRIG-B codes composition cell are generated and code element synthesis output circuit.
Wherein, Beidou satellite system receptor correspondence installs antenna, strengthens Beidou satellite system receptor reception signal strong
Degree, it is ensured that signal source precision；As shown in Fig. 2 fractional frequency signal synchronous processing circuit includes NAND gate, frequency dividing information source and 10 frequency dividing meters
Number circuit, the T1 ends of MCU outputs pass through two-stage NAND gate 1D22A and 1D22B logic controls and open laggard into frequency dividing information source 10MHz
Enter 10 branch frequency counting circuits, produce 1MHz, 100kHz, 10kHz, 1kHz and 1Hz signal, the 10 branch frequency counting circuit bag respectively
The frequency dividing chip of cascade and the counting chip of cascade are included, Big Dipper 1PPS signals respectively divide chip and the MR ends of counting chip carry
For set signal；The frequency dividing information source adopts constant-temperature crystal oscillator, ensures the letter opened into frequency dividing information source during being easy to long-play
It is number stable；As shown in figure 3, IRIG-B codes composition cell is generated and code element synthesis output circuit includes cell generative circuit, data
Selector 5D13 and data latches 5D7,5D16 circuits packet in cell generative circuit produce cell P and cell 1, and 5D18 is produced
Cell 0, three kinds of cells are connected to data selector 5D13 inputs, and data selector 5D13 control ends are controlled by the P17 that MCU is exported
Line processed, 1Hz signals and 10Hz signal co- controllings, using the pulse per second (PPS) in Big Dipper information source as reference, according to the Big Dipper that MCU is received
The temporal information of information source carries out software programming, controls set change (set cycle is 10ms) of P17 data wires in order, so as to control
Data selector 5D13 processed exports the coding of IRIG-B according to cycle second, and the coding in the cycle per second includes ten groups of code elements, per group
Cell count in code element show respectively temporal information second, point, when, the temporal information such as day, data selector 5D13's is defeated
Go out an input of end connection data latches 5D7, through the IRIG-B that the outfan output of data latches 5D7 is accurately complete
Time encoding.
As shown in figure 4, this device course of work is as follows：
First, big-dipper satellite receptor receives satellite-signal, and locking keeps tracking mode, obtains satellite time information, carries
The time information source information of taking is exported to IRIG-B codes and modulates generation module and MCU；
Second step, IRIG-B codes modulation generation module introduce split-second precision benchmark Big Dipper 1PPS signals and frequency dividing circuit are entered
Row signal synchronization process so that the signal accuracy for participating in encoding in IRIG-B codes reaches nanosecond, fractional frequency signal synchronization process
Circuit produces 1kHz, 10kHz, 100kHz fractional frequency signal, and cell produces circuit and produces the cell 1 (5ms) of IRIG-B codes, cell 0
(2ms) with location recognition mark cell P (8ms)；
3rd step, the tri- kinds of signals of P17 control lines and 1Hz, 10Hz exported by MCU are precisely controlled data selector 5D13
Three kinds of cell outputs of IRIG-B codes are chronologically gated, and IRIG-B code signal outputs are converged into through data latches 5D7.
The signal period of IRIG-B codes is 1 second, is divided into 10 groups of code elements, and each group of code element begins with a tick lables Pn
(P1-P9).The control line P17 of MCU outputs, carries out set (0 or 1) by programme-control according to the temporal information that MCU is received, week
Phase is 10ms, and MCU receives pulse per second (PPS) to interrupt.The punctual mark P of second is gated when pulse per second (PPS) arrivesr, data selector 5D13's
Control signal is divided into 10 groups 1 second duration carries out block encoding, every group of code element start time control data selector 5D13 gating
Location recognition mark cell P, subsequently by MCU according to second time, point, when, the temporal information such as day change Synchronization Control P17 produces
Second, point, when, the data processing of the temporal information such as day, P17 correspondingly carries out bit count, and the code-element period of P17 output signals is
10ms, P in first group of code elementr4 code elements (BCD codings) afterwards represent 1,2,4, the 8 of the second respectively, the common individual position meter for representing the second
Number, is followed by second and the spacing element for dividing, and 3 code elements afterwards represent 10,20 and the 40 of the second respectively, and the information of such second passes through
P17 control line control data selector 5D13 realize the BCD codings of second in IRIG-B codes, and same reason is in packet afterwards
Realized in code element successively point, when, the BCD codings of the IRIG-B of temporal information such as day.
MCU is inquired about and management and control to the input state and output signal accuracy of Big Dipper information source, institute during device use
The calculation procedure of dependence belongs to technology as well known to those skilled in the art.
Claims (5)
1. a kind of power system time synchronized high accuracy IRIG-B code signal realizes device, it is characterised in that defend including the Big Dipper
Star receptor and IRIG-B codes modulation generation module, Beidou satellite system receptor are installed on Operation of Electric Systems scene, the Big Dipper
Satellite receiver outfan is connected to IRIG-B codes modulation generation module and MCU, and the IRIG-B codes modulation generation module includes
Fractional frequency signal synchronous processing circuit and IRIG-B codes composition cell are generated and code element synthesis output circuit.
2. power system time synchronized high accuracy IRIG-B code signal according to claim 1 realizes device, its feature
It is that the Beidou satellite system receptor correspondence installs antenna.
3. power system time synchronized high accuracy IRIG-B code signal according to claim 1 realizes device, its feature
It is that the fractional frequency signal synchronous processing circuit includes NAND gate, frequency dividing information source and 10 branch frequency counting circuits, the T1 of MCU outputs
End by two-stage NAND gate 1D22A and 1D22B logic controls and after opening frequency dividing information source 10MHz into 10 branch frequency counting circuits,
1MHz, 100kHz, 10kHz, 1kHz and 1Hz signal are produced respectively, and 10 branch frequency counting circuit includes the frequency dividing chip for cascading
With the counting chip of cascade, Big Dipper 1PPS signals respectively divide chip and the MR ends of counting chip provide set signal.
4. power system time synchronized high accuracy IRIG-B code signal according to claim 3 realizes device, its feature
It is that the frequency dividing information source adopts constant-temperature crystal oscillator.
5. power system time synchronized high accuracy IRIG-B code signal according to claim 1 realizes device, its feature
Be that IRIG-B codes composition cell is generated and code element synthesis output circuit include cell generative circuit, data selector and
Data latches, cell generative circuit outfan are connected to data selector input, and data selector control end is exported by MCU
P17 control lines, 1Hz signals and 10Hz signal co- controllings, the one of the outfan connection data latches of data selector is defeated
Enter end, through the IRIG-B time encodings that the outfan output of data latches is accurately complete.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621057824.3U CN206100006U (en) | 2016-09-14 | 2016-09-14 | Electric power system is high accuracy IRIG for time lock device is realized to B code signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621057824.3U CN206100006U (en) | 2016-09-14 | 2016-09-14 | Electric power system is high accuracy IRIG for time lock device is realized to B code signal |
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| Publication Number | Publication Date |
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| CN206100006U true CN206100006U (en) | 2017-04-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201621057824.3U Expired - Fee Related CN206100006U (en) | 2016-09-14 | 2016-09-14 | Electric power system is high accuracy IRIG for time lock device is realized to B code signal |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112881977A (en) * | 2021-01-13 | 2021-06-01 | 南京鼎臻智能电气有限公司 | High-precision self-calibration clock synchronization method based on Beidou or GPS |
| CN114138055A (en) * | 2021-12-08 | 2022-03-04 | 成都引众数字设备有限公司 | Method and device for converting direct current B code into power system serial port time message |
| CN114553357A (en) * | 2022-02-25 | 2022-05-27 | 南京贝龙通信科技有限公司 | Multimode synchronous clock server and frequency compensation method |
| CN112881977B (en) * | 2021-01-13 | 2024-05-17 | 南京鼎臻智能电气有限公司 | High-precision self-calibration clock synchronization method based on Beidou or GPS |
-
2016
- 2016-09-14 CN CN201621057824.3U patent/CN206100006U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112881977A (en) * | 2021-01-13 | 2021-06-01 | 南京鼎臻智能电气有限公司 | High-precision self-calibration clock synchronization method based on Beidou or GPS |
| CN112881977B (en) * | 2021-01-13 | 2024-05-17 | 南京鼎臻智能电气有限公司 | High-precision self-calibration clock synchronization method based on Beidou or GPS |
| CN114138055A (en) * | 2021-12-08 | 2022-03-04 | 成都引众数字设备有限公司 | Method and device for converting direct current B code into power system serial port time message |
| CN114138055B (en) * | 2021-12-08 | 2024-03-15 | 成都引众数字设备有限公司 | Method and device for converting direct current B code into serial port time message of power system |
| CN114553357A (en) * | 2022-02-25 | 2022-05-27 | 南京贝龙通信科技有限公司 | Multimode synchronous clock server and frequency compensation method |
| CN114553357B (en) * | 2022-02-25 | 2023-01-31 | 南京贝龙通信科技有限公司 | Multimode synchronous clock server and frequency compensation method |
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