CN114553202A - Driving circuit and chip for power semiconductor switch device - Google Patents

Driving circuit and chip for power semiconductor switch device Download PDF

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Publication number
CN114553202A
CN114553202A CN202011356313.2A CN202011356313A CN114553202A CN 114553202 A CN114553202 A CN 114553202A CN 202011356313 A CN202011356313 A CN 202011356313A CN 114553202 A CN114553202 A CN 114553202A
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China
Prior art keywords
switch
node
control
voltage
inverter
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CN202011356313.2A
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Chinese (zh)
Inventor
刘利书
刘海清
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Midea Group Co Ltd
Guangdong Midea White Goods Technology Innovation Center Co Ltd
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Midea Group Co Ltd
Guangdong Midea White Goods Technology Innovation Center Co Ltd
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Priority to CN202011356313.2A priority Critical patent/CN114553202A/en
Publication of CN114553202A publication Critical patent/CN114553202A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The application discloses drive circuit and chip for power semiconductor switching device, wherein power semiconductor switching device includes first power switching device and the second power switching device that sets up between operating voltage and reference voltage, and the first node between first power switching device and the second power switching device is used for connecting the load, and this drive circuit includes: the driving unit is used for generating a driving signal at the output end of the driving circuit, the output end of the driving unit is used for being connected with the control end of the first power switching device, and the driving unit comprises a first leakage branch and a second leakage branch which are connected in parallel; the detection unit is used for detecting the voltage of the first node and controlling the conduction or the disconnection of the second leakage branch circuit according to the voltage of the first node, so that the leakage speed of the driving signal is controlled. According to the method and the device, when the detection unit detects that the voltage of the first node is abnormal, the second leakage branch is controlled to be disconnected, and the leakage speed of the driving signal is reduced.

Description

Driving circuit and chip for power semiconductor switch device
Technical Field
The present invention relates to the field of high voltage driving switch devices, and more particularly, to a driving circuit and a chip for a power semiconductor switch device.
Background
The bus voltage of an application working system of the high-voltage grid driving chip is very high and can reach hundreds of volts or even thousands of volts. In a system in which a power device is used as a switching device, especially in the case of very fast switching frequency, a severe electrical stress may be generated due to a change of high-amplitude voltage or current in a short time, for example, a rapid change of a sink current may cause a severe VS negative voltage impact, which may induce a latch-up of a driving tube.
Disclosure of Invention
The application at least provides a driving circuit and a chip for a power semiconductor switching device.
A first aspect of the present application provides a driving circuit for a power semiconductor switching device, wherein the power semiconductor switching device comprises a first power switching device and a second power switching device arranged between an operating voltage and a reference voltage, a first node between the first power switching device and the second power switching device is used for connecting a load, the driving circuit comprising:
the driving unit is used for generating a driving signal at the output end of the driving circuit, wherein the output end is used for being connected with the control end of the first power switching device, and the driving unit comprises a first leakage branch and a second leakage branch which are connected in parallel;
and the detection unit is used for detecting the voltage of the first node and controlling the conduction or the disconnection of the second leakage branch circuit according to the voltage of the first node, so that the leakage speed of the driving signal is controlled.
A second aspect of the present application provides a chip comprising a driving circuit as described above.
The beneficial effect of this application is: different from the prior art, the voltage of the first node is detected through the detection unit, and when the voltage of the first node is detected to be abnormal, the second leakage branch is controlled to be disconnected, so that the leakage speed of the driving signal is reduced, and the latch effect caused by the fact that the leakage speed of the driving signal is too high is prevented.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a high voltage gate driving switch circuit in the prior art;
FIG. 2 is a schematic structural diagram of an embodiment of a driving circuit of the present application;
FIG. 3 is a schematic diagram of the detecting unit shown in FIG. 2;
FIG. 4 is a schematic diagram of the first inverter group of FIG. 2;
FIG. 5 is a schematic diagram of the structure of the second inverter group of FIG. 2;
fig. 6 is a schematic structural diagram of an embodiment of a chip according to the present application.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present application, the driving circuit and the chip provided in the present application are described in further detail below with reference to the accompanying drawings and the detailed description. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second", etc. in this application are used to distinguish between different objects and not to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a high voltage gate driving switch circuit in the prior art. As shown in fig. 1, the high voltage gate driving switch circuit includes a gate driving circuit and an operating circuit.
The input end IN of the grid driving circuit inputs a control signal, and the control signal is transmitted to the control ends of the PMOS tube and the NMOS tube through the multistage phase inverter, namely to the grids of the PMOS tube and the NMOS tube, so as to control the conduction and the disconnection of the PMOS tube and the NMOS tube. The source electrode of the PMOS tube receives the working voltage VB, the drain electrode of the PMOS tube is connected with the drain electrode of the NMOS tube, and a signal output end HO is formed between the drain electrode of the NMOS tube and the drain electrode of the PMOS tube.
The working circuit comprises a first power switch device Q1, a second power switch device Q2 and a load Lload. A control terminal of the first power switch device Q1 is connected to the signal output terminal HO for receiving a control signal, a first path terminal of the first power switch device Q1 receives the bus voltage VP, a second path terminal of the first power switch device Q1 is connected to a first path terminal of the second power switch device Q2, and a second path terminal of the second power switch device Q2 is connected to the ground voltage VCOM. Wherein a node VS is formed between the second path terminal of the first power switch device Q1 and the first path terminal of the second power switch device Q2 for connecting the load Lload。
In this embodiment, the first power switch device Q1 and the second power switch device Q2 are both IGBTs (Insulated Gate Bipolar transistors), and the control end, the first pass end, and the second pass end of the first power switch device Q1 and the second power switch device Q2 are respectively a Gate, a collector, and an emitter of the IGBT.
In other embodiments, the first power switch device Q1 and the second power switch device Q2 may be power devices such as power MOS transistors or IGCTs (Integrated Gate Commutated thyristors).
When the first power switch device Q1 and the second power switch device Q2 are power MOS transistors, the control ends, the first path ends, and the second path ends of the first power switch device Q1 and the second power switch device Q2 are respectively a gate, a source, and a drain of a PMOS transistor; or, the control terminals, the first pass terminal and the second pass terminal of the first power switch Q1 and the second power switch Q2 are the gate, the drain and the source of the NMOS transistor, respectively.
When the grid of the PMOS tube receives a high-level control signal and the grid of the NMOS tube receives a low-level control signal, the PMOS tube is switched on and the NMOS tube is switched off. The working voltage VB is output to the first power switch device Q1 through the PMOS transistor, that is, the control end of the first power switch device Q1 receives the control signal output by the signal output end HO as a high level signal, the first power switch device Q1 is turned on, the bus voltage VP generates the working current through the first power switch device Q1 and flows to the load LloadAt this time, the flow of the working current is that the bus voltage VP flows to the parasitic inductor L1 of the first power switch device Q1, and then flows to the load Lload。
When the grid of the PMOS tube receives a low-level control signal, the grid of the NMOS tube receives a high-level control signal, the NMOS tube is switched on, and the PMOS tube is switched off. At this time, the control end of the first power switch device Q1 receives that the control signal output by the signal output end HO is a low level signal, the first power switch device Q1 is turned off, the gate charge of the first power switch device Q1 is released through the NMOS transistor, that is, the signal output end HO generates a sink current.
Due to the load LloadIs large inductance and flows through the load LloadCannot abruptly change and therefore freewheel through diode D2 of the second power switch Q2. At this time, the operating current flows to the ground voltage VCOM, flows to the parasitic inductor L2 of the second power switch Q2, and then flows to the load Lload. The parasitic inductor L2 generates an induced electromotive force by the operating current, so that the potential at the VS point is lower than the ground voltage VCOM, i.e., the VS point generates a negative voltage.
When the turn-off frequency of the first power switch device Q1 is faster, the sink current generated at the signal output terminal HO changes faster, and the larger the current value of the sink current, the higher the probability of latch-up.
In order to solve the problems that severe VS negative pressure impact is caused by rapid change of the sink current and latch-up effect of a driving tube is induced in the prior art, the application provides a driving circuit for a power semiconductor switching device. Referring to fig. 2-5, fig. 2 is a schematic structural diagram of an embodiment of a driving circuit of the present application; FIG. 3 is a schematic diagram of the detecting unit shown in FIG. 2; FIG. 4 is a schematic diagram of the first inverter group of FIG. 2; fig. 5 is a schematic diagram of the structure of the second inverter group in fig. 2.
As shown in fig. 2, the driving circuit 1 includes a driving unit 11 and a detecting unit 12, and the driving circuit 1 is connected to the working circuit 2 and drives the working circuit 2 to work. The working circuit 2 is the working circuit described in fig. 1, and is not described herein again. A first node a is formed between the first power switch Q1 and the second power switch Q2 for connecting a load LloadAnd a detection unit 12.
The driving unit 11 is connected between the first operating voltage VB and the second operating voltage VS', and is configured to receive a control signal input from an input terminal IN of the driving circuit 1, and generate a driving signal HO at an output terminal of the driving circuit 1, where the output terminal of the driving circuit 1 is connected to a control terminal of the first power switching device Q1. Alternatively, in other embodiments, the second operating voltage may be a reference ground voltage VCOM.
The drive unit 11 comprises a first bleeder branch 111, a second bleeder branch 112, a pull-up circuit 113, a first inverter group 114 and a second inverter group 115, wherein the first bleeder branch 111 is arranged in parallel with the second bleeder branch 112.
The first bleeder branch 111 comprises a first semiconductor device 1111 coupled between the output terminal of the driver circuit 1 and the second operating voltage VS ', a control terminal of the first semiconductor device 1111 is coupled to the input terminal IN of the driver circuit 1, a first pass terminal of the first semiconductor device 1111 is coupled to the output terminal of the driver circuit 1, and a second pass terminal of the first semiconductor device 1111 is coupled to the second operating voltage VS'. Specifically, the first semiconductor device 1111 is an NMOS transistor, and the control terminal, the first path terminal, and the second path terminal of the first semiconductor device 1111 are a gate, a drain, and a source of the NMOS transistor, respectively.
The second leakage branch 112 includes a first switch 1121 and a second semiconductor device 1122 connected in series between the output terminal of the driving circuit 1 and a second operating voltage VS', wherein a control terminal of the first switch 1121 is connected to the detecting unit 12 to be turned on or off according to the first node voltage VS of the first node a detected by the detecting unit 12, so as to control the second leakage branch 112 to be turned on or off.
Specifically, a first path terminal of the first switch 1121 is connected to the output terminal of the driving circuit 1, a second path terminal of the first switch 1121 is connected to a first path terminal of the second semiconductor device 1122, a second path terminal of the second semiconductor device 1122 is connected to the second operating voltage VS', and a control terminal of the second semiconductor device 1122 is connected to the input terminal IN of the driving circuit 1. The first switch 1121 and the second semiconductor device 1122 are both NMOS transistors, and the control end, the first pass end and the second pass end of the first switch 1121 and the second semiconductor device 1122 are respectively a gate, a drain and a source of the NMOS transistor.
The pull-up circuit 113 includes a third semiconductor device 1131, and the third semiconductor device 1131 is connected between the output terminal of the driving circuit 1 and the first operating voltage VB to pull up the driving signal, so that the first power switch device Q1 receives a high-level signal.
A control terminal of the third semiconductor device 1131 is connected to the input terminal IN of the driving circuit 1, a first path terminal of the third semiconductor device 1131 is connected to the first operating voltage VB, and a second path terminal of the third semiconductor device 1131 is connected to the output terminal of the driving circuit 1. Specifically, the third semiconductor device 1131 is a PMOS transistor, and the control terminal, the first pass terminal and the second pass terminal of the third semiconductor device 1131 are a gate, a source and a drain of the PMOS transistor, respectively.
The first inverter group 114 is connected between the first operating voltage VB and the second operating voltage VS', and between the pull-up circuit 113 and the input terminal IN of the driving circuit 1, and is configured to output a third control signal to the third semiconductor device 1131 to control the third semiconductor device 1131 to be turned on or off, so as to control the pull-up circuit 113 to be turned on or off.
Specifically, as shown in fig. 4, the first inverter group 114 includes a first inverter 1141, a second inverter 1142, and a third inverter 1143.
A first end of the first inverter 1141 is connected to the input terminal IN of the driving circuit 1, a second end is connected to the first voltage VB, a third end is connected to the second voltage VS', and a fourth end is connected to the first end of the second inverter 1142; a second end of the second inverter 1142 is connected to the first voltage VB, a third end is connected to the second voltage VS', and a fourth end is connected to the first end of the third inverter 1143; the third inverter 1143 has a second terminal connected to the first voltage VB, a third terminal connected to the second voltage VS', a fourth terminal connected to the control terminal of the third semiconductor device 1131, and outputs a third control signal to the third semiconductor device 1131 to control the third semiconductor device 1131 to turn on or off. The first end and the fourth end of the first inverter 1141, the second inverter 1142 and the third inverter 1143 are the signal input end and the signal output end of the first inverter 1141, the second inverter 1142 and the third inverter 1143, respectively.
The first phase inverter 1141, the second phase inverter 1142 and the third phase inverter 1143 are composed of a PMOS transistor and an NMOS transistor connected in series, and the second end and the third end of the first phase inverter 1141, the second phase inverter 1142 and the third phase inverter 1143 are the source electrode of the PMOS transistor and the source electrode of the NMOS transistor respectively.
The second inverter group 115 is connected between the first operating voltage VB and the second operating voltage VS', and between the first bleeder branch 111 and the second bleeder branch 112 and the input terminal IN of the driving circuit 1, and is configured to output a fourth control signal to the first semiconductor device 1111 and the second semiconductor device 1122 to control the first semiconductor device 1111 and the second semiconductor device 1122 to be turned on or off, so as to control the first bleeder branch 111 and the second bleeder branch 112 to be turned on or off.
Specifically, as shown in fig. 5, the second inverter group 115 includes a fourth inverter 1151, a fifth inverter 1152, a sixth inverter 1153, and a third resistor 1154.
A first end of the fourth inverter 1151 is connected to the input terminal IN of the driving circuit 1, a second end is connected to the first voltage VB, a third end is connected to the second voltage VS', and a fourth end is connected to the first end of the fifth inverter 1152; a second terminal of the fifth inverter 1152 is connected to the first voltage VB, a third terminal is connected to the second voltage VS', and a fourth terminal is connected to the first terminal of the sixth inverter 1153; the sixth inverter 1153 has a second terminal connected to the first voltage VB, a third terminal connected to the second voltage VS', and a fourth terminal connected to the control terminals of the first semiconductor device 1111 and the second semiconductor device 1122. First and fourth ends of the fourth, fifth and sixth inverters 1151, 1152 and 1153 are signal input ends and output ends of the fourth, fifth and sixth inverters 1151, 1152 and 1153, respectively.
One end of the third resistor 1154 is connected to the first voltage VB, and the other end of the third resistor 1154 is connected to the fourth end of the sixth inverter 1153 and a sixth node f formed between the first semiconductor device 1111 and the control terminal of the second semiconductor device 1122. Here, the sixth node f is configured to output a fourth control signal to the first semiconductor device 1111 and the second semiconductor device 1122 to control on or off of the first semiconductor device 1111 and the second semiconductor device 1122.
The fourth inverter 1151, the fifth inverter 1152 and the sixth inverter 1153 are respectively composed of a PMOS transistor and an NMOS transistor which are connected in series, and the second end and the third end of the fourth inverter 1151, the fifth inverter 1152 and the sixth inverter 1153 are respectively a source electrode of the PMOS transistor and a source electrode of the NMOS transistor.
The detecting unit 12 includes a comparing and clamping circuit 121 and a control signal generating circuit 122. The detecting unit 12 is preset with a floating ground, and the floating ground voltage is VS'.
The comparison clamp circuit 121 connects the first node a and the floating ground to receive the first node voltage VS and the floating ground voltage VS ', and generates a first control signal according to the first node voltage VS and the floating ground voltage VS'.
The control signal generating circuit 122 is connected to the comparing and clamping circuit 121, and is configured to generate a second control signal according to the first control signal, and output the second control signal to the first switch 1121 to control the first switch 1121 to be turned on or off, and further control the second bleeding branch 112 to be turned on or off.
As shown in fig. 3, the comparison clamping circuit 121 includes a first resistor 1211, a second switch 1212, a third switch 1213, and a diode 1214.
Specifically, one end of the first resistor 1211 is connected to the first operating voltage VB, the other end of the first resistor 1211 is connected to the first path terminal of the second switch 1212, and the second path terminal of the second switch 1212 is connected to the first node a; a first path end of the third switch 1213 is connected to the floating ground, and a second path end of the third switch 1213 is connected to the first node a; wherein a control terminal of the second switch 1212 and a control terminal of the third switch 1213 are connected together and to a second node b between the first resistor 1211 and the first path terminal of the second switch 1212. The anode of the diode 1214 is connected to the first node a, and the cathode of the diode 1214 is connected to the floating ground.
The first resistor 1211, the second switch 1212 and the third switch 1213 form a bias circuit for pressurizing the third switch 1213, so that the third switch 1213 operates normally.
A parasitic PNP tube 1215 is formed between the first operating voltage VB and the floating ground, the base of the parasitic PNP tube 1215 is connected to the first operating voltage VB, the emitter of the parasitic PNP tube 1215 is connected to the floating ground, and the collector of the parasitic PNP tube 1215 is connected to the first pass terminal of the third switch 1213 and the cathode of the diode 1214.
Optionally, the second switch 1212 and the third switch 1213 are both NMOS transistors, and the control terminals, the first path terminal and the second path terminal of the second switch 1212 and the third switch 1213 are the gate, the drain and the source of the NMOS transistor, respectively.
The control signal generating circuit 122 includes a fourth switch 1221, a fifth switch 1222, a sixth switch 1223, a seventh switch 1224, a second resistor 1225, and an eighth switch 1226.
Specifically, a first path end of the fourth switch 1221 is connected to the first operating voltage VB, and a control end of the fourth switch 1221 is connected to a second path end of the fourth switch 1221; a first path terminal of the fifth switch 1222 is connected to a second path terminal of the fourth switch 1221, a second path terminal of the fifth switch 1222 is connected to the first node a, and a control terminal of the fifth switch 1222 is connected to the floating ground. Among them, the diode 1214 is a clamp diode for maintaining a voltage difference value between the control terminal of the fifth switch 1222 and the second path terminal to be 5V or 7V.
A first path terminal of the sixth switch 1223 is connected to the first operating voltage VB, wherein a control terminal of the sixth switch 1223 and a control terminal of the fourth switch 1221 are connected together and to a third node c between a second path terminal of the fourth switch 1221 and the first path terminal of the fifth switch 1222; a first path terminal of the seventh switch 1224 is connected to the second path terminal of the sixth switch 1223, a second path terminal of the seventh switch 1224 is connected to the first node a, and a control terminal of the seventh switch 1224 is connected to the first path terminal of the seventh switch 1224.
One end of the second resistor 1225 is connected to the first operating voltage VB; a first path terminal of the eighth switch 1226 is connected to the other terminal of the second resistor 1225, a second path terminal of the eighth switch 1226 is connected to the first node a, wherein a control terminal of the eighth switch 1226 and a control terminal of the seventh switch 1224 are connected together and to a fourth node d between the first path terminal of the seventh switch 1224 and the second path terminal of the sixth switch 1223.
Optionally, the fourth switch 1221 and the sixth switch 1223 are both PMOS transistors, and the control end, the first path end, and the second path end of the fourth switch 1221 and the sixth switch 1223 are the gate, the source, and the floor of the PMOS transistor, respectively. The fifth switch 1222, the seventh switch 1224, and the eighth switch 1226 are all NMOS transistors, and the control end, the first pass end, and the second pass end of the fifth switch 1222, the seventh switch 1224, and the eighth switch 1226 are the gate, the drain, and the source of the NMOS transistor, respectively.
The second resistor 1225 and a first path of the eighth switch 1226 form a fifth node e, which is used to output a second control signal to the first switch 1121 to control the on/off of the first switch 1121.
When the first node voltage VS of the first node a is normal, the first node voltage VS is equal to the floating ground voltage VS', the control terminal of the fifth switch 1222 receives the first control signal and is at a low level, that is, the fifth switch 1222 is not turned on, at this time, the fourth switch 1221, the fifth switch 1222, the sixth switch 1223, the seventh switch 1224, and the eighth switch 1226 are not turned on, and the second control signal output by the fifth node e is the first voltage VB. Since the first voltage VB is at a high level, the first switch 1121 is turned on, and the gate charge of the first power switch Q1 releases the sink current generated at the signal output terminal HO through the NMOS transistor, so that the sink current flows through the first drain branch 111 and the second drain branch 112.
When the first node voltage VS at the first node a is abnormal, i.e. the first node voltage VS rapidly decreases to a negative voltage, a voltage difference is formed between the control terminal of the fifth switch 1222 and the second path terminal, i.e. the control terminal of the fifth switch 1222 receives the first control signal as high level, and the fifth switch 1222 is turned on to generate a current. Since the fourth switch 1221, the fifth switch 1222, the sixth switch 1223, the seventh switch 1224, the second resistor 1125, and the eighth switch 1226 form a mirror circuit, the fourth switch 1221, the fifth switch 1222, the sixth switch 1223, the seventh switch 1224, and the eighth switch 1226 are all turned on, and at this time, the second control signal output by the fifth node e is the first node voltage VS. Since the first node voltage VS is a negative voltage, i.e., a low level signal, the first switch 1121 is turned off, so that the second current leakage branch 112 is turned off, and the gate charge of the first power switch device Q1 is released through the NMOS transistor, so that the sink current generated at the signal output terminal HO can only be drained through the first current leakage branch 111, which reduces the current leakage rate compared with the normal first node voltage VS.
The first node voltage VS of the first node a is detected by the detecting unit 12, and when the first node voltage VS is detected to be abnormal, the second leakage branch 112 is controlled to be disconnected, so that the leakage speed of the driving signal, that is, the leakage rate of the sink current, is reduced, and the latch-up effect caused by the excessively high leakage speed of the driving signal is effectively prevented.
Fig. 6 is a schematic view of a chip 6 according to an embodiment of the present application. The chip 6 includes a driving circuit 61, and the driving circuit 61 is the driving circuit 1 disclosed in the above embodiments and is not described herein again.
The above are only examples of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent processes performed by the present application and the contents of the attached drawings, which are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims (10)

1. A driver circuit for a power semiconductor switching device, wherein the power semiconductor switching device comprises a first power switching device and a second power switching device arranged between an operating voltage and a reference voltage, and a first node between the first power switching device and the second power switching device is used for connecting a load, the driver circuit comprising:
the driving unit is used for generating a driving signal at an output end of the driving circuit, wherein the output end is used for being connected with a control end of the first power switching device, and the driving unit comprises a first leakage branch and a second leakage branch which are connected in parallel;
and the detection unit is used for detecting the voltage of the first node and controlling the conduction or the disconnection of the second leakage branch circuit according to the voltage of the first node, so that the leakage speed of the driving signal is controlled.
2. The driving circuit according to claim 1, wherein the driving unit is connected between a first operating voltage and a second operating voltage;
the first bleeder branch comprises a first semiconductor device connected between the output terminal and the second operating voltage;
the second leakage branch comprises a first switch and a second semiconductor device which are connected between the output end and the second working voltage in series, wherein the control end of the first switch is connected with the detection unit to be switched on or off according to the first node voltage detected by the detection unit, so that the second leakage branch is controlled to be switched on or off.
3. The driving circuit of claim 2, wherein the detecting unit is preset to a floating ground, comprising:
a comparison clamp circuit connected to the first node and the floating ground to receive the first node voltage and a floating ground voltage and generate a first control signal according to the first node voltage and the floating ground voltage;
and the control signal generating circuit is connected with the comparison clamping circuit to generate a second control signal according to the first control signal and output the second control signal to the first switch to control the first switch to be switched on or switched off.
4. The driver circuit of claim 3, wherein the comparison clamp circuit comprises:
one end of the first resistor is connected with the first working voltage;
a second switch, a first path end of which is connected with the other end of the first resistor, and a second path end of which is connected with the first node;
a third switch having a first path terminal connected to the floating ground and a second path terminal connected to the first node, wherein a control terminal of the second switch and a control terminal of the third switch are connected together and to a second node between the first resistor and the first path terminal of the second switch;
and the anode of the diode is connected with the first node, and the cathode of the diode is connected with the floating ground.
5. The driving circuit according to claim 3, wherein the control signal generating circuit comprises:
a fourth switch, a first path end of which is connected with the first working voltage, and a control end of which is connected with a second path end of which;
a fifth switch, a first path end of which is connected with a second path end of the fourth switch, a second path end of which is connected with the first node, and a control end of which is connected with the floating ground;
a sixth switch having a first path terminal connected to the first operating voltage, wherein a control terminal of the sixth switch and a control terminal of the fourth switch are connected together and to a third node between a second path terminal of the fourth switch and the first path terminal of the fifth switch;
a seventh switch, a first path end of which is connected to the second path end of the sixth switch, a second path end of which is connected to the first node, and a control end of which is connected to the first path end;
one end of the second resistor is connected with the first working voltage;
an eighth switch, a first path end of which is connected to the other end of the second resistor, and a second path end of which is connected to the first node, wherein a control end of the eighth switch and a control end of the seventh switch are connected together and to a fourth node between the first path end of the seventh switch and the second path end of the sixth switch;
a fifth node is formed between the second resistor and the first path end of the eighth switch, and is used for outputting the second control signal to the first switch to control the on or off of the first switch.
6. The drive circuit according to claim 2, wherein the drive unit further comprises:
a pull-up circuit including a third semiconductor device connected between the output terminal and the first operating voltage to pull up the driving signal.
7. The drive circuit according to claim 6, wherein the drive unit further comprises:
a first inverter group connected between the first operating voltage and the second operating voltage for outputting a third control signal to the third semiconductor device to control the third semiconductor device to be turned on or off, thereby controlling the pull-up circuit to be turned on or off;
and the second inverter group is connected between the first working voltage and the second working voltage and used for outputting a fourth control signal to the first semiconductor device and the second semiconductor device so as to control the conduction or the disconnection of the first semiconductor device and the second semiconductor device and further control the conduction or the disconnection of the first leakage branch and the second leakage branch.
8. The drive circuit according to claim 7, wherein the first inverter group comprises:
the input end of the first inverter is connected with the input end of the driving circuit;
the input end of the second inverter is connected with the output end of the first inverter;
and the input end of the third inverter is connected with the output end of the second inverter, the output end of the third inverter is connected with the control end of the third semiconductor device, and the third inverter outputs the third control signal to the third semiconductor device so as to control the third semiconductor device to be switched on or switched off.
9. The drive circuit according to claim 7, wherein the second inverter group comprises:
the input end of the fourth inverter is connected with the input end of the driving circuit;
the input end of the fifth inverter is connected with the output end of the fourth inverter;
a sixth inverter, an input terminal of which is connected to an output terminal of the fifth inverter, and an output terminal of which is connected to control terminals of the first semiconductor device and the second semiconductor device;
a third resistor having one end connected to the first voltage and the other end connected to a sixth node formed between an output end of the sixth inverter and the control ends of the first and second semiconductor devices;
wherein the sixth node is configured to output the fourth control signal to the first semiconductor device and the second semiconductor device to control on or off of the first semiconductor device and the second semiconductor device.
10. A chip comprising a driver circuit as claimed in any one of claims 1 to 9.
CN202011356313.2A 2020-11-26 2020-11-26 Driving circuit and chip for power semiconductor switch device Pending CN114553202A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011356313.2A CN114553202A (en) 2020-11-26 2020-11-26 Driving circuit and chip for power semiconductor switch device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011356313.2A CN114553202A (en) 2020-11-26 2020-11-26 Driving circuit and chip for power semiconductor switch device

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CN114553202A true CN114553202A (en) 2022-05-27

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CN202011356313.2A Pending CN114553202A (en) 2020-11-26 2020-11-26 Driving circuit and chip for power semiconductor switch device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117434340A (en) * 2023-12-21 2024-01-23 芯耀辉科技有限公司 Voltage detection circuit and chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117434340A (en) * 2023-12-21 2024-01-23 芯耀辉科技有限公司 Voltage detection circuit and chip
CN117434340B (en) * 2023-12-21 2024-04-23 芯耀辉科技有限公司 Voltage detection circuit and chip

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