CN114552375A

CN114552375A - Vertical cavity surface emitting laser array

Info

Publication number: CN114552375A
Application number: CN202210192186.XA
Authority: CN
Inventors: 梁栋; 刘嵩; 张�成; 翁玮呈
Original assignee: Vertilite Co Ltd
Current assignee: Vertilite Co Ltd
Priority date: 2022-02-28
Filing date: 2022-02-28
Publication date: 2022-05-27

Abstract

The invention provides a vertical cavity surface emitting laser array, comprising: a substrate; a plurality of vertical cavity surface emitting laser sub-arrays formed on the substrate, each vertical cavity surface emitting laser sub-array including a plurality of light emitting cells; a plurality of first electrodes formed at one side of the plurality of light emitting cells; a plurality of second electrodes formed on one side of the light emitting unit away from the first electrodes; when at least one first electrode and at least one second electrode are electrified, the plurality of light-emitting units controlled by the overlapping area of the projection areas of the first electrode and the second electrode in the light emitting direction are lightened. The vertical cavity surface emitting laser array provided by the invention realizes the partition control of the vertical cavity surface emitting laser array.

Description

Vertical cavity surface emitting laser array

Technical Field

The invention relates to the technical field of semiconductor lasers, in particular to a vertical cavity surface emitting laser array.

Background

A Vertical Cavity Surface Emitting Laser (VCSEL) is developed based on semiconductor materials such as gallium arsenide, and is different from semiconductor devices of other light sources such as light emitting diodes and laser diodes. The array has the advantages of small volume, circular output light spots, single longitudinal mode output, small threshold current, low price, easy integration into a large-area array and the like, and is widely applied to the fields of optical communication, optical interconnection, optical storage and the like. However, the back surface of a typical VCSEL array is a common cathode. In some application scenarios where the light source needs to be lighted in different regions, the conventional vertical cavity surface emitting laser array cannot meet the requirements. Therefore, how to implement the regional control of the light source has become an urgent problem to be solved.

Disclosure of Invention

In view of the above-mentioned deficiencies of the prior art, the present application provides a vertical cavity surface emitting laser array, which implements a partitioned control of the vertical cavity surface emitting laser array.

To achieve the above and other objects, the present application provides a vertical cavity surface emitting laser array comprising:

a substrate;

a plurality of vertical cavity surface emitting laser sub-arrays formed on the substrate, each of the vertical cavity surface emitting laser sub-arrays including a plurality of light emitting cells;

a plurality of first electrodes formed at one side of the plurality of light emitting cells;

a plurality of second electrodes formed on one side of the light emitting unit away from the first electrodes;

when at least one first electrode and at least one second electrode are electrified, the plurality of light-emitting units controlled by the overlapping area of the projection areas of the first electrode and the second electrode in the light emitting direction are lightened.

Optionally, an epitaxial layer formed on the upper surface of the substrate, the plurality of sub-arrays of vertical cavity surface emitting lasers being formed on the epitaxial layer;

the second ohmic metal layer is positioned on the epitaxial layer;

the first insulating layer is positioned on the epitaxial layer;

the second electrode is positioned on the second insulating layer and is electrically connected with the light-emitting unit through the second ohmic metal layer;

a first ohmic metal layer located in the groove of the substrate;

and the first electrode is positioned on the first ohmic metal layer and is electrically connected with the epitaxial layer through the first ohmic metal layer.

Optionally, the epitaxial layer includes a first ohmic contact layer, the first ohmic contact layer is located on the upper surface of the substrate, and the first ohmic metal layer is in ohmic contact with the first ohmic contact layer.

Optionally, the epitaxial layer further comprises a first reflective layer, an active layer and a second reflective layer, and the sum of the thicknesses of the active layer and the second reflective layer is in a range of 8-10 micrometers.

Optionally, the epitaxial layer includes a second ohmic contact layer on the second reflective layer, and the second ohmic metal layer is in ohmic contact with the second ohmic contact layer.

Optionally, the light emitting unit forms a plurality of light emitting unit arrays, the plurality of light emitting unit arrays have an isolation structure therebetween, and the plurality of light emitting units have a first trench therebetween.

Optionally, the isolation structure includes a second trench and/or an ion implantation layer, and the second trench is etched to the surface of the substrate or the ion implantation layer is implanted to the surface of the substrate to isolate adjacent light emitting cell arrays.

Optionally, the first insulating layer covers the second ohmic contact layer and the upper surface and the side surfaces of the second ohmic metal layer.

Optionally, the second insulating layer covers the first insulating layer, the sidewalls and the bottom surface of the first trench, and the sidewalls and the bottom surface of the second trench.

Optionally, the etching depth of the second trench is greater than the etching depth of the first trench.

In summary, the present application provides a vertical cavity surface emitting laser array, in which a second electrode arranged to intersect with a first electrode is disposed on a back surface of a substrate as a cathode, so as to improve a manufacturing process of the vertical cavity surface emitting laser array and achieve regional control of a light source.

Drawings

FIG. 1 is a schematic diagram of an VCSEL array structure according to an embodiment of the present application;

FIG. 2 is a schematic view of a VCSEL array photoresist layer according to an embodiment of the present application;

FIG. 3 is a schematic illustration of a second ohmic metal layer deposition for an VCSEL array in one embodiment of the present application;

FIG. 4 is a diagram illustrating an exemplary second ohmic metal layer patterned for a VCSEL array according to an embodiment of the present invention;

FIG. 5 is a top view of a second ohmic metal layer of an VCSEL array in an embodiment of the present application;

FIG. 6 is a schematic view of a first insulating layer of an VCSEL array in an embodiment of the present application;

FIG. 7 is a schematic diagram illustrating a first trench etch structure of an VCSEL array in an embodiment of the present application;

FIG. 8 is a schematic view of a VCSEL array current confinement layer in an embodiment of the present application;

FIG. 9 is a schematic view of an embodiment of a VCSEL array covered by a second insulating layer;

FIG. 10 is a schematic view of an embodiment of a VCSEL array formed with a first opening;

FIG. 11 is a schematic diagram of a second electrode structure of an VCSEL array in an embodiment of the present application;

FIG. 12 is a bottom etch schematic view of a VCSEL array substrate in an embodiment of the present application;

FIG. 13 is a schematic illustration of an etched barrier layer of an VCSEL array in an embodiment of the present application;

FIG. 14 is a schematic view of a first ohmic metal layer of an VCSEL array in an embodiment of the present application;

FIG. 15 is a schematic view of a second opening of an VCSEL array in an embodiment of the present application;

FIG. 16 is a first electrode of an VCSEL array in an embodiment of the present application;

FIG. 17 is a second schematic diagram of a first electrode of an VCSEL array in an embodiment of the present application;

FIG. 18 is a top view of an VCSEL array in an embodiment of the present application;

FIG. 19 is a first backside view of an VCSEL array in an embodiment of the present application;

FIG. 20 is a schematic view of a sub-array of VCSEL array light emitting cells in an embodiment of the present application;

FIG. 21 is a second backside view of an VCSEL array in an embodiment of the present application;

FIG. 22 is a rear view of a VCSEL array of an embodiment of the present application.

Description of reference numerals:

1, a substrate;

2, an epitaxial layer;

21 a first ohmic contact layer;

22 a first reflective layer;

23 an active layer;

24 a second reflective layer;

25 a second ohmic contact layer;

3, photoresist layer;

4, etching the barrier layer;

5 a second ohmic metal layer;

6 a first insulating layer;

7 a light emitting unit;

70 an array of light emitting cells;

71 a first array of light emitting cells;

72 a second array of light emitting cells;

201 a first trench;

202 a second trench;

26 an oxide layer;

261 a current confinement layer;

262 a light emitting aperture;

8 a second insulating layer;

81 a first opening;

9 a second electrode;

101, a groove;

10 a first ohmic metal layer;

11 a third insulating layer;

111 second openings;

12 a first electrode;

91 a first anode;

92 a second anode;

121 a first cathode;

122 a second cathode;

123 a third cathode;

124 a fourth cathode;

711 a first sub-array of light emitting cells;

712 a second sub-array of light emitting cells;

721 a third light emitting cell sub-array;

722 a fourth light emitting cell sub-array.

Detailed Description

The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

The application provides a vertical cavity surface emitting laser array, which realizes the regional control of a light source by arranging a second electrode parallel to or crossed with a first electrode on the back of a substrate as a cathode.

Referring to fig. 1, in an embodiment of the present invention, the epitaxial layer 2 sequentially includes at least a first reflective layer 22 formed on the first ohmic contact layer 21, an active layer 23 formed on the first reflective layer 22, a second reflective layer 24 formed on the active layer 23, and a second ohmic contact layer 25 formed on the second reflective layer 24, and the inner level of the epitaxial layer 2 is not limited thereto and may be changed according to the actual design. In some examples, the first ohmic contact layer 21 may be located between the active layer 23 and the first reflective layer 22; or the first ohmic contact layer 21 may be positioned between the first reflective layers 22, but the present application is not limited thereto. In the present embodiment, the substrate 1 may be any semi-insulating material suitable for forming a vertical cavity surface emitting laser, and the substrate 1 is, for example, a semi-insulating GaAs substrate which is a GaAs substrate not doped with impurities and has a very high resistance.

Referring to fig. 1 again, in the present embodiment, the first ohmic contact layer 21 may be, for example, a highly doped N-type semiconductor layer to form an ohmic contact with a subsequent ohmic metal layer, such as gallium arsenide (GaAs). The first reflective layer 22 may be formed of, for example, a stack of two materials having different refractive indices, including AlGaAs and GaAs, or AlGaAs of a high aluminum composition and AlGaAs of a low aluminum composition, the first reflective layer 22 may be an N-type mirror, and the first reflective layer 22 may be an N-type bragg mirror. The active layer 23 includes a quantum well composite structure formed by stacking GaAs and AlGaAs, or InGaAs and AlGaAs materials, and the active layer 23 serves to convert electric energy into optical energy. The second reflective layer 24 may include a stack of two materials having different refractive indexes, i.e., AlGaAs and GaAs, or AlGaAs of a high aluminum composition and AlGaAs of a low aluminum composition, the second reflective layer 24 may be a P-type mirror, and the second reflective layer 24 may be a P-type bragg mirror. The first and second reflective layers 22 and 24 serve to enhance reflection of light generated from the active layer 23 and then emit the light from the surface of the second reflective layer 24. The second ohmic contact layer 25 may be, for example, a highly doped P-type semiconductor layer to facilitate ohmic contact with a subsequent ohmic metal layer, such as gallium arsenide (GaAs).

In some embodiments, the first ohmic contact layer 21, the first reflective layer 22, the active layer 23, the second reflective layer 24, and the second ohmic contact layer 25 may be formed, for example, by a chemical vapor deposition method.

In some embodiments, the sum of the thicknesses of the first reflective layer 22, the active layer 23, and the second reflective layer 24 is between 8-10 microns.

In some embodiments, the first reflective layer 22 or the second reflective layer 24 comprises a series of alternating layers of materials of different refractive indices, wherein the effective optical thickness of each alternating layer (the layer thickness times the layer refractive index) is an odd integer multiple of the operating wavelength of the quarter-wavelength VCSEL, i.e., the effective optical thickness of each alternating layer is a quarter of an odd integer multiple of the operating wavelength of the VCSEL. Suitable dielectric materials for forming the alternating layers of the first reflective layer 22 or the second reflective layer 24 include tantalum oxide, titanium oxide, aluminum oxide, titanium nitride, silicon nitride, and the like. Suitable semiconducting materials for forming the alternating layers of the first reflective layer 22 or the second reflective layer 24 include gallium nitride, aluminum nitride, and aluminum gallium nitride, although the invention is not limited in this respect.

In some embodiments, the active layer 23 may include one or more semiconductor layers including one or more quantum well layers or one or more quantum dot layers sandwiched between respective pairs of barrier layers.

Referring to fig. 2-5, in an embodiment of the present application, a plurality of second ohmic metal layers 5 may be formed on the second ohmic contact layer 25 of the epitaxial layer 2. Referring to fig. 2-3, in an embodiment of the present invention, in order to separate the plurality of second ohmic metal layers 5 on the epitaxial layer 2, a photoresist layer 3 may be disposed on the surface of the second ohmic contact layer 25, and the photoresist layer 3 completely covers the upper surface of the second ohmic contact layer 25. In an embodiment of the present disclosure, the photoresist is uniformly coated on the upper surface of the second ohmic contact layer 25, and the pattern on the mask is transferred to the photoresist by the processes of developing and removing the photoresist, so as to form a geometric pattern completely corresponding to the mask. In this embodiment, the geometric figure corresponding to the mask may be a ring. After the photoresist layer 3 is subjected to the above-mentioned exposure and development processes, a plurality of annular regions are formed on the photoresist layer 3, and the annular regions expose the upper surface of the second ohmic contact layer 25. In one embodiment of the present application, a second ohmic metal layer 5 is deposited on the upper surfaces of the photoresist layer 3 and the second ohmic contact layer 25, and the second ohmic metal layer 5 also covers the annular region of the photoresist layer 3 (i.e., the region where the second ohmic contact layer 25 is exposed).

Referring to fig. 4-5, in an embodiment of the present invention, the photoresist layer 3 and the second ohmic metal layer 5 deposited on the upper surface of the photoresist layer 3 may be removed by using acetone, and at this time, a plurality of annular second ohmic metal layers 5 are formed on the upper surface of the second ohmic contact layer 25. In this embodiment, the shape of the second ohmic metal layer 5 may be, for example, a circular ring shape, and in some embodiments, the shape of the second ohmic metal layer 5 may also be an elliptical ring shape, a rectangular ring shape, a hexagonal ring shape, and the shape of the second ohmic metal layer 5 may be selected as needed. The second ohmic metal layer 5 can be used as a reference for photolithography calibration in subsequent processes, so as to prepare a vertical cavity surface emitting laser with high precision, and the second ohmic metal layer 5 can also be used as a metal contact pad of a subsequent electrode. The material of the second ohmic metal layer 5 may include one or a combination of Au metal, Pt metal, Ge metal, Ti metal, and Ni metal, which may be selected according to the requirement. The second ohmic metal layer 5 may be formed, for example, by a chemical vapor deposition method.

Referring to fig. 6, in an embodiment of the present invention, the first insulating layer 6 may cover the second ohmic contact layer 25, and the first insulating layer 6 may also cover the upper surface and the side surface of the second ohmic metal layer 5. The material of the first insulating layer 6 may be silicon nitride or silicon oxide or other insulating materials, wherein the thickness of the first insulating layer 6 may be in the range of, for example, 100-300 nm. In the present embodiment, the first insulating layer 6 may be formed, for example, by chemical vapor deposition.

Referring to fig. 7, in an embodiment of the present invention, a portion of the first insulating layer 6 and the epitaxial layer 2 is first etched to form a plurality of first trenches 201 and a plurality of light emitting units 7, wherein the bottom surface of the first trenches 201 exposes the first reflective layer 22 or the first ohmic contact layer 21, and the etching is performed for the purpose of performing a subsequent oxidation process on the second reflective layer 24 and isolating the active layers 23 between the light emitting units 7, so that the etching depth is required to ensure that the active layers 23 are etched through, and it is not limited to which epitaxial layer structure under the active layers 23 is exposed by the etching process, and the etching depth can be adjusted according to the design. The first trench 201 is, for example, annular, and the specific shape may, for example, correspond to the shape of the second ohmic metal layer 5, so as to ensure that the shape of the light emitting hole formed by the subsequent oxidation process corresponds to the shape of the second ohmic metal layer 5 or the first trench 201, but the application is not limited thereto. The first trench 201 surrounds the corresponding light emitting unit 7 and spatially isolates two light emitting units 7 (some light emitting units 7 may not be electrically isolated from each other). The other part of the first insulating layer 6 and the epitaxial layer 2 are etched to form at least one second trench 202, the bottom surface of the second trench 202 exposes the substrate 1, so that the light emitting units 7 on both sides of the second trench 202 are electrically isolated, the light emitting unit arrays 70 can be formed between the light emitting units 7 on both sides of the second trench 202, and the light emitting unit arrays 70 are isolated from each other to meet the requirements of the cathode and the anode of the light emitting unit array 70 for independent lighting. The purpose of the second groove 202 is to form the light emitting cell array 70 having a plurality of light emitting cells 7, and the shape of the second groove 202 may be linear or circular, which is not limited in this application.

Referring to fig. 8, in an embodiment of the present invention, the epitaxial layer 5 may further include at least one oxide layer 26, the oxide layer 26 is exposed on the sidewall of the first trench 201, the current confinement layer 261 may be formed by oxidizing the oxide layer 26, and a region of the oxide layer 26 that is not oxidized is defined as the light emitting hole 262 of the light emitting unit 7. Note that, since the top view of the second ohmic metal layer 5 is a circular ring structure, the current confinement layer 261 is also a circular ring structure. In other embodiments, when the top view of the second ohmic metal layer 5 is a rectangular ring shape, the current confinement layer 261 may also be a rectangular ring structure. In an embodiment of the present application, the oxidation may be performed along the sidewall of the first trench 201 toward the center of the light emitting unit 7 by, for example, a high temperature oxidation method with highly doped aluminum. After oxidation, a current confinement layer 261 is formed in the light emitting unit 7, and a light emitting hole 262 is defined in an unoxidized region of the oxide layer 26, thereby forming a light emitting region.

Referring to fig. 7-8 again, the forming manner or forming sequence of the first trench 201, the second trench 202 and the oxide layer 26 in the present application is not limited thereto, and in other embodiments (not shown in the drawings), the first insulating layer 6 and the epitaxial layer 2 may be etched to form the first trench 201 and the portion of the second trench 202 (the etching depth is the same as that of the first trench), then oxidized to form the oxide layer 26, and then the second trench 202 is etched again or ion-implanted to form the light emitting cell array 70 with the cathode and the anode independent from each other; or the first trench and the oxide layer 26 are formed first, and then the second trench 202 is formed, the formation manner of the light emitting cell array 70 and the oxide layer 26 may be specifically designed.

Referring to fig. 9, in an embodiment of the present application, a second insulating layer 8 may be formed on the epitaxial layer 2 and a portion of the substrate 1. A second insulating layer 8 may cover the epitaxial layer 2 and a portion of the upper surface of the substrate 1. Specifically, the second insulating layer 8 may cover the first insulating layer 6, the sidewalls and the bottom surface of the first trench 201, and the sidewalls and the bottom surface of the second trench 202. The material and the process of the second insulating layer 8 may be the same as those of the first insulating layer 6, and are not described herein.

Referring to fig. 10, in an embodiment of the present invention, the second insulating layer 8 on the upper surface of the second ohmic metal layer 5 may be removed to form a first opening 81, and the first via 81 exposes the second ohmic metal layer 5, so that the second ohmic metal layer 5 is connected to a pad metal (the second electrode 9 described below). In the present embodiment, the width of the first opening 81 is smaller than the width of the second ohmic metal layer 5. The material of the second ohmic metal layer 5 may be one or a combination of Au metal, Ag metal, Pt metal, Ge metal, Ti metal, and Ni metal.

Referring to fig. 11, in an embodiment of the present application, the second electrode 9 may be formed. In an embodiment of the present application, the second electrode 9 may include a first anode 91 and a second anode 92. The second electrode 9 may be disposed on the first and second insulating layers 6 and 8, and the second electrode 9 may be in ohmic contact with the second ohmic contact layer 25 of the light emitting unit 7 through the second ohmic metal layer 5, and the second electrode 9 may serve as an anode of the vertical cavity surface emitting laser. The second electrode 9 may cover the first insulating layer 6 and the second insulating layer 8 of the light emitting cell array 70 not positioned on the light emitting hole 262 and cover the second ohmic metal layer 5 through the first opening 81 (i.e., the second electrode 9 is electrically connected to the second ohmic metal layer 5). Specifically, the second electrode 9 does not cover the light emitting hole 262 of the light emitting unit 7, and the second electrodes 9 between every two light emitting unit arrays 70 are not electrically connected to each other. In some embodiments of the present application, the material of the second electrode 9 may be one or a combination of Au metal, Cu metal, Pt metal, Ti metal and Ni metal. When the vertical cavity surface emitting laser operates, current is injected from the second electrode 9, passes through the second reflective layer 24, enters the active layer 23, due to the existence of the current limiting layer 261, most of the current vertically flows into the active layer 23 from the light emitting hole 262, and enables the active region to be excited and radiated, and laser oscillation is formed by excited and radiated light in a resonant cavity formed by the second reflective layer 24 and the first reflective layer 22, and then the laser oscillation is radiated from the second reflective layer 24 to form emergent light.

Referring to fig. 12, in one embodiment of the present application, the wafer is bonded to a handle substrate by organic (including but not limited to PMMA) or metal (including but not limited to Au), and then a backside process is performed. The handle substrate may be a temporarily supporting substrate that needs to be separated from the wafer after the backside process is completed. The handle substrate may also be a permanently supported substrate that does not require separation from the wafer after the backside process is completed and may become part of the device. In the second case, the bonding organics and the handle substrate are transparent materials with respect to the lasing wavelength. In addition, an anti-reflection layer can be added on the substrate to reduce the light loss, and the operation substrate is not shown in the schematic diagram. After the wafer is bonded to the handle substrate, the substrate 1 is thinned, typically to a thickness of 15-100 um. And etching the surface of the thinned substrate 1 away from the first ohmic contact layer 21 to form a groove 101, wherein the groove 101 exposes the lower surface of the first ohmic contact layer 21 away from the epitaxial layer 2. The size and shape of the groove may be freely designed, and in this example, may be a square shape having a size close to that of the light emitting cell array 70. In the etching process, the surface of the substrate 1 away from the epitaxial layer 2 may be etched to form the groove 101 by, for example, dry etching, and then the substrate material remaining in the groove 101 may be removed by, for example, wet etching to expose the first ohmic contact layer 21. The common solution is formed by proportioning phosphoric acid, hydrogen peroxide and water. Then, an n-type metal (the first ohmic metal layer 10 described below) is deposited on the first ohmic contact layer 21 to form an ohmic contact. Followed by electroplating or deposition of a thicker metal, such as Au or Cu, to form the back side pad metal (first electrode 12 described below).

Referring to fig. 13, in the present embodiment, an etch stopper layer 4 may be disposed between the substrate 1 and the first ohmic contact layer 21. The substrate 1 is opened by dry etching to form a groove 101, and the remaining substrate in the groove 101 and a part of the etch stopper 4 are removed by wet etching to expose the first ohmic contact layer 21. The material of the etch stop layer may be, for example, InGaP or a material having a high etch selectivity ratio with GaAs. An n-type metal (first ohmic metal layer 10 described below) is deposited to form an ohmic contact to form a back side pad metal (first electrode 12 described below).

Referring to fig. 14, in an embodiment of the present disclosure, a first ohmic metal layer 10 may be formed on a surface of the first ohmic contact layer 21 away from the first reflective layer 22. A third insulating layer 11 is formed on the first ohmic metal layer 10 and the surface of the substrate 1 remote from the first ohmic contact layer 21 and the sidewall of the groove 101. In the present embodiment, the etch stopper layer 4 may also be disposed between the substrate 1 and the first ohmic contact layer 21. In some embodiments of the present application, the material of the first ohmic metal layer 10 may be one or a combination of Au metal, Ag metal, Pt metal, Ge metal, Ti metal, and Ni metal. In this embodiment, the material of the third insulating layer 11 may be silicon nitride or silicon oxide or other insulating materials, and the thickness of the third insulating layer 11 may be in a range of 100nm to 1um, for example. In the present embodiment, the third insulating layer 11 may be formed, for example, by chemical vapor deposition. In other embodiments, since the substrate 1 is an insulating substrate, the third insulating layer 11 may not be formed on the surfaces of the first ohmic metal layer 10 and the substrate 1 away from the first ohmic contact layer 21 and on the sidewalls of the groove 101 for simplifying the process.

Referring to fig. 15 and 16, in an embodiment of the present invention, the third insulating layer 11 on the surface of the first ohmic metal layer 10 is removed to form a second opening 111, and the second opening 111 exposes the first ohmic metal layer 10, so that the first ohmic metal layer 10 is connected to the first electrode 12. In an embodiment of the present application, the width of the second opening 111 is smaller than the width of the first ohmic metal layer 10. The first electrode 12 may be formed in the recess 101 of the substrate 1 and cover the first ohmic metal layer 10 through the second opening 111 (i.e., the first electrode 12 is electrically connected to the first ohmic metal layer 10). In the present embodiment, the etch stopper layer 4 may also be disposed between the substrate 1 and the first ohmic contact layer 21. The first electrode 12 is in ohmic contact with the first ohmic contact layer 21 through the first ohmic metal layer 10, and the first electrode 12 may serve as a cathode of the vertical cavity surface emitting laser. In the present application, the thickness of the first electrode 12 may be larger than the depth of the recess 101 of the substrate 1, typically 5-90 um. The material of the first electrode 12 may be one or a combination of Au metal, Cu metal, Ti metal, and Ni metal.

Referring to fig. 17, in an embodiment of the present application, the first electrode 12 may include a first cathode 121, a second cathode 122, a third cathode 123 and a fourth cathode 124, the first electrode 12 may be located on the lower surface of the substrate 1, and the first electrode 12 covers the first ohmic metal layer 10 and a portion of the third insulating layer 11. In the present embodiment, the opening depth of the substrate 1 may be, for example, 5 to 90 um.

Referring to fig. 18, in an embodiment of the present application, on the front surface of the vcsel array, the first trench 201 divides the light emitting units 7 on two sides into a first light emitting unit array 71 and a second light emitting unit array 72, and the first light emitting unit array 71 and the second light emitting unit array 72 are vertically arranged in parallel. The first anode 91 is disposed on the first light emitting cell array 71, and the second anode 92 is disposed on the second light emitting cell array 72.

Referring to fig. 19 and 20, in an embodiment of the present application, a first cathode 121, a second cathode 122, a third cathode 123 and a fourth cathode 124 are included at the back of the vcsel array, wherein the first cathode 121 and the second cathode 122 divide the first light emitting cell array 71 into a first light emitting cell subarray 711 and a second light emitting cell subarray 712, and the third cathode 123 and the fourth cathode 124 divide the second light emitting cell array 72 into a third light emitting cell subarray 721 and a fourth light emitting cell subarray 722. The first cathode 121, the second cathode 122, the third cathode 123, and the fourth cathode 124 are independent of each other, and the first light emitting cell array 71 and the second light emitting cell array 72 can be independently controlled by the cathode (non-anode control), and specifically, the first light emitting cell sub-array 711, the second light emitting cell sub-array 712, the third light emitting cell sub-array 721, and the fourth light emitting cell sub-array 724 can be independently controlled by the cathode.

Referring to fig. 21, in an embodiment of the present application, a first cathode 121 and a second cathode 122 may be included at the bottom of the vcsel array. The first cathode 121 and the second cathode 122 are vertically arranged in parallel, and specifically, the first cathode 121 and the second cathode 122 are respectively disposed at two sides of the first trench 201. At this time, the rear cathode arrangement of the vcsel array is the same as the front first and second light emitting

cell arrays

71 and 72, i.e. the first cathode 121 overlaps the first anode 91 in the vertical direction (the light emitting direction of the laser), and the second cathode 122 overlaps the second anode 92 in the vertical direction.

Referring to fig. 22, in an embodiment of the present application, a first cathode 111 and a second cathode 112 may be included at the bottom of the vcsel array. At this time, the first cathode 111 and the second cathode 112 may be horizontally arranged in parallel, the first cathode 111 and the first light-emitting cell sub-array 711 and the third light-emitting cell sub-array 721 may overlap in projection in the vertical direction, the second cathode 112 and the second light-emitting cell sub-array 712 and the fourth light-emitting cell sub-array 722 may overlap in projection in the vertical direction, that is, the first cathode 111 and the second cathode 112 may overlap (cross) the first anode 91 and the second anode 92 in projection in the vertical direction. The embodiment of the application can reduce the design of the cathode circuit on the premise of meeting the independent control through the crossed arrangement of the anode and the cathode, thereby simplifying the design of the circuit and improving the efficiency of mass production and the yield of mass production products.

In summary, the present application provides a vertical cavity surface emitting laser array, wherein the back recess of the substrate is provided with an independent cathode, and the projections of the anode and the cathode in the vertical direction are mutually overlapped, so that the partition independent control can be performed in a two-dimensional manner.

The above description is only a preferred embodiment of the present application and a description of the applied technical principle, and it should be understood by those skilled in the art that the scope of the present invention related to the present application is not limited to the technical solution of the specific combination of the above technical features, and also covers other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, for example, the technical solutions formed by mutually replacing the above features with (but not limited to) technical features having similar functions disclosed in the present application.

Other technical features than those described in the specification are known to those skilled in the art, and are not described herein in detail in order to highlight the innovative features of the present invention.

Claims

1. A vertical cavity surface emitting laser array, comprising:

a substrate;

2. The vertical cavity surface emitting laser array of claim 1, further comprising:

an epitaxial layer formed on an upper surface of the substrate, the plurality of sub-arrays of vertical cavity surface emitting lasers being formed on the epitaxial layer;

the second ohmic metal layer is positioned on the epitaxial layer;

the first insulating layer is positioned on the epitaxial layer;

a first ohmic metal layer located in the groove of the substrate;

3. The vertical cavity surface emitting laser array of claim 2, wherein: the epitaxial layer comprises a first ohmic contact layer, the first ohmic contact layer is positioned on the upper surface of the substrate, and the first ohmic metal layer is in ohmic contact with the first ohmic contact layer.

4. The vertical cavity surface emitting laser array of claim 2, wherein: the epitaxial layer further comprises a first reflecting layer, an active layer and a second reflecting layer, and the sum of the thicknesses of the active layer and the second reflecting layer is 8-10 microns.

5. The VCSEL array of claim 4, wherein: the epitaxial layer comprises a second ohmic contact layer, the second ohmic contact layer is positioned on the second reflecting layer, and the second ohmic metal layer is in ohmic contact with the second ohmic contact layer.

6. The vertical cavity surface emitting laser array of claim 2, wherein: the light emitting units form a plurality of light emitting unit arrays, isolation structures are arranged among the light emitting unit arrays, and first grooves are arranged among the light emitting units.

7. The VCSEL array of claim 6, wherein: the isolation structure comprises a second groove and/or an ion injection layer, wherein the second groove is etched to the surface of the substrate or the ion injection layer is injected to the surface of the substrate so as to isolate the adjacent light emitting unit arrays.

8. The vertical cavity surface emitting laser array of claim 2, wherein: the first insulating layer covers the second ohmic contact layer and the upper surface and the side surface of the second ohmic metal layer.

9. The vertical cavity surface emitting laser array of claim 7, wherein: the second insulating layer covers the first insulating layer, the sidewall and the bottom surface of the first trench, and the sidewall and the bottom surface of the second trench.

10. The vertical cavity surface emitting laser array of claim 7, wherein: the etching depth of the second groove is larger than that of the first groove.