CN114551432A - Resistor structure and manufacturing method thereof - Google Patents
Resistor structure and manufacturing method thereof Download PDFInfo
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- CN114551432A CN114551432A CN202210455002.4A CN202210455002A CN114551432A CN 114551432 A CN114551432 A CN 114551432A CN 202210455002 A CN202210455002 A CN 202210455002A CN 114551432 A CN114551432 A CN 114551432A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
- H01L27/016—Thin-film circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
- H01L21/707—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
Abstract
The invention provides a resistor structure and a manufacturing method thereof, which are applied to the technical field of semiconductors. The invention provides a manufacturing method of a resistor structure, which utilizes partial area of a metal upper polar plate of an MIM capacitor structure to be used as a thin film resistor in the process of forming the MIM capacitor structure by utilizing the prior art so as to replace a polysilicon resistor formed by the traditional process. In the manufacturing method of the resistor structure provided by the invention, the characteristic of low temperature coefficient of the metal upper polar plate of the MIM capacitor structure is utilized, so that the thin film resistor with low temperature coefficient and high resistance precision is formed, the defect that the high-precision resistor cannot be configured due to too large temperature coefficient of the polysilicon resistor is further solved, and the manufacturing cost for forming the resistor device is saved on the basis of utilizing the existing resources.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a resistor structure and a manufacturing method thereof.
Background
In the manufacture of semiconductor products, such as integrated circuits, it is often necessary to provide a resistive device in a component or components of the semiconductor product. Currently, a commonly used resistor device is a polysilicon resistor Poly resistor. Specifically, in the existing method for forming a polysilicon resistor, a doped polysilicon film layer is used to change the resistance of the polysilicon, and the doped polysilicon is used as a resistor device.
However, when the current carrier inside the doped polysilicon resistor is subjected to temperature change, the influence on the resistance of the polysilicon resistor occurs, and the precision of the polysilicon resistor is reduced, so that the doped polysilicon resistor cannot be used for products with high precision and small temperature drift. Also, if the resistance device is an indispensable component in a semiconductor product, each semiconductor product must be provided with a specific resistance device according to its own characteristic self-customized process, which causes problems that the resistance device is high in manufacturing cost, is not favorable for product commercialization, and cannot benefit users.
Disclosure of Invention
The invention aims to provide a resistor structure and a manufacturing method thereof, and provides a novel manufacturing method for forming a resistor structure by using the existing MIM capacitor device so as to solve the problem that the polysilicon resistor in the prior art has a large temperature coefficient and further causes low precision of the resistor device.
In a first aspect, to solve the above technical problem, the present invention provides a method for manufacturing a resistor structure, including:
a semiconductor substrate with a first metal layer formed on the surface is provided.
Sequentially forming a first dielectric layer and a second metal layer on a surface of the first metal layer to form a MIM capacitor while forming a resistor structure using a portion of the second metal layer serving as an upper plate of the MIM capacitor, the MIM capacitor including, from top to bottom, a remaining portion of the second metal layer serving as an upper plate, a first dielectric layer, and the first metal layer serving as a lower plate.
Further, the step of forming the second metal layer may include:
depositing a second metal layer on a surface of the first dielectric layer.
And carrying out photoetching and etching processes on the second metal layer deposited on the surface of the first dielectric layer by utilizing an upper plate photomask of the MIM capacitor, wherein the upper plate photomask of the MIM capacitor is defined with a pattern for forming the resistor structure and a pattern for forming an upper plate of the MIM capacitor.
Further, the pattern defined on the MIM capacitor top plate mask for forming the resistor structure is laterally aligned and non-contiguous with the pattern for forming the MIM capacitor top plate.
Further, the material of the second metal layer may include titanium nitride.
Further, after forming the resistor structure and the MIM capacitor, the method may further comprise:
and forming a second dielectric layer on the surface of the second metal layer, and forming a first through hole for electrically connecting the resistor structure and a second through hole for electrically connecting the MIM capacitor in the second dielectric layer through photoetching and etching processes.
And filling a conductive material in the first through hole and the second through hole.
And forming a third metal layer on the surface of the second dielectric layer, wherein the third metal layer is electrically connected with the first through hole and the second through hole which are filled with the conductive material.
In a second aspect, the resistor structure may be prepared by the method for manufacturing a resistor structure as described above, based on the method for manufacturing a resistor structure as described above.
In a third aspect, based on the method for manufacturing a resistor structure, the present invention further provides a method for manufacturing an MIM capacitor, which may include:
a semiconductor substrate with a first metal layer formed on the surface is provided.
Sequentially forming a first dielectric layer and a second metal layer on a surface of the first metal layer to form a MIM capacitor while forming a resistor structure using a portion of the second metal layer serving as an upper plate of the MIM capacitor, the MIM capacitor including, from top to bottom, a remaining portion of the second metal layer serving as an upper plate, a first dielectric layer, and the first metal layer serving as a lower plate.
Further, the material of the second metal layer comprises titanium nitride.
Further, the step of forming the second metal layer may include:
depositing a second metal layer on a surface of the first dielectric layer.
And carrying out photoetching and etching processes on the second metal layer deposited on the surface of the first dielectric layer by utilizing an upper plate photomask of the MIM capacitor, wherein the upper plate photomask of the MIM capacitor is defined with a pattern for forming the resistor structure and a pattern for forming an upper plate of the MIM capacitor.
Further, the pattern defined on the MIM capacitor top plate mask for forming the resistor structure is laterally aligned and non-contiguous with the pattern for forming the MIM capacitor top plate.
In a fourth aspect, based on the method for manufacturing the MIM capacitor, the present invention also provides a MIM capacitor, which may include:
a semiconductor substrate.
And the first metal layer is positioned on the surface of the semiconductor substrate and is used as a lower polar plate of the MIM capacitor.
And the first dielectric layer is positioned on the surface of the first metal layer and is used as a dielectric layer of the MIM capacitor.
A second metal layer on a surface of the first dielectric layer, wherein a portion of the second metal layer serves as an upper plate of the MIM capacitor and a remaining portion of the second metal layer serves as a resistor structure included in the MIM capacitor.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
the invention provides a manufacturing method of a resistor structure, which utilizes partial area of a metal upper polar plate of an MIM capacitor structure to be used as a thin film resistor in the process of forming the MIM capacitor structure by utilizing the prior art so as to replace a polysilicon resistor formed by the traditional process. In the manufacturing method of the resistor structure provided by the invention, the characteristic of low temperature coefficient of the metal upper polar plate of the MIM capacitor structure is utilized, so that the thin film resistor with low temperature coefficient and high resistance precision is formed, the defect that the high-precision resistor cannot be configured due to too large temperature coefficient of the polysilicon resistor is further solved, and the manufacturing cost for forming the resistor device is saved on the basis of utilizing the existing resources.
Furthermore, the resistor structure is formed on the basis of the technological platform for forming the MIM capacitor structure, so that the invention also provides a layer of photomask utilizing the MIM capacitor structure, and the double functions of the MIM capacitor structure and the resistor device can be realized, thereby effectively reducing the production cost of the semiconductor device and meeting the requirement of developing the high-precision resistor device.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a resistor structure according to an embodiment of the invention.
Fig. 2 is a schematic structural diagram of a resistor structure according to an embodiment of the invention.
Wherein the reference numbers are as follows:
100-a semiconductor substrate; 110 — a first metal layer;
120-a first dielectric layer; 130-a second metal layer;
140-a second dielectric layer; 150-a third metal layer;
a C-MIM capacitor structure; an R-resistor structure;
101-a first via; 102-second via.
Detailed Description
As described in the background, in the manufacture of semiconductor products, such as integrated circuits, it is often necessary to provide a resistive device in a component or components of the semiconductor product. Currently, a commonly used resistor device is a polysilicon resistor Poly resistor. Specifically, in the existing method for forming a polysilicon resistor, a doped polysilicon film layer is used to change the resistance of the polysilicon, and the doped polysilicon is used as a resistor device.
However, when the current carrier inside the doped polysilicon resistor is subjected to temperature change, the influence on the resistance of the polysilicon resistor occurs, and the precision of the polysilicon resistor is reduced, so that the doped polysilicon resistor cannot be used for products with high precision and small temperature drift. Also, if the resistance device is an indispensable component in a semiconductor product, each semiconductor product must be provided with a specific resistance device according to its own characteristic self-customized process, which causes problems that the resistance device is high in manufacturing cost, is not favorable for product commercialization, and cannot benefit users.
Therefore, the invention provides a resistor structure and a manufacturing method thereof, and provides a novel manufacturing method for forming a resistor structure by using the existing MIM capacitor device, so as to solve the problem that the polysilicon resistor in the prior art has a large temperature coefficient and further causes low precision of the resistor device.
The resistor structure and the method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements. In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
The following first describes a method for manufacturing a resistor structure according to the present invention. With specific reference to fig. 1 in conjunction with fig. 2, fig. 1 is a schematic flow chart illustrating a method for manufacturing a resistor structure according to an embodiment of the invention; fig. 2 is a schematic structural diagram of a finally formed resistor structure provided in an embodiment of the invention. Specifically, as shown in fig. 1, the manufacturing method of the resistor structure may include the following steps:
in step S100, a semiconductor substrate 100 having a first metal layer 110 formed on a surface thereof is provided.
In the present embodiment, the semiconductor substrate 100 is a platform for providing operations for subsequent processes to generate a resistor structure and a MIM capacitor structure. The semiconductor substrate 100 may be any suitable substrate known in the art, and may be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, and further includes a multilayer structure composed of these semiconductors, or may be Silicon On Insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), or may be Double-Side Polished silicon Wafers (DSP), or may be a ceramic substrate such as alumina, quartz, or a glass substrate. Illustratively, in embodiments of the present invention, the semiconductor substrate 100 is a silicon substrate. Preferably, in the embodiment of the present invention, the material of the first metal layer 110 and the third metal layer 150 may be aluminum, and the material of the second metal layer 130 is preferably titanium nitride.
Step S200, sequentially forming a first dielectric layer 120 and a second metal layer 130 on a surface of the first metal layer 110 to form a MIM capacitor C while forming a resistor structure R using a portion of the second metal layer serving as an upper plate of the MIM capacitor, the MIM capacitor C including, from top to bottom, the remaining portion of the second metal layer serving as an upper plate, the first dielectric layer, and the first metal layer serving as a lower plate.
In this embodiment, since the characteristic of low temperature coefficient of the metal upper plate of the MIM capacitor structure is utilized in the forming of the MIM capacitor structure according to the prior art, so as to form a thin film resistor with low temperature coefficient and high resistance precision, the forming of the resistor structure is the forming of the MIM capacitor, that is, after the first metal layer 110 is formed in step S100, the first dielectric layer 120 serving as a dielectric of the MIM capacitor needs to be formed on the surface thereof, and then the second metal layer 130 serving as the upper plate of the MIM capacitor structure needs to be formed. However, since the second metal layer 130 formed as the top plate of the MIM capacitor structure also serves as the resistor structure, and the second metal layer 130 is formed by using a mask of the MIM capacitor structure, in particular, the present invention provides a specific manner for forming the second metal layer 130, which may include the following steps:
first, a second metal layer is deposited on a surface of the first dielectric layer.
And secondly, carrying out photoetching and etching processes on the second metal layer deposited on the surface of the first dielectric layer by utilizing an upper plate photomask of the MIM capacitor, wherein the upper plate photomask of the MIM capacitor is defined with a pattern for forming the resistor structure and a pattern for forming an upper plate of the MIM capacitor.
As an example, the pattern defined on the MIM capacitor top plate mask used to form the resistor structure is laterally aligned with and does not meet the pattern used to form the MIM capacitor top plate.
As another example, the pattern defined on the MIM capacitor top plate mask used to form the resistor structure is aligned laterally next to the pattern used to form the MIM capacitor top plate. Preferably, in the embodiment of the present invention, the mask is preferably the first example, and therefore, fig. 2 also schematically illustrates a structure of the second metal layer 130 formed by the mask for forming the upper plate of the MIM capacitor, in which the pattern for forming the resistor structure is arranged laterally to the pattern for forming the upper plate of the MIM capacitor and is not connected to the pattern for forming the upper plate of the MIM capacitor.
Further, with continued reference to fig. 2, after forming the resistor structure R and the MIM capacitor C, the method for manufacturing a resistor structure according to the present invention may further include the following steps:
first, a second dielectric layer 140 is formed on the surface of the second metal layer 130, and a first via 101 for electrically connecting the resistor structure R and a second via 102 for electrically connecting the MIM capacitor C are formed in the second dielectric layer 140 by photolithography and etching processes.
Next, a conductive material is filled in the first via hole 101 and the second via hole 102.
Thereafter, a third metal layer 150 electrically connected to the first via hole 101 and the second via hole 102 filled with the conductive material is formed on the surface of the second dielectric layer 140.
In this embodiment, the third metal layer 150 is used as an electrode pad to electrically connect the resistor structure R and the capacitor structure C through the first via 101 and the second via 102 filled with the conductive material, respectively, for connecting with an external circuit.
In addition, based on the same inventive concept as the manufacturing method of the resistor structure, the invention further provides a resistor structure, which is specifically prepared by the manufacturing method of the resistor structure, and the specific manufacturing method refers to the process of the manufacturing method described with reference to fig. 1, and will not be described in detail herein.
In the same way, based on the same inventive concept as the manufacturing method of the resistor structure, the invention also provides a manufacturing method of the MIM capacitor, which specifically comprises the following steps:
a semiconductor substrate with a first metal layer formed on the surface is provided.
Sequentially forming a first dielectric layer and a second metal layer on a surface of the first metal layer to form a MIM capacitor while forming a resistor structure using a portion of the second metal layer serving as an upper plate of the MIM capacitor, the MIM capacitor including, from top to bottom, a remaining portion of the second metal layer serving as an upper plate, a first dielectric layer, and the first metal layer serving as a lower plate.
Wherein the material of the second metal layer comprises titanium nitride.
Further, the step of forming the second metal layer during the formation of the MIM capacitor structure may include the steps of:
first, a second metal layer is deposited on a surface of the first dielectric layer.
And secondly, carrying out photoetching and etching processes on the second metal layer deposited on the surface of the first dielectric layer by utilizing an upper plate photomask of the MIM capacitor, wherein the upper plate photomask of the MIM capacitor is defined with a pattern for forming the resistor structure and a pattern for forming an upper plate of the MIM capacitor.
Wherein the pattern for forming the resistor structure defined on the MIM capacitor upper plate mask is arranged transversely and not connected with the pattern for forming the MIM capacitor upper plate.
In addition, based on the same inventive concept, the present invention also provides an MIM capacitor, which may specifically include:
a semiconductor substrate.
And the first metal layer is positioned on the surface of the semiconductor substrate and is used as a lower polar plate of the MIM capacitor.
And the first dielectric layer is positioned on the surface of the first metal layer and is used as a dielectric layer of the MIM capacitor.
A second metal layer on a surface of the first dielectric layer, wherein a portion of the second metal layer serves as an upper plate of the MIM capacitor and a remaining portion of the second metal layer serves as a resistor structure included in the MIM capacitor.
In summary, the present invention provides a method for manufacturing a resistor structure, which uses a partial region of a metal top plate of a MIM capacitor structure as a thin film resistor device in a process of forming the MIM capacitor structure using the prior art, so as to replace a polysilicon resistor formed by a conventional process. In the manufacturing method of the resistor structure provided by the invention, the characteristic of low temperature coefficient of the metal upper polar plate of the MIM capacitor structure is utilized, so that the thin film resistor with low temperature coefficient and high resistance precision is formed, the defect that the high-precision resistor cannot be configured due to too large temperature coefficient of the polysilicon resistor is further solved, and the manufacturing cost for forming the resistor device is saved on the basis of utilizing the existing resources.
Furthermore, the resistor structure is formed on the basis of the technological platform for forming the MIM capacitor structure, so that the invention also provides a layer of photomask utilizing the MIM capacitor structure, and the double functions of the MIM capacitor structure and the resistor device can be realized, thereby effectively reducing the production cost of the semiconductor device and meeting the requirement of developing the high-precision resistor device.
In addition, the embodiment of the invention also provides an electronic device, which comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus,
a memory for storing a computer program.
The processor is configured to implement the method for manufacturing a resistor structure or the method for manufacturing an MIM capacitor according to the embodiment of the present invention when executing the program stored in the memory, and specifically, the method for manufacturing a resistor structure may include:
a semiconductor substrate with a first metal layer formed on the surface is provided.
Sequentially forming a first dielectric layer and a second metal layer on a surface of the first metal layer to form a MIM capacitor while forming a resistor structure using a portion of the second metal layer serving as an upper plate of the MIM capacitor, the MIM capacitor including, from top to bottom, a remaining portion of the second metal layer serving as an upper plate, a first dielectric layer, and the first metal layer serving as a lower plate.
The manufacturing method of the MIM capacitor comprises the following steps:
a semiconductor substrate with a first metal layer formed on the surface is provided.
Sequentially forming a first dielectric layer and a second metal layer on a surface of the first metal layer to form a MIM capacitor while forming a resistor structure using a portion of the second metal layer serving as an upper plate of the MIM capacitor, the MIM capacitor including, from top to bottom, a remaining portion of the second metal layer serving as an upper plate, a first dielectric layer, and the first metal layer serving as a lower plate.
For specific implementation and related explanation of each step of the method, reference may be made to the method embodiments shown in fig. 1 and fig. 2, which are not described herein again.
In addition, other implementation manners of the method for manufacturing the resistor structure, which are realized by the processor executing the program stored in the memory, are the same as the implementation manners mentioned in the foregoing method embodiment portions, and are not described again here.
The communication bus mentioned in the electronic device may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.
The communication interface is used for communication between the electronic equipment and other equipment.
The Memory may include a Random Access Memory (RAM) or a Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory 303 may also be at least one storage device located remotely from the aforementioned processor.
The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.
In yet another embodiment of the present invention, a computer-readable storage medium is further provided, which has instructions stored therein, and when the computer-readable storage medium is run on a computer, the computer is caused to execute the method for manufacturing a resistor structure according to any one of the above embodiments.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the apparatus, the electronic device, and the computer-readable storage medium embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and in relation to the description, reference may be made to some portions of the description of the method embodiments.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (11)
1. A method of manufacturing a resistor structure, comprising:
providing a semiconductor substrate with a first metal layer formed on the surface;
sequentially forming a first dielectric layer and a second metal layer on a surface of the first metal layer to form a MIM capacitor while forming a resistor structure using a portion of the second metal layer serving as an upper plate of the MIM capacitor, the MIM capacitor including, from top to bottom, a remaining portion of the second metal layer serving as an upper plate, a first dielectric layer, and the first metal layer serving as a lower plate.
2. The method of manufacturing a resistor structure according to claim 1, wherein the step of forming the second metal layer comprises:
depositing a second metal layer on a surface of the first dielectric layer;
and carrying out photoetching and etching processes on the second metal layer deposited on the surface of the first dielectric layer by utilizing an upper plate photomask of the MIM capacitor, wherein the upper plate photomask of the MIM capacitor is defined with a pattern for forming the resistor structure and a pattern for forming an upper plate of the MIM capacitor.
3. The method of claim 2, wherein the pattern defined on the MIM capacitor top plate mask used to form the resistor structure is laterally aligned and non-contiguous with the pattern used to form the MIM capacitor top plate.
4. The method of manufacturing a resistor structure according to claim 1, wherein the material of the second metal layer comprises titanium nitride.
5. The method of manufacturing a resistor structure of claim 1, wherein after forming the resistor structure and the MIM capacitor, the method further comprises:
forming a second dielectric layer on the surface of the second metal layer, and forming a first through hole for electrically connecting the resistor structure and a second through hole for electrically connecting the MIM capacitor in the second dielectric layer through photoetching and etching processes;
filling a conductive material in the first through hole and the second through hole;
and forming a third metal layer on the surface of the second dielectric layer, wherein the third metal layer is electrically connected with the first through hole and the second through hole which are filled with the conductive material.
6. A resistor structure, characterized in that the resistor structure is prepared by the method for manufacturing a resistor structure according to any one of claims 1 to 5.
7. A method of fabricating a MIM capacitor, comprising:
providing a semiconductor substrate with a first metal layer formed on the surface;
sequentially forming a first dielectric layer and a second metal layer on a surface of the first metal layer to form a MIM capacitor while forming a resistor structure using a portion of the second metal layer serving as an upper plate of the MIM capacitor, the MIM capacitor including, from top to bottom, a remaining portion of the second metal layer serving as an upper plate, a first dielectric layer, and the first metal layer serving as a lower plate.
8. The method of fabricating the MIM capacitor according to claim 7 wherein the material of the second metal layer comprises titanium nitride.
9. The method of fabricating the MIM capacitor according to claim 7 wherein the step of forming the second metal layer comprises:
depositing a second metal layer on a surface of the first dielectric layer;
and carrying out photoetching and etching processes on the second metal layer deposited on the surface of the first dielectric layer by utilizing an upper plate photomask of the MIM capacitor, wherein the upper plate photomask of the MIM capacitor is defined with a pattern for forming the resistor structure and a pattern for forming an upper plate of the MIM capacitor.
10. The method of claim 9, wherein the pattern defined on the MIM capacitor top plate mask used to form the resistor structure is laterally aligned and non-contiguous with the pattern used to form the MIM capacitor top plate.
11. A MIM capacitor manufactured according to the method of manufacturing a MIM capacitor according to one of claims 7 to 10, comprising:
a semiconductor substrate;
the first metal layer is positioned on the surface of the semiconductor substrate and is used as a lower polar plate of the MIM capacitor;
the first dielectric layer is positioned on the surface of the first metal layer and is used as a dielectric layer of the MIM capacitor;
a second metal layer on a surface of the first dielectric layer, wherein a portion of the second metal layer serves as an upper plate of the MIM capacitor and a remaining portion of the second metal layer serves as a resistor structure included in the MIM capacitor.
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| CN202210455002.4A CN114551432A (en) | 2022-04-28 | 2022-04-28 | Resistor structure and manufacturing method thereof |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1830042A (en) * | 2003-06-02 | 2006-09-06 | 国际商业机器公司 | Method of fabrication of thin film resistor with 0 TCR |
| CN103811460A (en) * | 2012-10-17 | 2014-05-21 | 德州仪器德国股份有限公司 | Electronic Device Comprising a Semiconductor Structure Having an Integrated Circuit Back End Capacitor and Thin Film Resistor and Method of Manufacturing the Same |
| US20140264751A1 (en) * | 2013-03-12 | 2014-09-18 | Qualcomm Incorporated | Metal-insulator-metal (mim) capacitor |
| US20150108607A1 (en) * | 2013-10-17 | 2015-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit and manufacturing method thereof |
| CN106463507A (en) * | 2014-05-05 | 2017-02-22 | 德克萨斯仪器股份有限公司 | Integrated thin film resistor and mim capacitor |
| CN109786356A (en) * | 2017-11-13 | 2019-05-21 | 台湾积体电路制造股份有限公司 | Device including MIM capacitor and resistor |
-
2022
- 2022-04-28 CN CN202210455002.4A patent/CN114551432A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1830042A (en) * | 2003-06-02 | 2006-09-06 | 国际商业机器公司 | Method of fabrication of thin film resistor with 0 TCR |
| CN103811460A (en) * | 2012-10-17 | 2014-05-21 | 德州仪器德国股份有限公司 | Electronic Device Comprising a Semiconductor Structure Having an Integrated Circuit Back End Capacitor and Thin Film Resistor and Method of Manufacturing the Same |
| US20140264751A1 (en) * | 2013-03-12 | 2014-09-18 | Qualcomm Incorporated | Metal-insulator-metal (mim) capacitor |
| US20150108607A1 (en) * | 2013-10-17 | 2015-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit and manufacturing method thereof |
| CN106463507A (en) * | 2014-05-05 | 2017-02-22 | 德克萨斯仪器股份有限公司 | Integrated thin film resistor and mim capacitor |
| CN109786356A (en) * | 2017-11-13 | 2019-05-21 | 台湾积体电路制造股份有限公司 | Device including MIM capacitor and resistor |
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