CN114550636A

CN114550636A - Control method of data driver and time sequence controller and electronic equipment

Info

Publication number: CN114550636A
Application number: CN202210218999.1A
Authority: CN
Inventors: 李东明; 白东勋; 南帐镇; 倪恩伟
Original assignee: Beijing Eswin Computing Technology Co Ltd; Hefei Eswin IC Technology Co Ltd
Current assignee: Hefei Yisiwei Computing Technology Co ltd; Beijing Eswin Computing Technology Co Ltd
Priority date: 2022-03-08
Filing date: 2022-03-08
Publication date: 2022-05-27
Anticipated expiration: 2042-03-08
Also published as: CN114550636B; US20230290292A1

Abstract

A control method and a control device of a data driver, a timing controller and a control method thereof, an electronic device and a storage medium, the control method of the data driver includes: respectively acquiring m data comparison signals, wherein in the m data comparison signals, the ith data comparison signal represents a comparison relation between first display data used for enabling the ith group of sub-pixels in the first pixel row to display and second display data used for enabling the ith group of sub-pixels in the second pixel row to display, the second pixel row is driven and displayed after the first pixel row in terms of time, i is an integer, and i is more than 0 and less than or equal to m; and respectively controlling the working state of the data driver according to each data comparison signal in the m data comparison signals. The control method helps to reduce the operating power consumption of the data driver.

Description

Control method of data driver and time sequence controller and electronic equipment

Technical Field

Embodiments of the present disclosure relate to a control method of a data driver, a control method of a timing controller, a data driver control device, a timing controller, an electronic apparatus, and a storage medium.

Background

At present, with the continuous development and progress of display technology, the performance requirements of the market for display products are gradually increased. For example, in order to achieve better display effect, it is generally required to increase display performance parameters of a display product, such as resolution, Frame Rate (Frame Rate), etc., so that the transmission speed of data for display in the display product is correspondingly increased.

Disclosure of Invention

At least one embodiment of the present disclosure provides a control method of a data driver for a display panel including a plurality of pixel rows sequentially arranged in a first direction, each of the pixel rows including a plurality of sub-pixels sequentially arranged in a second direction and divided into m groups, the second direction being different from the first direction, m being an integer greater than 1; the plurality of pixel rows comprises a first pixel row and a second pixel row, the second pixel row being driven to display temporally after the first pixel row; the control method comprises the following steps: respectively acquiring m data comparison signals, wherein in the m data comparison signals, the ith data comparison signal represents a comparison relation between first display data used for enabling the ith group of sub-pixels in the first pixel row to display and second display data used for enabling the ith group of sub-pixels in the second pixel row to display, i is an integer, and i is greater than 0 and less than or equal to m; and respectively controlling the working state of the data driver according to each data comparison signal in the m data comparison signals.

For example, in a control method of a data driver provided by an embodiment of the present disclosure, the number of the plurality of sub-pixels included in each of the pixel rows is (m × n), n is an integer greater than 0; the (m × j + i) th sub-pixel in the first pixel row belongs to the ith group of sub-pixels in the first pixel row, the (m × j + i) th sub-pixel in the second pixel row belongs to the ith group of sub-pixels in the second pixel row, j is an integer, and j is more than or equal to 0 and less than n; the ith data comparison signal represents a comparison relationship between first display data for causing a (m × j + i) th sub-pixel in the first pixel row to display and second display data for causing a (m × j + i) th sub-pixel in the second pixel row to display.

For example, in a control method of a data driver provided in an embodiment of the present disclosure, the (m × j + i) th sub-pixel in the first pixel row and the (m × j + i) th sub-pixel in the second pixel row share the same data line in the display panel, so as to apply a first display electrical signal corresponding to the first display data to the (m × j + i) th sub-pixel in the first pixel row and apply a second display electrical signal corresponding to the second display data to the (m × j + i) th sub-pixel in the second pixel row through the same data line, respectively.

For example, in a control method of a data driver provided in an embodiment of the present disclosure, the (m × j + i) th sub-pixel in the first pixel row and the (m × j + i) th sub-pixel in the second pixel row are respectively located at two sides of the same data line in the second direction; or, the (m × j + i) th sub-pixel in the first pixel row and the (m × j + i) th sub-pixel in the second pixel row are located on at least one side of the same data line in the second direction.

For example, in a control method of a data driver provided by an embodiment of the present disclosure, the number of the plurality of sub-pixels included in each of the pixel rows is (2 × m × n), n is an integer greater than 0; the (2 XmXj +2 xi-1) th sub-pixel and the (2 XmXj +2 xi) th sub-pixel in the first pixel row belong to the ith group of sub-pixels in the first pixel row, the (2 XmXj +2 xi-1) th sub-pixel and the (2 XmXj +2 xi) th sub-pixel in the second pixel row belong to the ith group of sub-pixels in the second pixel row, j is an integer, and j is more than or equal to 0 and less than n; the ith data comparison signal represents a comparison relationship between first display data for causing the (2 × m × j +2 × i-1) th sub-pixel and the (2 × m × j +2 × i) th sub-pixel in the first pixel row to display and second display data for causing the (2 × m × j +2 × i-1) th sub-pixel and the (2 × m × j +2 × i) th sub-pixel in the second pixel row to display.

For example, in a control method of a data driver provided in an embodiment of the present disclosure, the (2 × m × j +2 × i-1) th and (2 × m × j +2 × i) th sub-pixels in the first pixel row and the (2 × m × j +2 × i) th and (2 × m × j +2 × i) th sub-pixels in the second pixel row share the same data line in the display panel, so as to apply a first display electrical signal corresponding to the first display data to the (2 × m × j +2 × i-1) th and (2 × m × j +2 × i) th sub-pixels in the first pixel row and to apply a second display electrical signal corresponding to the second display data to the (2 × m × j +2 × i-1) th and (2 × j +2 × i) th sub-pixels in the second pixel row through the same data line, respectively ) And a sub-pixel.

For example, in a control method of a data driver provided in an embodiment of the present disclosure, the (2 × m × j +2 × i-1) th sub-pixel and the (2 × m × j +2 × i) th sub-pixel in the first pixel row and the (2 × m × j +2 × i-1) th sub-pixel and the (2 × m × j +2 × i) th sub-pixel in the second pixel row are respectively located on two sides of the same data line in the second direction; or the (2 × m × j +2 × i-1) th sub-pixel and the (2 × m × j +2 × i) th sub-pixel in the first pixel row and the (2 × m × j +2 × i-1) th sub-pixel and the (2 × m × j +2 × i) th sub-pixel in the second pixel row are located on at least one side of the same data line in the second direction.

For example, in a control method of a data driver provided in an embodiment of the present disclosure, the first pixel row and the second pixel row are two pixel rows arranged adjacent to each other in the first direction, and driving display orders of the first pixel row and the second pixel row are adjacent to each other in time.

For example, in a control method of a data driver provided in an embodiment of the present disclosure, the data driver includes a plurality of modules configured to receive an input data signal and obtain display data from the input data signal, and respectively control the data according to each of the m data comparison signals, including: in response to the ith data comparison signal indicating that the first display data and the second display data have a first comparison relationship therebetween, obtaining the second display data based on the first display data that has been buffered by the data driver, wherein the first comparison relationship includes whether the first display data is the same as or opposite to the second display data; or, in response to the ith data comparison signal indicating that the first display data and the second display data have a second comparison relationship therebetween different from the first comparison relationship, the second display data is derived based on the input data signals received by the data driver for the ith group of sub-pixels in the second pixel row.

For example, in a control method of a data driver provided in an embodiment of the present disclosure, the data is respectively controlled according to each of the m data comparison signals, and the method further includes: determining whether the data driver receives the input data signal in response to the first comparison relationship.

For example, in a control method of a data driver provided in an embodiment of the present disclosure, the data is respectively controlled according to each of the m data comparison signals, and the method further includes: responding to the first comparison relationship, and enabling at least part of the modules in the plurality of modules to be in a first working state; responding to the second comparison relationship, and enabling the modules to be in a second working state; each of the plurality of modules consumes less power in the first operating state than in the second operating state.

For example, in a control method of a data driver provided in an embodiment of the present disclosure, enabling at least some of the modules to be in the first operating state includes: such that the at least some modules are in an inactive state.

At least one embodiment of the present disclosure also provides a control method of a timing controller, the control method including: determining a plurality of comparison relationships between a plurality of sets of first display data and a plurality of sets of second display data respectively according to source input data received from a data source, and generating a plurality of data comparison signals for representing the plurality of comparison relationships, the plurality of sets of first display data being used for enabling a plurality of sets of sub-pixels in a first pixel row to be displayed respectively, the plurality of sets of second display data being used for enabling a plurality of sets of sub-pixels in a second pixel row to be displayed, the second pixel row being driven to be displayed after the first pixel row in terms of time; and transmitting the plurality of data comparison signals to a data driver.

At least one embodiment of the present disclosure also provides a data driver control apparatus including a data comparison signal acquisition unit and a working state control unit; the data comparison signal acquisition unit is configured to acquire a plurality of data comparison signals respectively representing a plurality of comparison relationships between a plurality of sets of first display data respectively for causing a plurality of sets of sub-pixels in a first pixel row to be displayed and a plurality of sets of second display data respectively for causing a plurality of sets of sub-pixels in a second pixel row to be driven to be displayed temporally after the first pixel row; the working state control unit is configured to control the working state of the data driver according to each data comparison signal.

At least one embodiment of the present disclosure also provides a timing controller including a data comparison signal generating unit and a signal transmitting unit; the data comparison signal generation unit is configured to determine a plurality of comparison relationships between a plurality of sets of first display data and a plurality of sets of second display data, respectively, according to source input data received from a data source, the plurality of sets of first display data being used to cause a plurality of sets of sub-pixels in a first pixel row to be displayed, the plurality of sets of second display data being used to cause a plurality of sets of sub-pixels in a second pixel row to be displayed, the second pixel row being driven to be displayed temporally after the first pixel row, and generate a plurality of data comparison signals representing the plurality of comparison relationships; the signal transmission unit is configured to transmit the plurality of data comparison signals to a data driver.

At least one embodiment of the present disclosure further provides an electronic device, including the timing controller and the data driver according to any one of the embodiments of the present disclosure; the data driver comprises a data comparison signal acquisition unit and a working state control unit; the data comparison signal acquisition unit is configured to acquire the plurality of data comparison signals; the working state control unit is configured to control the working state of the data driver according to each data comparison signal.

At least one embodiment of the present disclosure also provides an electronic device comprising a memory and a processor; the memory non-transiently stores computer-executable instructions; the processor is configured to execute the computer-executable instructions, and when executed by the processor, the computer-executable instructions implement the control method of the data driver according to any embodiment of the present disclosure or the control method of the timing controller according to any embodiment of the present disclosure.

At least one embodiment of the present disclosure also provides a non-transitory computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement a control method of a data driver according to any one of the embodiments of the present disclosure or a control method of a timing controller according to any one of the embodiments of the present disclosure.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

Fig. 1 is a schematic flow chart of a control method of a data driver according to some embodiments of the present disclosure;

fig. 2 is a schematic structural diagram of a display panel according to some embodiments of the present disclosure;

fig. 3 is a schematic structural diagram of another display panel provided in some embodiments of the present disclosure;

fig. 4 is a schematic structural diagram of another display panel according to some embodiments of the present disclosure;

fig. 5 is a schematic flowchart of step S12 in a control method of a data driver according to some embodiments of the present disclosure;

fig. 6 is a schematic diagram of a data driver according to some embodiments of the present disclosure;

FIG. 7 is a schematic diagram of an example implementation of the data driver shown in FIG. 6;

FIG. 8 is a schematic diagram of another example implementation of the data driver shown in FIG. 6;

FIG. 9 is a schematic diagram of an input data signal provided by some embodiments of the present disclosure;

FIG. 10 is a schematic diagram of an operating state of the example of the data driver shown in FIG. 7;

FIG. 11 is a schematic illustration of another operating state of the example of the data driver shown in FIG. 7;

FIG. 12 is a schematic diagram of an operating state of the example of the data driver shown in FIG. 8;

FIG. 13 is a schematic illustration of another operating state of the example of the data driver shown in FIG. 8;

FIG. 14 is a schematic diagram of another input data signal provided by some embodiments of the present disclosure;

fig. 15 is a schematic flow chart of a control method of a timing controller according to some embodiments of the present disclosure;

fig. 16 is a schematic block diagram of a data driver control apparatus provided in some embodiments of the present disclosure;

fig. 17 is a schematic block diagram of a timing controller control apparatus according to some embodiments of the present disclosure;

fig. 18 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure;

fig. 19 is a schematic diagram of an example of an electronic device provided by some embodiments of the present disclosure;

fig. 20 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure;

fig. 21 is a schematic block diagram of yet another electronic device provided by some embodiments of the present disclosure; and

fig. 22 is a schematic diagram of a storage medium according to some embodiments of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

With the increasing of display performance parameters of display products, such as resolution, Frame Rate (Frame Rate), and the like, the transmission speed of data for display in the display products is correspondingly increased, so that the power consumption of transmission interfaces, logic circuits, or other units or modules for data transmission and data processing in the display products is increased, the total power consumption of the display products is greatly increased, and the use cost of the products is sharply increased.

Moreover, since the total power consumption of the display product is greatly increased, when the display product is used for low-voltage domain display, for example, the higher operating current may also have a serious adverse effect on the characteristics of the display product, such as high-frequency electromagnetic interference (EMI) resistance, Wireless Wide Area Network (WWAN) signal transmission, and the like, and thus the stability and reliability of signal transmission in the display product may be reduced.

At least one embodiment of the present disclosure provides a control method of a data driver for a display panel including a plurality of pixel rows sequentially arranged in a first direction, each pixel row including a plurality of sub-pixels sequentially arranged in a second direction and divided into m groups, the second direction being different from the first direction, m being an integer greater than 1; the plurality of pixel rows include a first pixel row and a second pixel row, the second pixel row being driven to display temporally after the first pixel row; the control method comprises the following steps: respectively acquiring m data comparison signals, wherein in the m data comparison signals, the ith data comparison signal represents a comparison relation between first display data used for enabling the ith group of sub-pixels in the first pixel row to display and second display data used for enabling the ith group of sub-pixels in the second pixel row to display, i is an integer, and i is more than 0 and less than or equal to m; and respectively controlling the working state of the data driver according to each data comparison signal in the m data comparison signals.

In the control method of the data driver provided by the embodiment of the disclosure, the sub-pixels in the second pixel row to be driven and displayed are divided into multiple groups, and a comparison relationship between the second display data corresponding to each group of sub-pixels and the first display data corresponding to the corresponding sub-pixel group in the first pixel row driven and displayed prior to the second pixel row is obtained respectively, so that the data driver is in different working states when providing the second display data corresponding to different sub-pixel groups in the second pixel row according to the obtained multiple data comparison signals representing the comparison relationship. Therefore, the working power consumption of the data driver can be flexibly controlled, so that the beneficial effects of reducing the working power consumption of the data driver and further reducing the total power consumption of a system are facilitated, and the use cost of a product is reduced.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different figures will be used to refer to the same elements that have been described.

Fig. 1 is a schematic flowchart of a control method for a data driver of a display panel according to some embodiments of the present disclosure.

The display panel includes a plurality of pixel rows sequentially arranged in a first direction, each pixel row including a plurality of sub-pixels sequentially arranged in a second direction and divided into m groups, m being an integer greater than 1, that is, the plurality of sub-pixels included in each pixel row are divided into a plurality of groups. The second direction is different from the first direction. The plurality of pixel rows includes a first pixel row and a second pixel row, the second pixel row being driven to display temporally after the first pixel row.

As shown in fig. 1, the control method of the data driver for the display panel according to the embodiment of the present disclosure includes steps S11 and S12.

Step S11: m data comparison signals are respectively obtained, wherein in the m data comparison signals, the ith data comparison signal represents a comparison relation between first display data used for enabling the ith group of sub-pixels in the first pixel row to display and second display data used for enabling the ith group of sub-pixels in the second pixel row to display, i is an integer, and i is greater than 0 and less than or equal to m.

Step S12: and respectively controlling the working state of the data driver according to each data comparison signal in the m data comparison signals.

For example, the display panel in the above embodiments of the present disclosure may be any product or component having a display function, such as a liquid crystal panel, a liquid crystal television, an OLED panel, an OLED television, a QLED panel, a QLED television, a display, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, and the like, and the embodiments of the present disclosure do not specifically limit the type of the display panel.

For example, the plurality of sub-pixels in the display panel may be arranged in an array along the first direction and the second direction, respectively. For example, the plurality of sub-pixels may be arranged in a plurality of rows in a first direction and a plurality of columns in a second direction, respectively, the first direction may be a column direction, and the second direction may be a row direction.

For example, the plurality of sub-pixels in each pixel row may be divided into a plurality of groups, that is, into m groups, for example, the plurality of sub-pixels in each pixel row may be divided into a first group and a second group, or divided into a first group, a second group, and a third group, or divided into a first group, a second group, a third group, and a fourth group, or divided into more groups, and so on, which is not particularly limited by the embodiments of the present disclosure.

For example, multiple sets of sub-pixels in different pixel rows may correspond one to each other. For example, taking the example of a first pixel row and a second pixel row, a first group of sub-pixels in the first pixel row corresponds to a first group of sub-pixels in the second pixel row, a second group of sub-pixels in the first pixel row corresponds to a second group of sub-pixels in the second pixel row, a third group of sub-pixels in the first pixel row corresponds to a third group of sub-pixels in the second pixel row, and so on.

For example, with respect to the above-described step S11, among the acquired plurality of data comparison signals (i.e., m data comparison signals), the first data comparison signal represents a comparison relationship between first display data for causing a first group of subpixels in a first pixel row to display and second display data for causing a first group of subpixels in a second pixel row to display, the second data comparison signal represents a comparison relationship between first display data for causing a second group of subpixels in the first pixel row to display and second display data for causing a second group of subpixels in the second pixel row to display, the third data comparison signal represents a comparison relationship between first display data for causing a third group of subpixels in the first pixel row to display and second display data for causing a third group of subpixels in the second pixel row to display, and so on.

For example, with the above step S11, the display data is used to drive the corresponding pixel row for the display operation. For example, after signal processing such as noise reduction processing, digital-to-analog conversion processing, operational amplification processing, or the like is performed on the display data, a display voltage, a display current, or the like obtained based on the display data may be applied to the corresponding pixel row so that the sub-pixels in the corresponding pixel row perform display in accordance with the applied display voltage, display current, or the like.

For example, the time sequence in which the second pixel row is driven to display is after the first pixel row, and the first display data corresponding to the first pixel row is already acquired and buffered in the data driver before the data driver acquires the second display data corresponding to the second pixel row. For example, the second pixel row is a pixel row to be driven to display, the first pixel row may be a pixel row that is before the second pixel row in the time sequence of driving to display and is also not driven to display, or the first pixel row may also be a pixel row that is driven to display, which is not limited in this embodiment of the disclosure.

For example, the comparison relationship between the first display data and the second display data may include that the first display data is the same as the second display data, that the first display data is opposite to the second display data, or other relative data relationship between the first display data and the second display data, etc.

For example, the first display data and the second display data may be digital signals expressed by using a binary system as a principle, and the first display data and the second display data are opposite to each other in terms of bit-by-bit, that is, the second display data may be obtained by logically inverting the first display data, or the first display data may be obtained by logically inverting the second display data.

For example, taking the first display data and the second display data as "0100" and "1011" encoded in binary, respectively, the "0100" and the "1011" are bit-wise opposite, that is, 0100 ═ | is taken as an example! 1011, so that logically inverting one of the first display data and the second display data results in the other.

For another example, the first display data and the second display data may be analog signals represented by continuously changing physical quantities, and the first display data and the second display data are opposite in phase, that is, the second display data may be obtained by phase-inverting the first display data, or the first display data may be obtained by phase-inverting the second display data.

It should be noted that, the data types of the first display data and the second display data are not particularly limited in the embodiments of the present disclosure, and the first display data and the second display data may be digital signals or analog signals as described above, or may also be other suitable types of electrical signals, etc. according to the requirements of the practical application.

For example, with the above step S12, after the plurality of data comparison signals corresponding to different sub-pixel groups in the second pixel row are respectively acquired, the data driver may be respectively controlled to operate in corresponding different operating states according to each data comparison signal. For example, it may be determined, according to the acquired data comparison signals, that the data driver implements different operation modes or different work flows when acquiring the second display data corresponding to different sub-pixel groups, thereby enabling the data driver to operate in different operation states accordingly. Furthermore, the working power consumption of the data driver can be flexibly controlled, the beneficial effects of reducing the working power consumption of the data driver and further reducing the total power consumption of the system are favorably achieved, and the use cost is reduced.

For example, according to different comparison relationships between the first display data and the second display data, it can be determined whether the data driver can obtain the second display data according to the first display data cached in the data driver, which is helpful for reducing power consumption required to be consumed by the data driver in the process of obtaining the second display data and reducing the total system power consumption of the data driver.

In addition, the control method of the data driver according to the above embodiment of the present disclosure may further reduce the operating current generated in the data driver by reducing the total power consumption of the system of the data driver when the data driver is used for displaying, for example, a low voltage domain of a display panel, so as to be beneficial to improving characteristics of signal transmission in the data driver, such as high frequency electromagnetic interference (EMI) resistance, Wireless Wide Area Network (WWAN) signal transmission performance, and the like, and further improve stability and reliability of signal transmission in the data driver.

For example, the driving display order of the first pixel row and the second pixel row may be adjacent in time, that is, after the first pixel row is driven to display, the next pixel row driven to display in the display panel is the second pixel row. For example, the first pixel row and the second pixel row may be two pixel rows adjacently arranged in a first direction (e.g., a column direction).

Next, an embodiment of the present disclosure exemplifies a control method of a data driver for a display panel provided by an embodiment of the present disclosure, taking the schematic structure of the display panel shown in fig. 2 to 4 as an example. However, it should be noted that the embodiments of the present disclosure include but are not limited thereto.

For example, in the above embodiments of the present disclosure, m is an integer greater than 1, for example, m may take a value of 2, 3, 4, 5, and so on, that is, a plurality of sub-pixels included in each pixel row may be divided into, for example, 2 groups, 3 groups, 4 groups, 5 groups, and so on.

For example, taking m — 3 as an example, that is, taking an example that a plurality of sub-pixels included in each pixel row of a display panel are divided into 3 groups, a control method of a data driver for a display panel provided by an embodiment of the present disclosure is described in detail with reference to the display panels shown in fig. 2 to 4.

Accordingly, when m is equal to 3, a first data comparison signal, a second data comparison signal, and a third data comparison signal may be obtained, i is an integer, i is greater than 0 and less than or equal to 3, and i takes values of 1, 2, and 3, respectively.

Fig. 2 is a schematic structural diagram of a display panel according to some embodiments of the present disclosure, and fig. 3 is a schematic structural diagram of another display panel according to some embodiments of the present disclosure. It should be noted that, compared to the display panel 101 shown in fig. 2, in the display panel 102 shown in fig. 3, except that the relative arrangement positions of the two sub-pixels PX connected to the same data line DL in the two pixel rows adjacently arranged in the first direction R1 with respect to the data line DL in the second direction R2 are different, other structures, functions, or implementation manners are substantially the same or similar, and repeated descriptions are omitted.

For example, as shown in fig. 2, the first pixel row PXR1 and the second pixel row PXR2 may be two pixel rows arranged adjacently in the first direction R1 in the display panel 101, each subpixel PX (e.g., subpixels PX11 to PX16) in the first pixel row PXR1 is arranged in sequence in the second direction R2, and each subpixel PX (e.g., subpixels PX21 to PX26) in the second pixel row PXR2 is arranged in sequence in the second direction R2.

For example, each sub-pixel PX (e.g., sub-pixels PX11 to PX16) in the first pixel row PXR1 may be controlled by the same gate line to receive the same scan signal; each of the sub-pixels PX (e.g., sub-pixels PX21 to PX26) in the second pixel row PXR2 may be controlled by another same gate line to receive the same scan signal.

For example, after a display electric signal OUTPT such as a display voltage or a display current is applied to each sub-pixel PX in the first pixel row PXR1 via the plurality of data lines DL (e.g., data lines DL1 to DL6) to drive and display each sub-pixel PX in the first pixel row PXR1, a display electric signal OUTPT is applied to each sub-pixel PX in the second pixel row PXR2 via the plurality of data lines DL to drive and display each sub-pixel PX in the second pixel row PXR 2.

Taking the sub-pixels PX11 to PX16 included in the first pixel row PXR1 and the sub-pixels PX21 to PX26 included in the second pixel row PXR2 as an example, assuming that the number of the plurality of sub-pixels PX included in the first pixel row PXR1 and the number of the plurality of sub-pixels PX included in the second pixel row PXR2 are both 6, that is, (3 × 2) with m being 3 and n being 2, the (3 × j + i) th sub-pixel PX in the first pixel row PXR1 belongs to the i-th group of sub-pixels in the first pixel row PXR1 and the (3 × j + i) th sub-pixel PX in the second pixel row PXR2 belongs to the i-th group of sub-pixels in the second pixel row PXR 2; the ith data comparison signal represents a comparison relationship between the first display data for causing the (3 × j + i) th sub-pixel PX in the first pixel row PXR1 to display and the second display data for causing the (3 × j + i) th sub-pixel PX in the second pixel row PXR2 to display; correspondingly, j is more than or equal to 0 and less than 2, j is an integer, and j takes values of 0 and 1 respectively.

For example, taking the sub-pixels PX11 to PX16 included in the first pixel row PXR1 and the sub-pixels PX21 to PX26 included in the second pixel row PXR2 as examples, it is assumed that the sub-pixel PX11 is the first sub-pixel in the first pixel row PXR1 and the sub-pixel PX21 is the first sub-pixel in the second pixel row PXR 2: the first subpixel PX11(i ═ 1, j ═ 0) and the fourth subpixel PX14(i ═ 1, j ═ 1) in the first pixel row PXR1 belong to the first group of subpixels in the first pixel row PXR1, and the first subpixel PX21(i ═ 1, j ═ 0) and the fourth subpixel PX24(i ═ 1, j ═ 1) in the second pixel row PXR2 belong to the first group of subpixels in the second pixel row PXR 2; the second subpixel PX12(i ═ 2, j ═ 0) and the fifth subpixel PX15(i ═ 2, j ═ 1) in the first pixel row PXR1 belong to the second group of subpixels in the first pixel row PXR1, and the second subpixel PX22(i ═ 2, j ═ 0) and the fifth subpixel PX25(i ═ 2, j ═ 1) in the second pixel row PXR2 belong to the second group of subpixels in the second pixel row PXR 2; the third subpixel PX13(i ═ 3, j ═ 0) and the sixth subpixel PX16(i ═ 3, j ═ 1) in the first pixel row PXR1 belong to the third group of subpixels in the first pixel row PXR1, and the third subpixel PX23(i ═ 3, j ═ 0) and the sixth subpixel PX26(i ═ 3, j ═ 1) in the second pixel row PXR2 belong to the third group of subpixels in the second pixel row PXR 2; and so on.

For example, the first data comparison signal represents a comparison relationship between first display data for causing the sub-pixel PX11 to display and second display data for causing the sub-pixel PX21 to display, and a comparison relationship between the first display data for causing the sub-pixel PX14 to display and the second display data for causing the sub-pixel PX24 to display; the second data comparison signal represents a comparison relationship between the first display data for causing the sub-pixel PX12 to display and the second display data for causing the sub-pixel PX22 to display, and a comparison relationship between the first display data for causing the sub-pixel PX15 to display and the second display data for causing the sub-pixel PX25 to display; the third data comparison signal represents a comparison relationship between the first display data for causing the sub-pixel PX13 to display and the second display data for causing the sub-pixel PX23 to display, and a comparison relationship between the first display data for causing the sub-pixel PX16 to display and the second display data for causing the sub-pixel PX26 to display.

For example, taking the first group of sub-pixels PX11 and PX14 in the first pixel row PXR1 and the first group of sub-pixels PX21 and PX24 in the second pixel row PXR2 as an example, the sub-pixel PX11 in the first pixel row PXR1 shares the same data line DL1 in the display panel 101 with the sub-pixel PX21 in the second pixel row PXR2 to apply a first display electric signal corresponding to the first display data to the sub-pixel PX11 through the data line DL1 and apply a second display electric signal corresponding to the second display data to the sub-pixel PX21, respectively; the sub-pixels PX14 in the first pixel row PXR1 and the sub-pixels PX24 in the second pixel row PXR2 share the same data line DL4 in the display panel 101, so that a first display electric signal corresponding to first display data is applied to the sub-pixels PX14 and a second display electric signal corresponding to second display data is applied to the sub-pixels PX24 through the data line DL4, respectively. The connection manner between the other groups of sub-pixels in the first pixel row PXR1 and the second pixel row PXR2 and the data line DL is similar, and is not described herein again.

For example, taking the first group of sub-pixels PX11 and PX14 in the first pixel row PXR1 and the first group of sub-pixels PX21 and PX24 in the second pixel row PXR2 as examples, in the display panel 101 shown in fig. 2, the sub-pixel PX11 in the first pixel row PXR1 and the sub-pixel PX21 in the second pixel row PXR2 are respectively located on both sides of the same connected data line DL1 in the second direction R2, for example, the sub-pixel PX11 is located on the right side of the data line DL1, and the sub-pixel PX21 is located on the left side of the data line DL 1; the sub-pixels PX14 in the first pixel row PXR1 and the sub-pixels PX24 in the second pixel row PXR2 are respectively located on both sides of the same connected data line DL4 in the second direction R2, for example, the sub-pixels PX14 are located on the right side of the data line DL4, and the sub-pixels PX24 are located on the left side of the data line DL 4.

In some other embodiments of the present disclosure, for example, taking the display panel 102 shown in fig. 3 as an example, the sub-pixel PX11 in the first pixel row PXR1 and the sub-pixel PX21 in the second pixel row PXR2 may also be both located on the same side of the same connected data line DL1 in the second direction R2, for example, the sub-pixel PX11 and the sub-pixel PX21 are both located on the right side of the data line DL 1; the sub-pixels PX14 in the first pixel row PXR1 and the sub-pixels PX24 in the second pixel row PXR2 may also be both located on the same side of the same connected data line DL4 in the second direction R2, for example, the sub-pixels PX14 and the sub-pixels PX24 are both located on the right side of the data line DL 4.

In some other embodiments of the present disclosure, the sub-pixels PX11 in the first pixel row PXR1 and the sub-pixels PX21 in the second pixel row PXR2 may be both located on the left side of the data line DL1 in the second direction R2, and the sub-pixels PX14 in the first pixel row PXR1 and the sub-pixels PX24 in the second pixel row PXR2 may be both located on the left side of the data line DL4 in the second direction R2.

In some other embodiments of the present disclosure, the sub-pixels PX11 in the first pixel row PXR1 and the sub-pixels PX21 in the second pixel row PXR2 may be both located on the left side and the right side of the data line DL1 in the second direction R2, and the sub-pixels PX14 in the first pixel row PXR1 and the sub-pixels PX24 in the second pixel row PXR2 may be both located on the left side and the right side of the data line DL4 in the second direction R2, which is not particularly limited by the embodiments of the present disclosure.

It should be noted that, taking the sub-pixel PX11 and the sub-pixel PX21 as an example, compared with the display panel 101 shown in fig. 2, the display panel 102 shown in fig. 3 has substantially the same or similar structure, function, implementation manner, and the like except that the relative arrangement positions of the sub-pixel PX11 and the sub-pixel PX21 with respect to the data line DL1 are different, and repeated descriptions are omitted.

For example, in the display panel 101 shown in fig. 2 and the display panel 102 shown in fig. 3, the sub-pixels PX (e.g., the sub-pixels PX11 to PX16) in the first pixel row PXR1 may be sequentially arranged in an arrangement order of a first color sub-pixel (e.g., for providing light of a first color), a second color sub-pixel (e.g., for providing light of a second color), a third color sub-pixel (e.g., for providing light of a third color), a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; each sub-pixel PX (e.g., sub-pixels PX21 to PX26) in the second pixel row PXR2 may be sequentially arranged in the order of the third color sub-pixel, the first color sub-pixel, the second color sub-pixel, the third color sub-pixel, the first color sub-pixel, and the second color sub-pixel.

For example, when the display panel performs, for example, low voltage domain display, for example, each sub-pixel in the display panel is used to provide light of the same luminance or gray scale, the first display data for causing the first group of sub-pixels (for example, sub-pixels PX11 and PX14) in the first pixel row PXR1 to display may be the same as the second display data for causing the first group of sub-pixels (for example, sub-pixels PX21 and PX24) in the second pixel row PXR2 to display; the first display data for causing the second group of sub-pixels (e.g., sub-pixels PX12 and PX15) in the first pixel row PXR1 to display may be the same as the second display data for causing the second group of sub-pixels (e.g., sub-pixels PX22 and PX25) in the second pixel row PXR2 to display; the first display data for causing the third group of subpixels (e.g., subpixels PX13 and PX16) in the first pixel row PXR1 to display may be the same as the second display data for causing the third group of subpixels (e.g., subpixels PX23 and PX26) in the second pixel row PXR2 to display.

For example, in the display panel 101 shown in fig. 2 and the display panel 102 shown in fig. 3, the sub-pixels PX (e.g., the sub-pixels PX11 to PX16) in the first pixel row PXR1 may be sequentially arranged in an arrangement order of the first color sub-pixel, the second color sub-pixel, the third color sub-pixel, the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel; each of the sub-pixels PX (e.g., sub-pixels PX21 to PX26) in the second pixel row PXR2 may be all provided as the same color sub-pixel or a non-light emitting sub-pixel.

For example, when the display panel performs, for example, low-voltage domain display, first display data for causing a first group of sub-pixels (e.g., sub-pixels PX11 and PX14) in the first pixel row PXR1 to display may be opposite to second display data for causing a first group of sub-pixels (e.g., sub-pixels PX21 and PX24) in the second pixel row PXR2 to display; the first display data for causing the second group of subpixels (e.g., subpixels PX12 and PX15) in the first pixel row PXR1 to display may be the inverse of the second display data for causing the second group of subpixels (e.g., subpixels PX22 and PX25) in the second pixel row PXR2 to display; the first display data for causing the third group of subpixels (e.g., subpixels PX13 and PX16) in the first pixel row PXR1 to display may be the inverse of the second display data for causing the third group of subpixels (e.g., subpixels PX23 and PX26) in the second pixel row PXR2 to display.

For example, in the display panel 101 shown in fig. 2 and the display panel 102 shown in fig. 3, the sub-pixels PX (e.g., the sub-pixels PX11 to PX16) in the first pixel row PXR1 may be sequentially arranged in the order of arrangement of the non-emitting sub-pixel, the first color sub-pixel, the non-emitting sub-pixel, the second color sub-pixel, the non-emitting sub-pixel, and the third color sub-pixel; the sub-pixels PX (e.g., sub-pixels PX21 to PX26) in the second pixel row PXR2 may be sequentially arranged in the order of arrangement of the non-emitting sub-pixel, the second color sub-pixel, the non-emitting sub-pixel, the third color sub-pixel, the non-emitting sub-pixel, and the first color sub-pixel.

For example, when the display panel performs, for example, low-voltage domain display, first display data for causing a first group of sub-pixels (e.g., sub-pixels PX11 and PX14) in the first pixel row PXR1 to display may be the same as second display data for causing a first group of sub-pixels (e.g., sub-pixels PX21 and PX24) in the second pixel row PXR2 to display; the first display data for causing the second group of sub-pixels (e.g., sub-pixels PX12 and PX15) in the first pixel row PXR1 to display may be the same as the second display data for causing the second group of sub-pixels (e.g., sub-pixels PX22 and PX25) in the second pixel row PXR2 to display; the first display data for causing the third group of subpixels (e.g., subpixels PX13 and PX16) in the first pixel row PXR1 to display may be the same as the second display data for causing the third group of subpixels (e.g., subpixels PX23 and PX26) in the second pixel row PXR2 to display.

For example, in the display panel 101 shown in fig. 2 and the display panel 102 shown in fig. 3, the sub-pixels PX (e.g., the sub-pixels PX11 to PX16) in the first pixel row PXR1 may be sequentially arranged in the order of arrangement of the non-emitting sub-pixel, the first color sub-pixel, the non-emitting sub-pixel, the second color sub-pixel, the non-emitting sub-pixel, and the third color sub-pixel; the sub-pixels PX (e.g., sub-pixels PX21 to PX26) in the second pixel row PXR2 may be sequentially arranged in the order of the arrangement of the third color sub-pixel, the non-light emitting sub-pixel, the first color sub-pixel, the non-light emitting sub-pixel, the second color sub-pixel, and the non-light emitting sub-pixel.

For example, in the display panel 101 shown in fig. 2 and the display panel 102 shown in fig. 3, the sub-pixels PX (e.g., the sub-pixels PX11 to PX16) in the first pixel row PXR1 may be sequentially arranged in the order of arrangement of the non-emitting sub-pixel, the first color sub-pixel, the non-emitting sub-pixel, and the first color sub-pixel; the sub-pixels PX (e.g., sub-pixels PX21 to PX26) in the second pixel row PXR2 may be sequentially arranged in the order of the first color sub-pixel, the non-light emitting sub-pixel, the first color sub-pixel, the non-light emitting sub-pixel, and the non-light emitting sub-pixel.

For example, when the display panel performs, for example, low-voltage domain display, first display data for causing a first group of sub-pixels (e.g., sub-pixels PX11 and PX14) in the first pixel row PXR1 to display may be opposite to second display data for causing a first group of sub-pixels (e.g., sub-pixels PX21 and PX24) in the second pixel row PXR2 to display; the first display data for causing the second group of sub-pixels (e.g., sub-pixels PX12 and PX15) in the first pixel row PXR1 to display may be the same as the second display data for causing the second group of sub-pixels (e.g., sub-pixels PX22 and PX25) in the second pixel row PXR2 to display; the first display data for causing the third group of subpixels (e.g., subpixels PX13 and PX16) in the first pixel row PXR1 to display may be the inverse of the second display data for causing the third group of subpixels (e.g., subpixels PX23 and PX26) in the second pixel row PXR2 to display.

For example, in the display panel 101 shown in fig. 2 and the display panel 102 shown in fig. 3, the sub-pixels PX (e.g., sub-pixels PX11 to PX16) in the first pixel row PXR1 may be arranged in the order of the first color sub-pixel, the second color sub-pixel, the non-emitting sub-pixel, and the third color sub-pixel; the sub-pixels PX (e.g., sub-pixels PX21 to PX26) in the second pixel row PXR2 may be sequentially arranged in the order of arrangement of the non-emitting sub-pixel, the third color sub-pixel, the first color sub-pixel, and the second color sub-pixel.

For example, when the display panel performs, for example, low-voltage domain display, first display data for causing a first group of sub-pixels (e.g., sub-pixels PX11 and PX14) in the first pixel row PXR1 to display may be opposite to second display data for causing a first group of sub-pixels (e.g., sub-pixels PX21 and PX24) in the second pixel row PXR2 to display; the first display data for causing the second group of subpixels (e.g., subpixels PX12 and PX15) in the first pixel row PXR1 to display may be the inverse of the second display data for causing the second group of subpixels (e.g., subpixels PX22 and PX25) in the second pixel row PXR2 to display; the first display data for causing the third group of subpixels (e.g., subpixels PX13 and PX16) in the first pixel row PXR1 to display may be the same as the second display data for causing the third group of subpixels (e.g., subpixels PX23 and PX26) in the second pixel row PXR2 to display.

For example, the first color, the second color, and the third color may be red, green, blue, white, or other desired display colors, respectively, which is not particularly limited in the embodiments of the present disclosure.

It should be noted that, in some other embodiments of the present disclosure, the sub-pixels PX in the first pixel row PXR1 and the second pixel row PXR2 may be arranged in sequence in other suitable arrangement orders, and the embodiments of the present disclosure are not limited in this respect.

Fig. 4 is a schematic structural diagram of another display panel according to some embodiments of the disclosure.

For example, as shown in fig. 4, the first pixel row PXR1 and the second pixel row PXR2 may be two pixel rows arranged adjacently in the first direction R1 in the display panel 103, each subpixel PX (e.g., subpixels PX1 to PX10) in the first pixel row PXR1 is arranged in sequence in the second direction R2, and each subpixel PX (e.g., subpixels PX1 to PX10) in the second pixel row PXR2 is arranged in sequence in the second direction R2.

For example, after a display electric signal OUTPT such as a display voltage or a display current is applied to each sub-pixel PX in the first pixel row PXR1 via a plurality of data lines DL (e.g., data lines DL1 to DL5) to drive and display each sub-pixel PX in the first pixel row PXR1, a display electric signal OUTPT is applied to each sub-pixel PX in the second pixel row PXR2 via the plurality of data lines DL to drive and display each sub-pixel PX in the second pixel row PXR 2.

For example, taking m — 3 and n — 2 as an example, that is, taking the plurality of subpixels PX included in each of the first pixel row PXR1 and the second pixel row PXR2 of the display panel 103 as each being divided into 3 groups, and assuming that the number of the plurality of subpixels PX included in the first pixel row PXR1 and the number of the plurality of subpixels PX included in the second pixel row PXR2 are both 12, that is, (2 × 3 × 2), the (2 × 3 × j +2 × i-1) th and (2 × 3 × j +2 × i) th subpixels PX in the first pixel row PXR1 belong to the i-th group of subpixels in the first pixel row PXR1, and the (2 × 3 × j +2 × i-1) th and (2 × 3 × j +2 × i) th subpixels PX in the second pixel row PXR2 belong to the i-th group of subpixels PXR2 in the second pixel row PXR 2; the ith data comparison signal represents a comparison relationship between first display data for causing the (2 × 3 × j +2 × i-1) th and (2 × 3 × j +2 × i) th sub-pixels PX in the first pixel row PXR1 to display and second display data for causing the (2 × 3 × j +2 × i-1) th and (2 × 3 × j +2 × i) th sub-pixels PX in the second pixel row PXR2 to display; correspondingly, i is more than 0 and less than or equal to 3, i is an integer, i takes values of 1, 2 and 3 respectively, j is more than or equal to 0 and less than 2, j is an integer, and j takes values of 0 and 1 respectively.

For example, assume that the first subpixel in the first pixel row PXR1 is subpixel PX1, and the first subpixel in the second pixel row PXR2 is subpixel PX 1: a subpixel PX1 (i.e., (2 × 3 × 0+2 × 1-1) subpixel, i ═ 1, j ═ 0), a subpixel PX2 (i.e., (2 × 3 × 0+2 × 1) subpixel, i ═ 1, j ═ 0), a subpixel PX7 (i.e., (2 × 3 × 1+2 × 1-1) subpixel, i ═ 1, j ═ 1), a subpixel PX8 (i.e., (2 × 3 × 1+2 × 1) subpixel, i ═ 1, j ═ 1) belongs to the first group of subpixels in the first pixel row PXR1, a subpixel PX1 (i.e., (2 × 3 × 0+2 × 1-1) in the second pixel row PXR 2(i ═ 1), i × 0 × 1, j × ═ 0, i × 0 × 3 × 1, i × 0 ═ 2 × 1 × 3 × 1, i × 1 ═ 2 × 1, i × 1 ═ 2 × 1 —, a subpixel (PX 1) in the first pixel row PXR 3558), i ═ 1, j ═ 1), subpixel PX8 (i.e., the (2 × 3 × 1+2 × 1) th subpixel, i ═ 1, j ═ 1) belongs to the first group of subpixels in second pixel row PXR 2; a subpixel PX3 (i.e., (2 × 3 × 0+2 × 2-1) subpixel, i ═ 2, j ═ 0), a subpixel PX4 (i.e., (2 × 3 × 0+2 × 2) subpixel, i ═ 2, j ═ 0), a subpixel PX9 (i.e., (2 × 3 × 1+2 × 2-1) subpixel, i ═ 2, j ═ 1), a subpixel PX10 (i.e., (2 × 3 × 0+2 × 2) subpixel, i ═ 2, j ═ 1) belongs to the second group of subpixels in the first pixel row PXR1, a subpixel PX3 (i.e., (2 × 3 × 0+2 × 2-1) in the second pixel row PXR2, (i ═ 2 × 0, j ═ 2 × 0), a subpixel PX 28 × 0, i × ═ 2 × 2, i × 0 ═ 2 × 2, i × 3 × 2 ═ 2 × 380, i ═ 2 × 2 — (PX 3 × 2 — + 3, 2 — (PX 3) of subpixels, i — + 3 × 2 ═ 2 — (2) in the first pixel row PXR 3558, i ═ 2, j ═ 1), subpixel PX10 (i.e., the (2 × 3 × 1+2 × 2) th subpixel, i ═ 2, j ═ 1) belongs to the second group of subpixels in the second pixel row PXR 2; a subpixel PX5 (i.e., (2 × 3 × 0+2 × 3-1) subpixel, i ═ 3, j ═ 0), a subpixel PX6 (i.e., (2 × 3 × 0+2 × 3) subpixel, i ═ 3, j ═ 0), a subpixel PX11 (i.e., (2 × 3 × 1+2 × 3-1) subpixel, i ═ 3, j ═ 1, not shown), a subpixel PX12 (i.e., (2 × 3 × 1+2 × 3) subpixel, i ═ 3, j ═ 1, not shown) belongs to a third group of subpixels in the first pixel row PXR1, a subpixel 5 (i.e., (2 × 3 × 0+2 × 3-1) in the second pixel row PXR 3890, i × 3-1), a subpixel PX 380 (3 × 3), a subpixel PX3 × 1(i ═ 3 × 3) subpixel, i ═ 3 × 1, i ═ 3 × 3, i — (PX 3) and a subpixel PX3 × 1, i — (PX 3 × 3) in the first pixel row PXR 3558, i ═ 3, j ═ 1, not shown in the figure), the subpixel PX12 (i.e., the (2 × 3 × 1+2 × 3) th subpixel, i ═ 3, j ═ 1, not shown in the figure) belongs to the third group of subpixels in the second pixel row PXR 2; and so on.

For example, taking as an example the sub-pixels PX1 to PX6 included in the first pixel row PXR1 and the sub-pixels PX1 to PX6 included in the second pixel row PXR2, the first data comparison signal represents a comparison relationship between first display data for causing the sub-pixels PX1 and PX2 in the first pixel row PXR1 to display and second display data for causing the sub-pixels PX1 and PX2 in the second pixel row PXR2 to display; the second data comparison signal represents a comparison relationship between first display data for causing the sub-pixels PX3 and PX4 in the first pixel row PXR1 to display and second display data for causing the sub-pixels PX3 and PX4 in the second pixel row PXR2 to display; the third data comparison signal represents a comparison relationship between the first display data for causing the sub-pixels PX5 and PX6 in the first pixel row PXR1 to display and the second display data for causing the sub-pixels PX5 and PX6 in the second pixel row PXR2 to display; and so on.

For example, taking the sub-pixels PX1 and PX2 in the first pixel row PXR1 and the sub-pixels PX1 and PX2 in the second pixel row PXR2 as an example, the sub-pixels PX1 and PX2 in the first pixel row PXR1 and the sub-pixels PX1 and PX2 in the second pixel row PXR2 share the same data line DL1 in the display panel 103 to apply a first display electric signal corresponding to the first display data to the sub-pixels PX1 and PX2 in the first pixel row PXR1 and to apply a second display electric signal corresponding to the second display data to the sub-pixels PX1 and PX2 in the second pixel row PXR2, respectively, through the data line DL 1.

For example, the sub-pixels PX1 and PX2 in the first pixel row PXR1 may be respectively controlled by two different gate lines to respectively receive different scan signals. For example, the two gate lines may be respectively disposed at opposite sides of the display region of the display panel 103 to implement a double-side driving display of the display panel 103. For example, the sub-pixels PX1 and PX2 of the second pixel row PXR2 may be respectively controlled by two different gate lines to respectively receive different scan signals. For example, the two gate lines may be respectively disposed at opposite sides of the display region of the display panel 103 to implement a double-side driving display of the display panel 103.

For example, taking the sub-pixels PX1 and PX2 in the first pixel row PXR1 and the sub-pixels PX1 and PX2 in the second pixel row PXR2 as examples, in the display panel 103 shown in fig. 4, the sub-pixels PX1 and PX2 in the first pixel row PXR1 and the sub-pixels PX1 and PX2 in the second pixel row PXR2 are respectively located on both sides of the same connected data line DL1 in the second direction R2. For example, the subpixels PX1 and PX2 in the first pixel row PXR1 are both located on the right side of the data line DL1, and the subpixels PX1 and PX2 in the second pixel row PXR2 are both located on the left side of the data line DL 1.

It should be noted that, in some other embodiments of the present disclosure, the sub-pixels PX1 and PX2 in the first pixel row PXR1 and the sub-pixels PX1 and PX2 in the second pixel row PXR2 may also be both located on the same side of the same data line DL1 connected in the second direction R2, for example, both located on the right side or the left side of the data line DL1, or both located on the left side and the right side, and the like, which is not limited in this embodiment of the present disclosure.

For example, the sub-pixels PX1, PX3, PX5, PX7, PX9, etc. in the first pixel row PXR1 are all controlled by the same gate line, and the sub-pixels PX2, PX4, PX6, PX8, PX10, etc. are all controlled by another same gate line, so that the two sub-pixels PX connected to the same data line DL in the first pixel row PXR1 may sequentially receive the first display electrical signal corresponding to the first display data through the data lines DL, respectively; for example, the sub-pixels PX1, PX3, PX5, PX7, PX9, etc. in the second pixel row PXR2 are all controlled by the same gate line, and the sub-pixels PX2, PX4, PX6, PX8, PX10, etc. are all controlled by the same gate line, so that the two sub-pixels PX connected to the same data line DL in the second pixel row PXR2 can respectively and sequentially receive the second display electrical signal corresponding to the second display data through the data line DL.

For example, in the display panel 103 shown in fig. 4, the sub-pixels PX (e.g., the sub-pixels PX1 to PX6) in the first pixel row PXR1 may be sequentially arranged in an arrangement order of a first color sub-pixel (e.g., for providing light of a first color), a non-light emitting sub-pixel, a second color sub-pixel (e.g., for providing light of a second color), a non-light emitting sub-pixel, a third color sub-pixel (e.g., for providing light of a third color), and a non-light emitting sub-pixel; the sub-pixels PX (e.g., sub-pixels PX1 to PX6) in the second pixel row PXR2 may be sequentially arranged in the order of arrangement of the non-emitting sub-pixel, the second color sub-pixel, the non-emitting sub-pixel, the third color sub-pixel, the non-emitting sub-pixel, and the first color sub-pixel.

For example, when the display panel performs, for example, low-voltage domain display, taking as an example that the sub-pixels PX1 and PX2 in the first pixel row PXR1 and the sub-pixels PX1 and PX2 in the second pixel row PXR2 are sequentially driven to display, first display data for causing the sub-pixels PX1 and PX2 in the first pixel row PXR1 to display are opposite to each other, first display data for causing the sub-pixels PX2 in the first pixel row PXR1 to display are the same as second display data for causing the sub-pixels PX1 in the second pixel row PXR2 to display, and second display data for causing the sub-pixels PX1 and PX2 in the second pixel row PXR2 to display are opposite to each other. The comparison relationship between the first display data and the second display data corresponding to the sub-pixels PX in the other groups of sub-pixels is similar to that, and is not described herein again.

For example, in the display panel 103 shown in fig. 4, the sub-pixels PX (e.g., sub-pixels PX1 to PX6) in the first pixel row PXR1 may be sequentially arranged in the order of arrangement of the first color sub-pixel, the non-light emitting sub-pixel, the second color sub-pixel, the non-light emitting sub-pixel, the third color sub-pixel, and the non-light emitting sub-pixel; the sub-pixels PX (e.g., sub-pixels PX1 to PX6) in the second pixel row PXR2 may be sequentially arranged in the order of the arrangement of the third color sub-pixel, the non-light emitting sub-pixel, the first color sub-pixel, the non-light emitting sub-pixel, the second color sub-pixel, and the non-light emitting sub-pixel.

For example, when the display panel performs, for example, low-voltage domain display, taking as an example that the sub-pixels PX1 and PX2 in the first pixel row PXR1 and the sub-pixels PX1 and PX2 in the second pixel row PXR2 are sequentially driven to display, first display data for causing the sub-pixels PX1 and PX2 in the first pixel row PXR1 to display are opposite to each other, first display data for causing the sub-pixels PX2 in the first pixel row PXR1 to display is opposite to second display data for causing the sub-pixels PX1 in the second pixel row PXR2 to display, and second display data for causing the sub-pixels PX1 and PX2 in the second pixel row PXR2 to display are opposite to each other. The comparison relationship between the first display data and the second display data corresponding to the sub-pixels PX in the other groups of sub-pixels is similar to that, and is not described herein again.

For example, in the display panel 103 shown in fig. 4, the sub-pixels PX (e.g., sub-pixels PX1 to PX6) in the first pixel row PXR1 may be sequentially arranged in the order of arrangement of the non-emitting sub-pixel, the first color sub-pixel, and the non-emitting sub-pixel; the sub-pixels PX (e.g., sub-pixels PX1 to PX6) in the second pixel row PXR2 may be sequentially arranged in the order of the first color sub-pixel, the non-light emitting sub-pixel, the first color sub-pixel, the non-light emitting sub-pixel, and the non-light emitting sub-pixel.

For example, when the display panel performs, for example, low-voltage domain display, taking as an example that the sub-pixels PX1 and PX2 in the first pixel row PXR1 and the sub-pixels PX1 and PX2 in the second pixel row PXR2 are sequentially driven to display, first display data for causing the sub-pixels PX1 and PX2 in the first pixel row PXR1 to display are opposite to each other, first display data for causing the sub-pixels PX2 in the first pixel row PXR1 to display are the same as second display data for causing the sub-pixels PX1 in the second pixel row PXR2 to display, and second display data for causing the sub-pixels PX1 and PX2 in the second pixel row PXR2 to display are opposite to each other. Taking as an example that the sub-pixels PX3 and PX4 in the first pixel row PXR1 and the sub-pixels PX3 and PX4 in the second pixel row PXR2 are sequentially driven to display, the first display data for causing the sub-pixels PX3 and PX4 in the first pixel row PXR1 to display are identical to each other, the first display data for causing the sub-pixels PX4 in the first pixel row PXR1 to display are identical to the second display data for causing the sub-pixels PX3 in the second pixel row PXR2 to display, and the second display data for causing the sub-pixels PX3 and PX4 in the second pixel row PXR2 to display are opposite to each other. Taking as an example that the sub-pixels PX5 and PX6 in the first pixel row PXR1 and the sub-pixels PX5 and PX6 in the second pixel row PXR2 are sequentially driven to display, the first display data for causing the sub-pixels PX5 and PX6 in the first pixel row PXR1 to display are opposite to each other, the first display data for causing the sub-pixels PX6 in the first pixel row PXR1 to display are the same as the second display data for causing the sub-pixels PX5 in the second pixel row PXR2 to display, and the second display data for causing the sub-pixels PX5 and PX6 in the second pixel row PXR2 to display are the same as each other.

For example, in the display panel 103 shown in fig. 4, the sub-pixels PX (e.g., the sub-pixels PX1 to PX6) in the first pixel row PXR1 may be sequentially arranged in the order of arrangement of the first color sub-pixel, the non-light emitting sub-pixel, the second color sub-pixel, and the third color sub-pixel; the sub-pixels PX (e.g., sub-pixels PX1 to PX6) in the second pixel row PXR2 may be sequentially arranged in the order of arrangement of the non-emitting sub-pixel, the second color sub-pixel, the third color sub-pixel, and the first color sub-pixel.

For example, when the display panel performs, for example, low-voltage domain display, taking as an example that the sub-pixels PX1 and PX2 in the first pixel row PXR1 and the sub-pixels PX1 and PX2 in the second pixel row PXR2 are sequentially driven to display, first display data for causing the sub-pixels PX1 and PX2 in the first pixel row PXR1 to display are opposite to each other, first display data for causing the sub-pixels PX2 in the first pixel row PXR1 to display is the same as second display data for causing the sub-pixels PX1 in the second pixel row PXR2 to display, and second display data for causing the sub-pixels PX1 and PX2 in the second pixel row PXR2 to display is the same as each other. Taking as an example that the sub-pixels PX3 and PX4 in the first pixel row PXR1 and the sub-pixels PX3 and PX4 in the second pixel row PXR2 are sequentially driven to display, the first display data for causing the sub-pixels PX3 and PX4 in the first pixel row PXR1 to display are identical to each other, the first display data for causing the sub-pixels PX4 in the first pixel row PXR1 to display are identical to the second display data for causing the sub-pixels PX3 in the second pixel row PXR2 to display, and the second display data for causing the sub-pixels PX3 and PX4 in the second pixel row PXR2 to display are opposite to each other. Taking as an example that the sub-pixels PX5 and PX6 in the first pixel row PXR1 and the sub-pixels PX5 and PX6 in the second pixel row PXR2 are sequentially driven to display, the first display data for causing the sub-pixels PX5 and PX6 in the first pixel row PXR1 to display are identical to each other, the first display data for causing the sub-pixels PX6 in the first pixel row PXR1 to display are identical to the second display data for causing the sub-pixels PX5 in the second pixel row PXR2 to display, and the second display data for causing the sub-pixels PX5 and PX6 in the second pixel row PXR2 to display are identical to each other.

For example, the first color, the second color, and the third color may be red, green, blue, white, or other desired display colors, respectively, and embodiments of the present disclosure are not limited in this regard.

In the following, taking as an example the data comparison signal representing the comparison relationship between the first display data for causing one sub-pixel PX in the first pixel row PXR1 to be displayed and the second display data for causing the corresponding sub-pixel PX in the second pixel row PXR2 to be displayed in each of the above-described embodiments, for example, the data comparison signal representing the comparison relationship between the first display data for causing the sub-pixel PX11 in the first pixel row PXR1 to be displayed and the second display data for causing the sub-pixel PX21 in the second pixel row PXR2 in the embodiments shown in fig. 2 and 3, or the data comparison signal representing the comparison relationship between the first display data for causing the sub-pixels PX1 and PX2 in the first pixel row PXR1 to be displayed and the second display data for causing the sub-pixels PX1 and PX2 in the second pixel row PXR2 to be displayed in the embodiment shown in fig. 4, the embodiments of step S11 and step S12 will be specifically described.

Fig. 5 is a schematic flowchart of step S12 in a control method of a data driver according to some embodiments of the present disclosure.

As shown in fig. 5, in some embodiments of the present disclosure, the step S12 includes steps S121 and S122.

Step S121: in response to the data comparison signal indicating that the first display data and the second display data have a first comparison relationship therebetween, the second display data is obtained based on the first display data that has been buffered by the data driver, and the first comparison relationship includes whether the first display data is the same as or opposite to the second display data.

Step S122: the second display data is derived based on the input data signal for the second row of pixels received by the data driver in response to the data comparison signal indicating that the first display data and the second display data have a second comparison relationship therebetween different from the first comparison relationship.

For example, with respect to the above steps S121 and S122, by determining the comparison relationship between the first display data and the second display data, the data driver may be controlled to respectively implement the acquisition of the second display data in different manners. Therefore, the data drivers can work in different working states respectively, flexible control over working power consumption of the data drivers is facilitated, and use cost of the data drivers is further reduced.

For example, in the case that it is determined in step S121 that the first display data is the same as or opposite to the second display data, the data driver may be enabled to obtain the second display data according to the first display data already cached in the data driver, thereby helping to reduce power consumption required by the data driver in acquiring the second display data and reducing total system power consumption of the data driver.

For example, in the case where it is determined in step S122 that there is no identical or opposite comparison relationship between the first display data and the second display data, then an appropriate signal processing operation is performed on the input data signal corresponding to the second pixel row received by the data driver to obtain the desired second display data based on the input data signal.

Next, an embodiment of the present disclosure takes the workflow of the data driver shown in fig. 6 as an example, and exemplarily illustrates a control method of the data driver provided by the embodiment of the present disclosure. However, it should be noted that the embodiments of the present disclosure include but are not limited thereto.

Fig. 6 is a schematic diagram of a data driver according to some embodiments of the disclosure. As shown in fig. 6, the data driver 10 includes a physical layer processing module 110, a link layer processing module 120, and a lane array processing module 130.

For example, after the data driver 10 receives the input electrical signal inp provided by the timing controller, the input electrical signal inp sequentially passes through the physical layer processing block 110, the link layer processing block 120, and the lane array processing block 130. After the input electrical signal inp is sequentially signal-processed by the physical layer processing module 110, the link layer processing module 120, and the channel array processing module 130, a display electrical signal OUTPT for providing to the display panel is obtained, for example, the display electrical signal OUTPT may be a display voltage or a display current applied to the sub-pixels in each pixel row of the display panel, so as to drive each sub-pixel in the display panel to perform display.

For example, after receiving the input electrical signal inp provided by the timing controller, the phy layer processing module 110 performs phy layer processing on the input electrical signal inp to obtain a corresponding input data signal PDAT and an input clock signal PCLK, and transmits the obtained input data signal PDAT and the obtained input clock signal PCLK to the link layer processing module 120, respectively.

For example, the input electrical signal inp received by the data driver 10 and provided by the timing controller may be transmitted to the data driver 10 in a serial manner, or may also be transmitted to the data driver 10 in a parallel manner, or may also be transmitted in other suitable transmission manners, and the like, and the embodiment of the present disclosure is not particularly limited thereto.

For example, taking the example of the data driver 10 shown in fig. 7 as an example, when the input electrical signal inp is transmitted to the data driver 10 in a serial manner, that is, the input data signal PDAT and the input clock signal PCLK included in the input electrical signal inp are transmitted to the data driver 10 in a serial manner, the analog front terminal module 111 in the physical layer processing module 110 is configured to perform signal processing operations such as signal amplification, frequency conversion, modulation and demodulation, adjacent channel processing, or level adjustment and control on the input electrical signal inp to obtain a stable electrical signal suitable for the data driver 10, and provide the processed input electrical signal inp to other sub-modules in the physical layer processing module 110 for subsequent signal processing operations. For example, the input electrical signal inp processed by the front end module 111 is transmitted to the clock data recovery submodule 112, the clock data recovery submodule 112 performs recovery sampling on the processed input electrical signal inp, extracts the input data signal PDAT and the input clock signal PCLK from the processed input electrical signal inp, and then transmits the extracted input data signal PDAT and the extracted input clock signal PCLK to the subsequent link layer processing module 120.

For another example, taking the example of the data driver 10 shown in fig. 8 as an example, when the input electrical signal inp is transmitted to the data driver 10 in parallel, that is, the input electrical signal inp dat corresponding to the input data signal PDAT and the input electrical signal inclk corresponding to the input clock signal PCLK are transmitted to the data driver 10 through different signal transmission channels, respectively, the input electrical signal inp dat corresponding to the input data signal PDAT is transmitted to the data path sub-module 113 in the physical layer processing module 110, and the input electrical signal inclk corresponding to the input clock signal PCLK is transmitted to the clock path sub-module 114 in the physical layer processing module 110.

For example, the data path sub-module 113 performs signal processing operations such as signal amplification, frequency conversion, modulation and demodulation, adjacent channel processing, or level adjustment and control on the received input electrical signal INPDAT to obtain a stable electrical signal suitable for the data driver 10, performs recovery sampling on the electrical signal subjected to the signal processing operations, extracts a corresponding input data signal PDAT therefrom, and then transmits the extracted input data signal PDAT to the subsequent link layer processing module 120. The clock path sub-module 114 performs signal processing operations such as signal amplification, frequency conversion, modulation and demodulation, adjacent channel processing, or level adjustment and control on the received input electrical signal inclk to obtain a stable electrical signal suitable for the data driver 10, recovers and samples the electrical signal after the signal processing operations, extracts a corresponding input clock signal PCLK therefrom, and then transmits the extracted input clock signal PCLK to the subsequent link layer processing module 120.

It should be noted that, except that the transmission manner of the input electrical signal inp to the data driver 10 is different and the structure of the physical layer processing module 110 is different, other structures, functions, or implementations of the data driver 10 shown in fig. 7 and 8 are substantially the same or similar, and repeated descriptions are omitted.

For example, the input data signal PDAT transmitted by the physical layer processing module 110 to the link layer processing module 120 may be as shown in fig. 9. For example, the input data signals PDAT may include display data signals DSPDAT corresponding to respective pixel rows, such as first display data signals DSPDAT1 corresponding to a first pixel row, second display data signals DSPDAT2 corresponding to a second pixel row, third display data signals DSPDAT3 corresponding to a third pixel row, and so on … …. For example, as in the example described above, the display data signals DSPDAT may be combined with the clock signal and then transmitted together, and then separated from each other by the clock data recovery submodule 112.

For example, the input data signals PDAT further comprise packet control signals PACKDAT, such as first packet control signal PACKDAT1 corresponding to the first display data signals DSPDAT1, second packet control signal PACKDAT2 corresponding to the second display data signals DSPDAT2, third packet control signal PACKDAT3 corresponding to the third display data signals DSPDAT3, and so on … …. For example, the packet control signal PACKDAT is not sent in combination with the clock signal.

Thus, after identifying the packet control signal PACKDAT and the display data signal DSPDAT in the input data signal PDAT, the display data DAT identified from the display data signal DSPDAT can be respectively associated with the corresponding pixel rows according to the data control packet identified from the packet control signal PACKDAT.

For example, as shown in fig. 6, the link layer processing module 120 performs link layer processing on the received input data signal PDAT and the input clock signal PCLK, respectively, identifies display data DAT (and a data control packet) from the input data signal PDAT, identifies clock control data CLK from the input clock signal PCLK, and transmits the obtained display data DAT and clock control data CLK to the channel array processing module 130 after corresponding data processing (for example, formatting the display data DAT, etc.).

For example, as shown in fig. 7 and 8, the link layer processing module 120 may include a signal identification sub-module 121, a data control packet registration sub-module 122, and a display data formatting sub-module 123. The signal identification submodule 121 may be configured to perform identification processing on the input data signal PDAT and the input clock signal PCLK received from the physical layer processing module 110, respectively, to identify the display data DAT and the data control packet from the input data signal PDAT, and identify the clock control data CLK from the input clock signal PCLK. The data control packet registration submodule 122 may be configured to register a data control packet identified from the input data signal PDAT. The display data formatting sub-module 123 may be configured to perform operations such as formatting on the display data DAT identified from the input data signal PDAT, and then provide the display data DAT after signal processing such as formatting to the subsequent channel array processing module 130.

For example, as shown in fig. 6, the channel array processing module 130 may buffer the received display data DAT and the clock control data CLK, perform signal processing operations such as digital-to-analog conversion and operational amplification on the buffered display data DAT to obtain a display electrical signal OUTPT such as a display voltage or a display current for providing to the display panel, and then provide the obtained display electrical signal OUTPT to the display panel under the control of the clock control data CLK to drive each sub-pixel in the display panel for displaying.

For example, as shown in fig. 7 and 8 in combination, in at least one example, the channel array processing module 130 may include a first latch submodule 131 and a second latch submodule 132 which are cascaded, and the first latch submodule 131 and the second latch submodule 132 are used for buffering display data DAT to be provided to the display panel. For example, in the p-th duty cycle (e.g., clock cycle) of the channel array processing module 130, the first latch submodule 131 buffers the display data for the a-th pixel row, and the second latch submodule 132 buffers the display data for the a-1-th pixel row, where the display driving of the a-1-th pixel row precedes the a-th pixel row; in the next working cycle of the channel array processing module 130, i.e. the p +1 th working cycle, the first latch submodule 131 buffers the display data for the a +1 th pixel row, while the second latch submodule 132 buffers the display data for the a th pixel row, and so on. Therefore, the first latch submodule 131 and the second latch submodule 132 work in parallel with each other, and when the first latch submodule 131 samples and buffers the input display data, the second latch submodule 132 transfers the buffered display data to the next stage, thereby improving the working efficiency of the channel array processing module 130.

The channel array processing module 130 further includes a conversion processing sub-module 133, for example, the conversion processing sub-module 133 may be configured to perform signal processing operations, such as digital-to-analog conversion and operational amplification, on the buffered display data DAT to obtain a display electrical signal OUTPT, such as a display voltage or a display current, for being provided to the display panel. The channel array processing module 130 further includes a shift register submodule 134, and the shift register submodule 134 can be used for registering the clock control data CLK received by the channel array processing module 130.

It should be noted that, in the above embodiments of the present disclosure, the modules included in the data driver 10 and the sub-modules included in each module shown in fig. 6 to fig. 8 are only exemplary illustrations, the data driver 10 may further include other modules or sub-modules, each module may also include other sub-modules, and the like, and details regarding the structure, the function, and the like of the data driver 10 may refer to conventional designs in the art, and are not repeated herein.

For example, taking the data driver 10 shown in fig. 6 to 8 as an example, in some embodiments of the present disclosure, the electrical signal corresponding to the data comparison signal CMP may be included in the input electrical signal inp and provided to the data driver 10 by the timing controller.

For another example, in some other embodiments of the present disclosure, the electrical signal corresponding to the data comparison signal CMP may also be separately transmitted to the data driver 10 independently of the input electrical signal inp. For example, the electrical signal corresponding to the data comparison signal CMP may be provided by a timing controller, or may also be provided by other control devices or modules in signal connection with the data driver 10, and the like, which is not particularly limited by the embodiments of the present disclosure.

For example, taking as an example that an electrical signal corresponding to the data comparison signal CMP is transmitted included in the input electrical signal inp, a corresponding electrical signal of the data comparison signal CMP for indicating a comparison relationship between the first display data and the second display data may be transmitted together with the input data signal PDAT corresponding to the second pixel row, for example, with the second packet control signal PACKDAT2 in the input data signal PDAT, or as one of fields of the second packet control signal PACKDAT2, so that the electrical signal corresponding to the data comparison signal CMP may be transmitted within a transmission period of the second packet control signal PACKDAT2 shown in fig. 9. Furthermore, after the link layer processing module 120 receives the input data signal PDAT sent by the physical layer processing module 110, the signal identification sub-module 121 may identify the data comparison signal CMP before identifying the second display data from the input data signal PDAT, so as to be beneficial to controlling the working state of the data driver 10 according to the identified data comparison signal CMP.

It should be noted that in some other embodiments of the present disclosure, the electrical signal corresponding to the data comparison signal CMP may also be transmitted in other time periods, for example, in an interval time period between the input data signal PDAT corresponding to the first pixel row and the input data signal PDAT corresponding to the second pixel row. For example, the time period during which the data comparison signal CMP is identified in the data driver 10 is sufficient for the signal identification submodule 121 to identify the data comparison signal CMP before identifying the second display data, or the time period during which the data comparison signal CMP is identified before performing other signal processing operations on the identified second display data in the data driver 10. The embodiment of the present disclosure does not particularly limit the period of time for which the data comparison signal CMP is recognized in the data driver 10.

Next, a specific method of controlling the operating state of the data driver 10 according to the data comparison signal CMP in the above-described step S12 will be exemplarily described by taking different examples of the data driver 10 shown in fig. 7 and 8 as examples, respectively.

Fig. 10 is a schematic diagram of an operation state of the example of the data driver shown in fig. 7, for example, fig. 10 shows an operation state of different sub-modules in the data driver 10 in a case where the data comparison signal CMP indicates that the first display data and the second display data have a second comparison relationship (i.e., there is no identical or opposite relationship between the first display data and the second display data).

Fig. 11 is a schematic diagram of another operation state of the example of the data driver shown in fig. 7, for example, fig. 11 shows an operation state of different sub-modules in the data driver 10 in a case where the data comparison signal CMP indicates that the first display data and the second display data have a first comparison relationship (i.e., the first display data and the second display data are the same or opposite).

For example, as shown in fig. 10 and 11, after the signal identifying sub-module 121 identifies the data comparison signal CMP, the data comparison signal CMP may be provided to other sub-modules in the data driver 10, for example, the link layer processing module 120 may transmit the data comparison signal CMP to the physical layer processing module 110 and the channel array processing module 130, respectively, so as to control the operating states of the other sub-modules.

For example, in the case of a second comparison relationship between the first display data and the second display data shown in fig. 10, the physical layer processing module 110 (and each sub-module in the physical layer processing module 110), the link layer processing module 120 (and each sub-module in the link layer processing module 120), and the channel array processing module 130 (and each sub-module in the channel array processing module 130) in the data driver 10 are all in the second operating state, for example, all in the normal operating state.

For example, in the case of having the first comparison relationship between the first display data and the second display data as shown in fig. 11, the physical layer processing module 110, the link layer processing module 120, or the channel array processing module 130 in the data driver 10 may be in a first operation state different from the second operation state, respectively. For example, the first operating state may be understood as at least one sub-module in the module being in an inactive state (e.g., an inactive state, a disabled state, etc., and the like in the examples described later), or may also be understood as a state in which a part of functions or a part of operations in the module or the sub-module are inactive, so that the power consumption of each module in the first operating state is smaller than that in the second operating state, e.g., a low power consumption operating state with respect to the normal operating state.

It should be noted that, compared to the modules and the sub-modules shown in fig. 10 in the second operation state (e.g., normal operation state), the dashed boxes in fig. 11 indicate that the corresponding modules and sub-modules are in the first operation state (e.g., inactive state or abnormal operation state).

For example, as shown in fig. 10, in the case of a second comparison relationship between the first display data and the second display data, in the process of performing signal processing on the input electrical signal inp to obtain the display electrical signal OUTPT for providing to the display panel, the clock data recovery sub-module 112 in the physical layer processing module 110 needs to perform physical layer processing on the input electrical signal inp received by the data driver 10 to extract the input data signal PDAT from the input electrical signal inp; the signal identification submodule 121 and the display data formatting submodule 123 in the link layer processing module 120 need to perform link layer processing on the received input data signal PDAT, for example, need to extract second display data from the input data signal PDAT, and perform formatting processing on the extracted second display data, respectively; the first latch submodule 131 and the second latch submodule 132 in the channel array processing module 130 need to latch the second display data received from the link layer processing module 120.

For example, as shown in fig. 11, in the case that there is a first comparison relationship between the first display data and the second display data, after the channel array processing module 130 receives the data comparison signal CMP provided by the link layer processing module 120, the second latch submodule 132 in the channel array processing module 130 may obtain the second display data based on the first display data that has been buffered in response to the data comparison signal CMP. Further, the second latch submodule 132 is made not to receive the second display data transmitted from the first latch submodule 131; accordingly, the first latch submodule 131 does not need to receive or latch the second display data provided by the link layer processing module 120, and does not need to transmit the second display data to the second latch submodule 132. Further, the first latch submodule 131 may be in an inactive state, and a part of functions or operations in the second latch submodule 132 may be in an inactive state, thereby making power consumption of the channel array processing module 130 in the first operating state smaller than that in the second operating state.

For example, in the case where the first display data is the same as the second display data, the channel array processing module 130 may output the first display data that has been buffered in the second latch submodule 132 as the second display data.

For example, in the case that the first display data is opposite to the second display data, the channel array processing module 130 may invert the first display data that has been buffered in the second latch submodule 132 to obtain the second display data. For example, the negation operation may be performed in the second latch submodule 132, or may also be performed in other submodules in the channel array processing module 130; alternatively, the negation operation may be performed in other sub-modules not belonging to the channel array processing module 130, and the embodiment of the disclosure is not limited in this regard.

For example, as shown in fig. 11, in the case of having a first comparison relationship between the first display data and the second display data, since the link layer processing module 120 does not need to provide the second display data to the channel array processing module 130, the display data formatting sub-module 123 in the link layer processing module 120 may be in an inactive state in response to the data comparison signal CMP, and a part of the functions or operations in the signal identification sub-module 121 may be in an inactive state in response to the data comparison signal CMP, for example, a part of the functions and operations in the signal identification sub-module 121 for implementing the extraction of the second display data from the input data signal PDAT may be in an inactive state, so that the power consumption of the link layer processing module 120 in the first operating state is less than the power consumption in the second operating state.

For example, as shown in fig. 11, in the case that there is a first comparison relationship between the first display data and the second display data, after the physical layer processing module 110 receives the data comparison signal CMP provided by the link layer processing module 120, part of the functions or operations in the clock data recovery submodule 112 in the physical layer processing module 110 may be in an inactive state in response to the data comparison signal CMP, for example, part of the functions and operations in the clock data recovery submodule 112 for implementing the extraction of the input data signal PDAT from the input electrical signal inp may be in an inactive state, so that the power consumption of the physical layer processing module 110 in the first operating state is less than the power consumption in the second operating state.

For example, in some other examples of the disclosure, in the case that there is a first comparison relationship between the first display data and the second display data, part of the functions or part of the operations in the analog front terminal module 111 in the physical layer processing module 110 may also be in an inactive state or receive an electrical signal with a constant level in response to the data comparison signal CMP, thereby facilitating to further reduce the power consumption of the physical layer processing module 110 in the first operating state.

Fig. 12 is a schematic diagram of an operation state of the example of the data driver shown in fig. 8, for example, fig. 12 shows an operation state of different sub-modules in the data driver 10 in a case where the data comparison signal CMP indicates that the first display data and the second display data have a second comparison relationship (i.e., there is no identical or opposite relationship between the first display data and the second display data).

Fig. 13 is a schematic diagram of another operation state of the example of the data driver shown in fig. 8, for example, fig. 13 shows an operation state of different sub-modules in the data driver 10 in a case where the data comparison signal CMP indicates that the first display data and the second display data have a first comparison relationship (i.e., the first display data and the second display data are the same or opposite).

It should be noted that the control method in the example of the data driver shown in fig. 12 and 13 is basically similar to the control method in the example of the data driver shown in fig. 10 and 11, and repeated description is omitted.

For example, as shown in fig. 12, in the case where there is a second comparison relationship between the first display data and the second display data, the data path sub-module 113 in the physical layer processing module 110 performs signal processing operations such as signal amplification, frequency conversion, modulation and demodulation, adjacent channel processing, or level adjustment and control on the received input electrical signal INPDAT corresponding to the input data signal PDAT (e.g. corresponding to the signal processing operations in the analog front end module 111 in figure 10), to obtain a stable electrical signal suitable for the data driver 10, and to perform recovery sampling on the electrical signal after the above-mentioned signal processing operation, to extract therefrom a corresponding input data signal PDAT (e.g. corresponding to a part of the signal processing operation in the clock data recovery sub-module 112 in fig. 10), the extracted input data signal PDAT is then transmitted to the subsequent link layer processing module 120.

For example, as shown in fig. 13, in the case that there is a first comparison relationship between the first display data and the second display data, after the physical layer processing module 110 receives the data comparison signal CMP provided by the link layer processing module 120, at least part of the functions or at least part of the operations in the data path sub-module 113 in the physical layer processing module 110 may be in an inactive state in response to the data comparison signal CMP, so that the power consumption of the physical layer processing module 110 in the first operating state is less than the power consumption in the second operating state.

For example, the data path sub-module 113 for implementing, for example, a part of the signal processing functions and operations corresponding to the analog front terminal module 111 may be in an inactive state, and the data path sub-module 113 for implementing, for example, a part of the signal processing functions and operations corresponding to the clock data recovery sub-module 112 may be in an inactive state.

For example, in some examples of the present disclosure, in the example of the operating state shown in fig. 13, a part of the sub-modules of the data path sub-module 113 for implementing, for example, a part of signal processing functions and operations corresponding to the analog front terminal module 111 may also be in an inactive state or receive an electrical signal at a constant level, thereby facilitating to further reduce the power consumption of the physical layer processing module 110 in the first operating state.

For example, in some embodiments of the present disclosure, in the case where there is a first comparison relationship between the first display data and the second display data, the timing controller may also stop transmitting the valid electrical signal to the data driver 10 or transmit the dummy electrical signal to the data driver 10 during a period of transmitting the input data signal PDAT corresponding to the second display data. For example, the input data signal PDAT received by the link layer processing module 120 in the data driver 10 may be as shown in fig. 14, and the second display data signal DSPDAT2 corresponding to the second display data may be a dummy electrical signal or an electrical signal that is maintained at a constant level, thereby further reducing power consumption of the corresponding module or sub-module in the data driver 10 that serves the relevant input data signal PDAT in the first operating state.

For example, in some embodiments of the present disclosure, in the case that there is a first comparison relationship between the first display data and the second display data, the corresponding module (e.g., the link layer processing module 120) in the data driver 10 may also no longer receive the input data signal PDAT, so that the power consumption of the corresponding module or sub-module in the data driver 10 serving the relevant input data signal PDAT in the first operating state may be further reduced.

It should be noted that, in the embodiments of the present disclosure, the flow of the control method of the data driver provided in the above-mentioned embodiments of the present disclosure may include more or less operations, and these operations may be executed sequentially or in parallel. Although the flow of the control method of the data driver described above includes a plurality of operations occurring in a specific order, it should be clearly understood that the order of the plurality of operations is not limited. The above-described control method of the data driver may be performed once or may be performed a plurality of times according to a predetermined condition.

Fig. 15 is a schematic flowchart of a control method of a timing controller according to some embodiments of the present disclosure.

As shown in fig. 15, the control method of the timing controller according to the embodiment of the present disclosure includes steps S21 and S22.

Step S21: according to source input data received from a data source, a plurality of comparison relations between a plurality of groups of first display data and a plurality of groups of second display data are respectively determined, and a plurality of data comparison signals representing the plurality of comparison relations are generated, wherein the groups of first display data are respectively used for enabling a plurality of groups of sub-pixels in a first pixel row to be displayed, the groups of second display data are respectively used for enabling a plurality of groups of sub-pixels in a second pixel row to be displayed, and the second pixel row is driven to be displayed after the first pixel row in terms of time.

Step S22: a plurality of data comparison signals are sent to the data driver.

In the control method of the timing controller provided in the above embodiment of the disclosure, by dividing the sub-pixels in the second pixel row to be driven to display into a plurality of groups, respectively determining a comparison relationship between the second display data corresponding to each group of sub-pixels and the first display data corresponding to the corresponding sub-pixel group in the first pixel row driven to display prior to the second pixel row, and sending the generated plurality of data comparison signals representing the comparison relationship to the data driver, the data driver may be in different operating states in response to the plurality of data comparison signals when providing the second display data corresponding to different sub-pixel groups in the second pixel row. Therefore, the working power consumption of the data driver can be flexibly controlled, so that the beneficial effects of reducing the working power consumption of the data driver and further reducing the total power consumption of a system are favorably achieved, and the use cost is reduced.

In some embodiments of the present disclosure, the control method of the timing controller may further include step S23 for each of the plurality of data comparison signals.

Step S23: in response to the data comparison signal indicating that the first display data and the second display data have the first comparison relationship therebetween, the input data signal corresponding to the second display data is not transmitted to the data driver. The first comparison relationship includes the first display data being the same as or opposite to the second display data.

For example, in the case that it is determined that the first display data is the same as or opposite to the second display data, the data driver may be enabled to obtain the second display data according to the first display data already cached in the data driver, thereby helping to reduce power consumption required to be consumed by the data driver in the process of obtaining the second display data, and reducing the total system power consumption of the data driver.

In addition, the control method of the timing controller according to the above embodiment of the present disclosure may further reduce the operating current generated in the data driver by reducing the total power consumption of the system of the data driver when the display panel using the timing controller is used for low voltage domain display, so as to be beneficial to improving characteristics of signal transmission in the data driver, such as high frequency electromagnetic interference (EMI) resistance, Wireless Wide Area Network (WWAN) signal transmission performance, and the like, and further improve stability and reliability of signal transmission.

For example, the not transmitting the input data signal corresponding to the second display data to the data driver in the above-described step S23 includes: during a period of transmitting the input data signal corresponding to the second display data, the transmission of the valid electrical signal to the data driver or the transmission of the dummy electrical signal to the data driver is stopped.

For example, in the case where it is determined that the first display data is the same as or opposite to the second display data, it is possible to cause the timing controller to stop sending the valid electrical signal to the data driver or to send the dummy electrical signal to the data driver, that is, to cause the second display data obtained in the data driver to be no longer obtained by extraction from the input electrical signal sent from the timing controller, and to cause the data driver to obtain the second display data from the first display data that has been buffered in the data driver. Therefore, the power consumption required by the time sequence controller can be reduced, and the total power consumption of the system of the time sequence controller can be reduced.

It should be noted that, in the embodiments of the present disclosure, for specific operation procedures, steps, technical effects, and the like of the control method of the timing controller, reference may be made to the above description about the control method of the data driver, and details are not repeated here.

At least one embodiment of the present disclosure further provides a data driver control device, where the data driver control device obtains a comparison relationship between second display data corresponding to each group of sub-pixels in a second pixel row to be driven to display and first display data corresponding to a corresponding group of sub-pixels in a first pixel row driven to display before the second pixel row, and controls the data driver to be in different operating states respectively in response to a plurality of data comparison signals according to the comparison relationship. Therefore, the working power consumption of the data driver can be flexibly controlled, so that the beneficial effects of reducing the working power consumption of the data driver and further reducing the total power consumption of a system are facilitated, and the use cost of a product is reduced.

Fig. 16 is a schematic block diagram of a data driver control apparatus according to some embodiments of the present disclosure.

For example, as shown in fig. 16, the data driver control device 200 includes a data comparison signal acquisition unit 201 and an operating state control unit 202.

The data comparison signal acquisition unit 201 is configured to acquire a plurality of data comparison signals respectively representing a plurality of comparison relationships between a plurality of sets of first display data respectively for causing a plurality of sets of sub-pixels in a first pixel row to be displayed and a plurality of sets of second display data respectively for causing a plurality of sets of sub-pixels in a second pixel row to be driven to be displayed temporally after the first pixel row. For example, the data comparison signal acquisition unit 201 may perform step S11 in the control method of the data driver shown in fig. 1.

The operating state control unit 202 is configured to control the operating states of the data drivers according to the data comparison signals, respectively. For example, the operating state control unit 202 may perform step S12 in the control method of the data driver shown in fig. 1.

For example, the data comparison signal acquisition unit 201 and the operating state control unit 202 include codes and programs stored in a memory; the processor may execute the code and program to implement some or all of the functions of the data comparison signal acquisition unit 201 and the operating state control unit 202 as described above. For example, the data comparison signal acquisition unit 201 and the operating state control unit 202 may be dedicated hardware devices for implementing some or all of the functions of the data comparison signal acquisition unit 201 and the operating state control unit 202 as described above. For example, the data comparison signal acquisition unit 201 and the operating state control unit 202 may be one circuit board or a combination of a plurality of circuit boards for implementing the functions as described above. In the embodiment of the present application, the one or a combination of a plurality of circuit boards may include: (1) one or more processors; (2) one or more non-transitory memories connected to the processor; and (3) firmware stored in the memory executable by the processor.

It should be noted that the data comparison signal obtaining unit 201 is configured to implement step S11 shown in fig. 1, and the operating state control unit 202 is configured to implement step S12 shown in fig. 1. Thus, for the specific description of the data comparison signal obtaining unit 201, reference may be made to the description related to step S11 shown in fig. 1 in the embodiment of the control method of the data driver, and for the specific description of the operating state control unit 202, reference may be made to the description related to step S12 shown in fig. 1 in the embodiment of the control method of the data driver. In addition, the data driver control device can achieve the technical effects similar to the control method of the data driver, and the details are not repeated herein.

At least one embodiment of the present disclosure further provides a timing controller, which determines a comparison relationship between second display data corresponding to each group of sub-pixels and first display data corresponding to a corresponding sub-pixel group in a first pixel row that is driven and displayed prior to the second pixel row, and sends a plurality of generated data comparison signals representing the comparison relationship to a data driver, so that the data driver is in different operating states in response to the plurality of data comparison signals when providing second display data corresponding to different sub-pixel groups in the second pixel row. Therefore, the working power consumption of the data driver can be flexibly controlled, so that the beneficial effects of reducing the working power consumption of the data driver and further reducing the total power consumption of a system are favorably achieved, and the use cost is reduced.

Fig. 17 is a schematic block diagram of a timing controller according to some embodiments of the present disclosure.

For example, as shown in fig. 17, the timing controller 600 includes a data comparison signal generating unit 601 and a signal transmitting unit 602.

The data comparison signal generation unit 601 is configured to determine a plurality of comparison relationships between the plurality of sets of first display data and the plurality of sets of second display data, respectively, based on source input data received from the data source, and generate a plurality of data comparison signals representing the plurality of comparison relationships. The multiple groups of first display data are respectively used for enabling the multiple groups of sub-pixels in the first pixel row to display, the multiple groups of second display data are respectively used for enabling the multiple groups of sub-pixels in the second pixel row to display, and the second pixel row is driven to display behind the first pixel row in terms of time. For example, the data comparison signal generation unit 601 may perform step S21 in the control method of the timing controller shown in fig. 15.

The signal transmission unit 602 is configured to transmit a plurality of data comparison signals to the data driver. For example, the signal transmission unit 602 may perform step S22 in the control method of the timing controller shown in fig. 15.

For example, the data comparison signal generation unit 601 and the signal transmission unit 602 include codes and programs stored in a memory; the processor may execute the code and program to implement some or all of the functions of the data comparison signal generation unit 601 and the signal transmission unit 602 as described above. For example, the data comparison signal generation unit 601 and the signal transmission unit 602 may be dedicated hardware devices for implementing some or all of the functions of the data comparison signal generation unit 601 and the signal transmission unit 602 as described above. For example, the data comparison signal generation unit 601 and the signal transmission unit 602 may be one circuit board or a combination of a plurality of circuit boards for implementing the functions as described above. In the embodiment of the present application, the one or a combination of a plurality of circuit boards may include: (1) one or more processors; (2) one or more non-transitory memories connected to the processor; and (3) firmware stored in the memory executable by the processor.

It should be noted that the data comparison signal generation unit 601 is configured to implement step S21 shown in fig. 15, and the signal transmission unit 602 is configured to implement step S22 shown in fig. 15. Thus, the description of step S21 shown in fig. 15 in the embodiment of the control method of the timing controller described above may be referred to for the detailed description of the data comparison signal generation unit 601, and the description of step S22 shown in fig. 15 in the embodiment of the control method of the timing controller described above may be referred to for the detailed description of the signal transmission unit 602. In addition, the timing controller can achieve the technical effect similar to the control method of the timing controller, and the description is omitted here.

At least one embodiment of the present disclosure further provides an electronic device including the timing controller described in any embodiment of the present disclosure, for example, the timing controller 600 shown in fig. 17. The electronic device further includes the data driver described in any embodiment of the present disclosure, for example, the data driver includes a data comparison signal obtaining unit configured to obtain a plurality of data comparison signals, and an operating state control unit configured to control operating states of the data driver according to the data comparison signals, respectively. For example, for details of the data comparison signal obtaining unit and the operating state control unit included in the data driver, reference may be made to corresponding descriptions of the data comparison signal obtaining unit 201 and the operating state control unit 202 in the data driver control device 200 in the above-described embodiment, or may also be made to corresponding descriptions in the above-described embodiment of the control method for the data driver, for example, reference may be made to corresponding descriptions of the data driver 10 shown in fig. 6 to 8, and details are not repeated here.

In some embodiments of the present disclosure, the electronic device further comprises a display panel, the data driver being configured to provide display data to the display panel for driving the rows of pixels in the display panel for display.

For example, the display panel may be the display panel 101 shown in fig. 2, the display panel 102 shown in fig. 3, or the display panel 103 shown in fig. 4, and the like, and the embodiment of the present disclosure does not specifically limit the structure, type, function, and the like of the display panel.

Fig. 18 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure. Fig. 19 is a schematic diagram of an example of an electronic device according to some embodiments of the present disclosure, for example, fig. 19 is a schematic diagram of an example of the electronic device shown in fig. 18.

For example, as shown in fig. 18, the electronic apparatus 70 includes a timing controller 71, a data driver 72, and a display panel 73. For example, the timing controller 71 may be the timing controller according to any embodiment of the disclosure, such as the timing controller 600 shown in fig. 17. For example, the data driver 72 may be a data driver provided in any embodiment of the present disclosure, for example, the data driver 10 shown in fig. 6 to 8 may be referred to.

For example, the display panel 73 may be any product or component having a display function, such as a liquid crystal panel, a liquid crystal television, an OLED panel, an OLED television, a QLED panel, a QLED television, a display, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, and a navigator, and the embodiment of the disclosure is not limited thereto.

For example, the display panel 73 may refer to the display panel 101 shown in fig. 2, the display panel 102 shown in fig. 3, the display panel 103 shown in fig. 4, or the like.

For example, as shown in fig. 19, in one example, the electronic device 70 further includes at least one gate driver 74, and the at least one gate driver 74 may be disposed on one or more sides of the display panel 73, which is not particularly limited by the embodiments of the disclosure.

For example, two gate drivers 74 respectively located at two opposite sides of the display panel 73 may be provided in the electronic device 70, so that the two gate drivers 74 may implement a double-side driving display of the display panel 73.

For example, the data driver 72 is electrically connected to the pixel circuit in each sub-pixel PX through a plurality of data lines DL. For example, the data driver 72 provides corresponding display electrical signals, such as display voltages or display currents, to the sub-pixels PX in the display panel 73 through the plurality of data lines DL according to the input electrical signals provided by the timing controller 71, so as to drive the sub-pixels PX in the display panel 73 to perform display. For example, referring to fig. 19, the input electrical signal may include an electrical signal RGB corresponding to an input data signal, such as the input electrical signal INPDAT shown in fig. 8, and further include an electrical signal DCS corresponding to an input clock signal, such as the input electrical signal inclk shown in fig. 8. For example, the data driver 72 may be implemented as a semiconductor chip.

For example, the gate driver 74 is electrically connected to the pixel circuit in each sub-pixel PX through a plurality of scan lines GL to supply a corresponding scan signal, etc., to each pixel circuit, respectively. For example, the gate driver 74 supplies gate signals, i.e., scan signals, according to a plurality of scan control signals GCS supplied from the timing controller 71. For example, the gate driver 74 may be implemented as a semiconductor chip, or may be integrated in the display panel 73 to constitute a GOA circuit.

For example, the timing controller 71 is configured to process source input data DRGB externally input (e.g., provided from a data source) from the electronic device 70, and provide the processed electrical signals RGB corresponding to the input data signals to the data driver 71, and provide the scan control signal GCS and the electrical signal DCS corresponding to the input clock signal to the gate driver 74 and the data driver 71, respectively, to thereby control the data driver 71 and the gate driver 74.

For example, the timing controller 71 processes externally input source input data DRGB to match the size and resolution of the display panel 73, and then supplies the processed electrical signals RGB to the data driver 72. For example, the timing controller 71 generates the scan control signal GCS and the electrical signal DCS using synchronization signals SYNC (e.g., a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) externally input from the electronic device 70. The timing controller 71 supplies the generated electric signals DCS and scan control signals GCS to the data driver 72 and the gate driver 74, respectively, for control of the data driver 72 and the gate driver 74.

For example, the electronic device 70 may further include other components, such as a signal decoding circuit, etc., which may be conventional components, for example, and will not be described in detail herein.

At least one embodiment of the present disclosure also provides an electronic device that includes a processor, memory, and one or more computer program modules. One or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules including instructions for performing a control method of the data driver or a control method of the timing controller provided by any of the embodiments of the present disclosure.

Fig. 20 is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. As shown in fig. 20, the electronic device 300 includes a processor 310 and a memory 320. Memory 320 is used to non-transitory store computer-executable instructions (e.g., one or more computer program modules). The processor 310 is configured to execute the computer-executable instructions, and when the computer-executable instructions are executed by the processor 310, the computer-executable instructions may perform one or more steps of the control method of the data driver as described above or perform one or more steps of the control method of the timing controller as described above. The memory 320 and the processor 310 may be interconnected by a bus system and/or other form of connection mechanism (not shown).

For example, the processor 310 may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or other form of processing unit having data processing capabilities and/or program execution capabilities. For example, the Central Processing Unit (CPU) may be an X86 or ARM architecture or the like. The processor 310 may be a general-purpose processor or a special-purpose processor that may control other components in the electronic device 300 to perform desired functions.

For example, memory 320 may include any combination of one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, Random Access Memory (RAM), cache memory (or the like). The non-volatile memory may include, for example, Read Only Memory (ROM), a hard disk, an Erasable Programmable Read Only Memory (EPROM), a portable compact disc read only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer program modules may be stored on the computer-readable storage medium and executed by processor 310 to implement various functions of electronic device 300. Various applications and various data, as well as various data used and/or generated by the applications, and the like, may also be stored in the computer-readable storage medium.

It should be noted that, in the embodiment of the disclosure, reference may be made to the above description on the control method of the data driver and the control method of the timing controller for specific functions and technical effects of the electronic device 300, and details are not repeated herein.

Fig. 21 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure. The electronic device 400 is, for example, suitable for implementing a control method of a data driver or a control method of a timing controller provided in the embodiments of the present disclosure. The electronic device 400 may be a terminal device or the like. It should be noted that the electronic device 400 shown in fig. 21 is only an example, and does not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.

As shown in fig. 21, electronic device 400 may include a processing means (e.g., central processing unit, graphics processor, etc.) 410 that may perform various appropriate actions and processes in accordance with a program stored in a Read Only Memory (ROM)420 or a program loaded from a storage device 480 into a Random Access Memory (RAM) 430. In the RAM 430, various programs and data necessary for the operation of the electronic apparatus 400 are also stored. The processing device 410, the ROM 420, and the RAM 430 are connected to each other by a bus 440. An input/output (I/O) interface 450 is also connected to bus 440.

Generally, the following devices may be connected to the I/O interface 450: input devices 460 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 470 including, for example, a Liquid Crystal Display (LCD), speakers, vibrators, or the like; storage 480 including, for example, magnetic tape, hard disk, etc.; and a communication device 490. The communication device 490 may allow the electronic device 400 to communicate wirelessly or by wire with other electronic devices to exchange data. While fig. 21 illustrates an electronic device 400 having various means, it is to be understood that not all illustrated means are required to be implemented or provided, and that the electronic device 400 may alternatively be implemented or provided with more or less means.

For example, according to an embodiment of the present disclosure, the control method of the data driver or the control method of the timing controller described above may be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer readable medium, the computer program comprising program code for performing the control method of the data driver or the control method of the timing controller described above. In such an embodiment, the computer program may be downloaded and installed from a network through communication device 490, or installed from storage device 480, or installed from ROM 420. When the computer program is executed by the processing device 410, the functions defined in the control method of the data driver or the control method of the timing controller provided by the embodiment of the present disclosure may be implemented.

Fig. 22 is a schematic diagram of a storage medium according to some embodiments of the present disclosure. For example, as shown in fig. 22, the storage medium 500 may be a non-transitory computer-readable storage medium, on which one or more computer-readable instructions 501 may be non-temporarily stored on the storage medium 500. For example, the computer readable instructions 501, when executed by a processor, may perform one or more steps according to the control method of the data driver or the control method of the timing controller described above.

For example, the storage medium 500 may be applied to the electronic device described above, and for example, the storage medium 500 may include a memory in the electronic device.

For example, the storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a Random Access Memory (RAM), a Read Only Memory (ROM), an Erasable Programmable Read Only Memory (EPROM), a portable compact disc read only memory (CD-ROM), a flash memory, or any combination of the above, as well as other suitable storage media.

For example, the description of the storage medium 500 may refer to the description of the memory in the embodiment of the electronic device, and repeated descriptions are omitted. Specific functions and technical effects of the storage medium 500 can be referred to the above description of the control method of the data driver or the control method of the timing controller, which is not described herein again.

For the present disclosure, there are also the following points to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Thicknesses and dimensions of layers or structures may be exaggerated in the drawings used to describe embodiments of the present invention for clarity. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

(3) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. A control method of a data driver for a display panel, wherein the display panel includes a plurality of pixel rows sequentially arranged in a first direction, each of the pixel rows including a plurality of sub-pixels sequentially arranged in a second direction and divided into m groups, the second direction being different from the first direction, m being an integer greater than 1;

the plurality of pixel rows comprises a first pixel row and a second pixel row, the second pixel row being driven to display temporally after the first pixel row;

the control method comprises the following steps:

respectively acquiring m data comparison signals, wherein in the m data comparison signals, the ith data comparison signal represents a comparison relationship between first display data used for enabling the ith group of sub-pixels in the first pixel row to display and second display data used for enabling the ith group of sub-pixels in the second pixel row to display, i is an integer, and i is greater than 0 and is less than or equal to m; and

and respectively controlling the working state of the data driver according to each data comparison signal in the m data comparison signals.

2. The control method of the data driver according to claim 1, wherein the number of the plurality of sub-pixels included in each of the pixel rows is (m × n), n being an integer greater than 0;

the (m × j + i) th sub-pixel in the first pixel row belongs to the ith group of sub-pixels in the first pixel row, the (m × j + i) th sub-pixel in the second pixel row belongs to the ith group of sub-pixels in the second pixel row, j is an integer, and j is more than or equal to 0 and less than n;

the ith data comparison signal represents a comparison relationship between first display data for causing a (m × j + i) th sub-pixel in the first pixel row to display and second display data for causing a (m × j + i) th sub-pixel in the second pixel row to display.

3. The method of claim 2, wherein the (mxj + i) th sub-pixel in the first pixel row and the (mxj + i) th sub-pixel in the second pixel row share a same data line in the display panel to apply a first display electrical signal corresponding to the first display data to the (mxj + i) th sub-pixel in the first pixel row and to apply a second display electrical signal corresponding to the second display data to the (mxj + i) th sub-pixel in the second pixel row, respectively, through the same data line.

4. The control method of the data driver according to claim 3, wherein the (mxj + i) th sub-pixel in the first pixel row and the (mxj + i) th sub-pixel in the second pixel row are respectively located at both sides of the same data line in the second direction; or

The (m × j + i) th sub-pixel in the first pixel row and the (m × j + i) th sub-pixel in the second pixel row are located on at least one side of the same data line in the second direction.

5. The control method of the data driver according to claim 1, wherein the number of the plurality of sub-pixels included in each of the pixel rows is (2 x m x n), n being an integer greater than 0;

the (2 XmXj +2 xi-1) th sub-pixel and the (2 XmXj +2 xi) th sub-pixel in the first pixel row belong to the ith group of sub-pixels in the first pixel row, the (2 XmXj +2 xi-1) th sub-pixel and the (2 XmXj +2 xi) th sub-pixel in the second pixel row belong to the ith group of sub-pixels in the second pixel row, j is an integer, and j is more than or equal to 0 and less than n;

the ith data comparison signal represents a comparison relationship between first display data for causing the (2 × m × j +2 × i-1) th sub-pixel and the (2 × m × j +2 × i) th sub-pixel in the first pixel row to display and second display data for causing the (2 × m × j +2 × i-1) th sub-pixel and the (2 × m × j +2 × i) th sub-pixel in the second pixel row to display.

6. The method of claim 5, wherein the (2 xm x j +2 xi-1) and (2 xm x j +2 xi) sub-pixels in the first pixel row and the (2 xm x j +2 xi) sub-pixels in the second pixel row share a same data line in the display panel, so that the first display electrical signal corresponding to the first display data is applied to the (2 xm x j +2 xi-1) and (2 xm x j +2 xi) sub-pixels in the first pixel row and the second display electrical signal corresponding to the second display data is applied to the (2 xm x j +2 xi-1) and (2 xm x j +2 xi) sub-pixels in the second pixel row through the same data line, respectively, and the second display electrical signal corresponding to the second display data is applied to the (2 xm x j +2 xi-1) and (2 xm x j +2 xi) sub-1 sub-pixels in the second pixel row ) And a sub-pixel.

7. The method of claim 6, wherein the (2 xmxj +2 xi-1) th and (2 xmxj +2 xi) th sub-pixels in the first pixel row and the (2 xmxj +2 xi) th and (2 xmxj +2 xi-1) th and (2 xmxj +2 xi) th sub-pixels in the second pixel row are respectively located at both sides of the same data line in the second direction; or

The (2 × m × j +2 × i-1) th sub-pixel and the (2 × m × j +2 × i) th sub-pixel in the first pixel row and the (2 × m × j +2 × i-1) th sub-pixel and the (2 × m × j +2 × i) th sub-pixel in the second pixel row are located on at least one side of the same data line in the second direction.

8. The control method of the data driver according to any one of claims 1 to 7, wherein the first pixel row and the second pixel row are two pixel rows arranged adjacent to each other in the first direction, and driving display orders of the first pixel row and the second pixel row are temporally adjacent.

9. The method of controlling a data driver according to any one of claims 1 to 7, wherein the data driver comprises a plurality of modules configured to receive an input data signal and derive display data from the input data signal,

controlling the data according to each of the m data comparison signals, respectively, including:

in response to the ith data comparison signal indicating that the first display data and the second display data have a first comparison relationship therebetween, obtaining the second display data based on the first display data that has been buffered by the data driver, wherein the first comparison relationship includes whether the first display data is the same as or opposite to the second display data; or

In response to the ith data comparison signal indicating that the first display data and the second display data have a second comparison relationship therebetween different from the first comparison relationship, the second display data is derived based on the input data signals received by the data driver for the ith group of sub-pixels in the second row of pixels.

10. The method of claim 9, wherein the data is controlled separately according to each of the m data comparison signals, further comprising:

determining whether the data driver receives the input data signal in response to the first comparison relationship.

11. The method of claim 9, wherein the data is controlled separately according to each of the m data comparison signals, further comprising:

responding to the first comparison relationship, and enabling at least part of the modules in the plurality of modules to be in a first working state;

responding to the second comparison relationship, and enabling the modules to be in a second working state;

wherein a power consumption of each of the plurality of modules in the first operating state is less than a power consumption in the second operating state.

12. The method of claim 11, wherein causing at least some of the plurality of modules to be in the first operating state comprises:

such that the at least some modules are in an inactive state.

13. A method of controlling a timing controller, comprising:

determining a plurality of comparison relations between a plurality of groups of first display data and a plurality of groups of second display data respectively according to source input data received from a data source, and generating a plurality of data comparison signals for representing the plurality of comparison relations, wherein the groups of first display data are respectively used for enabling a plurality of groups of sub-pixels in a first pixel row to be displayed, the groups of second display data are respectively used for enabling a plurality of groups of sub-pixels in a second pixel row to be displayed, and the second pixel row is driven to be displayed after the first pixel row in terms of time; and

transmitting the plurality of data comparison signals to a data driver.

14. A data driver control apparatus comprising:

a data comparison signal acquisition unit configured to acquire a plurality of data comparison signals respectively representing a plurality of comparison relationships between a plurality of sets of first display data respectively for causing a plurality of sets of sub-pixels in a first pixel row to be displayed and a plurality of sets of second display data respectively for causing a plurality of sets of sub-pixels in a second pixel row to be driven and displayed temporally after the first pixel row; and

and the working state control unit is configured to respectively control the working state of the data driver according to each data comparison signal.

15. A timing controller, comprising:

a data comparison signal generation unit configured to determine, based on source input data received from a data source, a plurality of comparison relationships between a plurality of sets of first display data for causing a plurality of sets of sub-pixels in a first pixel row to be displayed, respectively, and a plurality of sets of second display data for causing a plurality of sets of sub-pixels in a second pixel row to be driven to be displayed temporally after the first pixel row, respectively, and generate a plurality of data comparison signals representing the plurality of comparison relationships; and

a signal transmission unit configured to transmit the plurality of data comparison signals to the data driver.

16. An electronic device comprising the timing controller of claim 15 and the data driver, wherein the data driver comprises:

a data comparison signal acquisition unit configured to acquire the plurality of data comparison signals; and

17. An electronic device, comprising:

a memory non-transiently storing computer executable instructions;

a processor configured to execute the computer-executable instructions,

wherein the computer executable instructions, when executed by the processor, implement a method of controlling a data driver according to any one of claims 1-12 or a method of controlling a timing controller according to claim 13.

18. A non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions that, when executed by a processor, implement the control method of the data driver according to any one of claims 1 to 12 or the control method of the timing controller according to claim 13.