CN114518528A - Safety chip fault detection circuit and terminal equipment - Google Patents
Safety chip fault detection circuit and terminal equipment Download PDFInfo
- Publication number
- CN114518528A CN114518528A CN202011300168.6A CN202011300168A CN114518528A CN 114518528 A CN114518528 A CN 114518528A CN 202011300168 A CN202011300168 A CN 202011300168A CN 114518528 A CN114518528 A CN 114518528A
- Authority
- CN
- China
- Prior art keywords
- pin
- gate
- exclusive
- module
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31727—Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks
Abstract
The invention provides a safety chip fault detection circuit and terminal equipment, comprising: phase difference alarm module, false alarm filtering module and latch output module, wherein: the phase difference alarm module is used for receiving the clock to be detected and the reference clock, performing phase detection on the clock to be detected and the reference clock and acquiring a first pulse; the input end of the false alarm filtering module is connected with the output end of the phase difference alarm module and is used for filtering the first pulse to obtain an alarm signal; and the input end of the latch output module is connected with the output end of the false alarm filtering module and is used for latching an alarm signal. The invention can improve the reliability of the fault detection of the safety chip.
Description
Technical Field
The invention relates to the technical field of clock fault detection, in particular to a safety chip fault detection circuit and terminal equipment.
Background
The bypass attack to the security chip mainly extracts the cryptographic parameters such as the key, thereby leading the cryptographic chip to lose the security function. In the prior art, a burr detector is generally adopted to detect the abnormal change of a clock signal, and an alarm is given when burrs are generated so as to realize the protection of clock signal fault injection attack. However, since the detection range of the burr detector is limited, in order to realize full-chip detection, a plurality of burr detectors need to be placed inside the chip, which can greatly increase the area of the chip and reduce the performance of the chip. In addition, the memory unit built in the security chip has a special structure, and a burr sensor is difficult to integrate in the memory unit, so that a dead zone exists in the detection range of the chip, and the clock attack protection of the whole chip cannot be realized. As can be seen, the reliability of the fault detection of the safety chip is lower at present.
Disclosure of Invention
The embodiment of the invention provides a safety chip fault detection circuit and terminal equipment, and aims to solve the problem of low reliability of safety chip fault detection.
In a first aspect, an embodiment of the present invention provides a circuit for detecting a fault of a security chip, where the circuit includes a phase difference alarm module, a false alarm filtering module, and a latch output module, where:
the phase difference alarm module is used for receiving a clock to be detected and a reference clock, and performing phase detection on the clock to be detected and the reference clock to obtain a first pulse;
the input end of the false alarm filtering module is connected with the output end of the phase difference alarm module and is used for filtering the first pulse to acquire an alarm signal;
and the input end of the latch output module is connected with the output end of the false alarm filtering module and is used for latching the alarm signal.
In a second aspect, an embodiment of the present invention provides a terminal device, where the terminal device includes the above security chip fault detection circuit.
In the embodiment of the invention, the phase difference alarm module receives a clock to be detected and a reference clock, performs phase detection on the clock to be detected and the reference clock, outputs a first pulse under the condition that a phase difference exists between the clock to be detected and the reference clock, further, the false alarm filtering module performs filtering processing on the first pulse to acquire an alarm signal, and further, the latch output module latches the alarm signal and outputs the alarm signal. The phase difference alarm module can detect the phase difference between the clock to be detected and the reference clock, the false alarm filtering module can filter the inherent phase difference in the actual design of the chip, and the obtained alarm signal is more accurate, so that the reliability of fault detection of the safety chip can be improved.
Drawings
Fig. 1 is one of the structural diagrams of a security chip failure detection circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a security chip failure detection circuit according to an embodiment of the present invention;
FIG. 3 is a second schematic diagram of a safety chip failure detection circuit according to an embodiment of the present invention;
fig. 4 is a second structural diagram of a safety chip fault detection circuit according to an embodiment of the present invention;
fig. 5 is a third structural diagram of a failure detection circuit of a security chip according to an embodiment of the present invention;
fig. 6 is a fourth structural diagram of a safety chip fault detection circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application may be implemented in sequences other than those illustrated or described herein, and the terms "first" and "second" used herein should not be construed as limiting the number of terms, e.g., the first term can be one or more than one.
Referring to fig. 1, fig. 1 is a structural diagram of a safety chip fault detection circuit according to an embodiment of the present invention, as shown in fig. 1, the safety chip fault detection circuit includes a phase difference alarm module 101, a false alarm filtering module 102, and a latch output module 103, where:
the phase difference alarm module 101 is configured to receive a clock to be detected and a reference clock, perform phase detection on the clock to be detected and the reference clock, and acquire a first pulse;
the input end of the false alarm filtering module is connected with the output end of the phase difference alarm module and is used for filtering the first pulse to obtain an alarm signal;
and the latch output module 103, the input end of which is connected with the output end of the false alarm filtering module, is used for latching the alarm signal.
In the actual design of the security chip, the input clock signal has a specific phase difference due to clock jitter and parasitic wiring, and the phase difference alarm module 101 generates a false alarm signal having a fixed width. In the input signals to be detected, an alarm signal and a false alarm signal corresponding to a clock fault may exist at the same time, the false alarm signal needs to be filtered, the alarm signal is finally obtained, and an alarm is given based on the alarm signal.
The phase difference alarm module 101 performs phase detection on an input clock signal, can detect changes of clock signal edges, has a high-speed response characteristic, and is easy to complete fault alarm in one clock cycle. The input clock signal comprises a clock to be detected and a reference clock, and the phase difference alarm module outputs a first pulse with a low level under the condition that the clock to be detected and the reference clock have a phase difference. The first pulse may include an alarm signal and a false alarm signal corresponding to a clock failure.
In addition, the alarm filtering module 102 is configured to perform filtering processing on the first pulse, filter a false alarm signal in the first pulse, and obtain an alarm signal corresponding to a clock fault.
Because the duration of the alarm signal may be very short, such as only 1 nanosecond, the generated alarm time is too short, and the alarm effect is not obvious, the received alarm signal needs to be latched by the latch output module 103, and the alarm signal can be continuously output, so that an ideal alarm effect is achieved.
In the embodiment of the invention, the phase difference alarm module receives a clock to be detected and a reference clock, performs phase detection on the clock to be detected and the reference clock, outputs a first pulse under the condition that a phase difference exists between the clock to be detected and the reference clock, further, the false alarm filtering module performs filtering processing on the first pulse to acquire an alarm signal, and further, the latch output module latches the alarm signal and outputs the alarm signal. The phase difference alarm module can detect the phase difference between the clock to be detected and the reference clock, the false alarm filtering module can filter the inherent phase difference in the actual design of the chip, and the obtained alarm signal is more accurate, so that the reliability of fault detection of the safety chip can be improved.
As shown in fig. 2, the principle of implementing the fault detection alarm according to the embodiment of the present invention is as follows: the method comprises the steps of inputting a clock to be detected and a reference clock, carrying out phase detection on the clock to be detected and the reference clock, and acquiring a phase difference alarm signal under the condition that the clock to be detected and the reference clock have a phase difference, wherein the phase difference alarm signal generally comprises an alarm signal and a false alarm signal. Further, the phase difference alarm signal is transmitted to the next circuit module for false alarm filtering, the false alarm signal is filtered, and the alarm signal is reserved. And further, latching the reserved alarm signal, and outputting the alarm signal to alarm.
As shown in fig. 3, when a fault is injected, the edge of the clock signal to be detected may be advanced, the clock to be detected and the reference clock have a phase difference, and an alarm signal of low level "0" will be generated, the alarm signal may last for a period of time under the action of the latch output module, and the alarm signal may be cleared when a reset signal is received; by the same principle, when a fault is injected, the edge of a clock signal to be detected may lag behind a reference clock, a phase difference exists between the clock to be detected and the reference clock, an alarm signal with a low level of 0 is generated, the alarm signal can last for a period of time under the action of the latch output module, and the alarm signal can be cleared when a reset signal is received.
As an alternative embodiment, as shown in fig. 4, the phase difference alarm module 101 includes:
an exclusive nor gate;
a first pin of the exclusive-nor gate is used for inputting a clock to be detected, a second pin of the exclusive-nor gate is used for inputting a reference clock, and a third pin of the exclusive-nor gate is used for outputting a first pulse;
and a third pin of the exclusive-OR gate is connected with the false alarm filtering module.
It should be noted that the xor gate is a logic gate for implementing logical xor in digital logic, and if the two inputs have different levels, the output is a high level "1"; if the two inputs are at the same level, the output is at a low level "0". The exclusive nor gate is inverted on the basis of the exclusive or gate, namely, firstly, exclusive or operation is carried out on two input levels, then, an inverted value is obtained on the result of the exclusive or operation, if the two input levels are different, the output is low level '0', and if the two input levels are the same, the output is high level '1'.
The first pin of the exclusive-nor gate inputs a clock to be detected, and the second pin of the exclusive-nor gate inputs a reference clock. The level of the clock to be detected is the same as that of the reference clock, which indicates that no alarm signal or false alarm signal corresponding to the clock fault exists, and a pulse with a high level of 1 is output; the level of the clock to be detected is different from that of the reference clock, which indicates that an alarm signal and a false alarm signal corresponding to the clock fault possibly exist, and a pulse with a low level of 0 is output, wherein the pulse is a first pulse.
Meanwhile, a third pin of the exclusive-nor gate is connected with the false alarm filtering module, and the first pulse of the low level is transmitted to the false alarm filtering module.
In the embodiment, the phase difference between the clock to be detected and the reference clock is detected through the exclusive-nor gate, the circuit area is small, the integration difficulty is low, and therefore the digital clock phase difference detection circuit can be applied to various digital circuit design flows.
Optionally, as shown in fig. 4, the false alarm filtering module 102 includes:
a delay and an OR gate;
a first pin of the delayer is connected with the phase difference alarm module, and a second pin of the delayer is connected with a second pin of the OR gate;
and a first pin of the OR gate is connected with the phase difference alarm module, and a third pin of the OR gate is connected with the latch output module.
It should be noted that the or gate has a plurality of input terminals and an output terminal, and the output is a high level "1" as long as one of the input terminals is a high level "1"; the output is low only if all inputs are low "0".
The delay device is a circuit that can delay the pulse signal for a certain time. Under the condition that the level width of the first pulse acquired by the exclusive-or gate is smaller than the inherent delay time of the delayer, the delayer can delay the pulse signal, and in the inherent delay time, the first pulse of low level '0' is input into the first pin of the or gate, the first pulse of low level '0' is not input into the second pin of the or gate, and then, the signal of high level '1' is output from the third pin of the or gate; when the inherent delay time is over, the second pin of the or gate inputs the first pulse of low level "0", or the first pin of the or gate does not input the first pulse of low level "0", then the third pin of the or gate outputs the high level "1" signal. In the case that the level width of the first pulse acquired by the xor-not gate is greater than the inherent delay time of the delayer, because the delayer can delay the pulse signal, in the inherent delay time, the first pulse of low level "0" is input to the first pin of the or gate, and the first pulse of low level "0" is not input to the second pin of the or gate, then, the third pin of the or gate outputs a high level "1" signal; because the level width of the first pulse is larger than the inherent delay time of the delayer, the inherent delay time is over, the second pin of the OR gate inputs the first pulse of low level '0', the first pulse of the first pin of the OR gate inputs the first pulse of low level '0', then, the output of the third pin of the OR gate is still the signal of low level '0', and the signal of low level '0' is the alarm signal.
According to the working principle of a digital system, after the physical realization of the system clock in the domain, due to the difference of parasitic parameters on each branch, inherent clock edge deviation exists on each branch of the clock tree structure, and the filtering processing function realized by the delayer and the OR gate can filter false alarm signals of the inherent clock edge deviation between the clock to be detected and the reference clock, so that false alarm is avoided. Meanwhile, the inherent clock edge deviation can be increased after fault injection, the inherent delay time of the delayer can be adjusted according to the actual application scene, and the increased inherent clock edge deviation is filtered.
In addition, a third pin of the or gate is connected with the latch output module and can transmit the alarm signal to the latch output module.
In the embodiment, the delayer and the OR gate can filter the false alarm signal, so that the filtering processing of the alarm signal is realized, and the reliability of the fault detection of the safety chip is improved.
Alternatively, as shown in fig. 5, the delayer includes a plurality of delay units;
a plurality of delay units are connected in series;
the first pin of the target delay unit is connected with the second pin of the OR gate, the first pin of the target delay unit is also connected with the third pin of the delayer, and the target delay unit is any one of the plurality of delay units;
the third pin of the delayer is used for receiving the trimming selection signal.
It should be noted that the delay unit includes a plurality of delay units, and the delay units may be composed of any logic gate circuit, for example, the delay units may be inverters and buffers with different delay characteristics, the type of the delay unit does not affect the functional implementation of the present invention, and in this embodiment, the type of the delay unit is not limited.
The delay is composed of a group of delay units (delay unit 1, delay unit 2, delay unit 3, … …, delay unit n) connected in series. When a first pulse is input into a first pin of the delayer, an input signal at the input end of the delayer is changed from a high level '1' to a low level '0', the edge of the low level '0' signal generates delay within a preset delay time, the preset delay time passes, and the low level '0' signal arrives at the output end of the delayer again. The third pin of the delayer is used for receiving the trimming selection signal, the length of the preset delay time can be determined by a gating switch controlled by the trimming selection signal, and only one path of the gating switch is conducted at the same time. Generally, the more delay units the input signal at the input of the delay passes through, the longer the predetermined delay time.
According to the practical application scene, the number of the delay units can be adjusted by configuring the trimming selection signal before the delayer is used, so that the required preset delay time is adjusted, and the inherent phase difference of the clock generated in the system design is eliminated. The related adjustment operation can be implemented at any stage of chip test and chip application, the configuration trimming selection signal does not influence the functional implementation of the invention, meanwhile, the configuration trimming numerical value can be stored in an on-chip memory or an off-chip memory, and the selection of the storage position of the configuration trimming numerical value does not influence the functional implementation of the invention.
In the embodiment, the delayer comprises a plurality of delay units, and the delay time of the delayer can be adjusted by trimming the selection signal according to the requirements of different application scenes, so that the application range of fault detection of the safety chip can be enlarged, and meanwhile, the accuracy of filtering false alarm signals can be improved.
Optionally, the latch output module 103 includes a register;
the first pin of the register is connected with the third pin of the false alarm filtering module or the gate;
the second pin of the register transmits the alarm signal to the third pin of the register;
a third pin of the register outputs an alarm signal;
the fourth pin of the register receives a reset signal.
The first pin of the register can also be called as a clock end of the register, and the first pin of the register is connected with a third pin of the false alarm filtering module or the gate and can be used for receiving an alarm signal. When the output signal of the or gate of the false alarm filtering module is changed from high level "1" to low level "0", the clock end of the register generates a falling edge to trigger the register to generate action. At this time, the second pin of the register may immediately transmit the low level "0" signal received by the first pin to the third pin of the register, and maintain the continuous generation of the fault detection alarm signal of the low level "0", and meanwhile, the second pin of the register is the input end of the register, and the third pin of the register is the output end of the register.
And a fourth pin of the register is used for receiving a reset input signal, when the reset operation is needed, the fourth pin of the register receives the reset input signal, the register is reset, the alarm signal of the output end of the register is changed from low level '0' to high level '1', and the fault alarm is cleared.
In the embodiment, as the fault detection alarm signal can be continuously generated through the register, when the reset input signal is received, the fault alarm is cleared, so that a better alarm effect can be obtained.
Optionally, as shown in fig. 6, the phase difference alarm module 101 includes a plurality of exclusive nor gates and gates;
a first pin of a first XOR gate in the plurality of XOR gates is connected with a first clock pin to be detected of a first pin of the phase difference alarm module, and a second pin of the first XOR gate in the plurality of XOR gates is connected with a second pin of the phase difference alarm module;
a first pin of a second exclusive-nor gate in the plurality of exclusive-nor gates is connected with a second clock pin to be detected of the first pin of the phase difference alarm module, and a second pin of the second exclusive-nor gate in the plurality of exclusive-nor gates is connected with a second pin of the phase difference alarm module;
a third pin of the first exclusive-OR gate is connected with a first pin of the AND gate, and a third pin of the second exclusive-OR gate is connected with a second pin of the AND gate;
and a third pin of the AND gate is connected with the false alarm filtering module.
It should be noted that the and gate is a basic logic gate circuit for performing an and operation, and has a plurality of inputs and an output, and when all inputs are simultaneously at high level "1", the output is at high level "1", otherwise, the output is at low level "0".
The phase difference alarm module may include a plurality of exclusive nor gates, and two adjacent exclusive nor gates are connected to the same and gate.
Meanwhile, a first pin of the first exclusive nor gate is used for inputting a first clock to be detected, and a second pin of the first exclusive nor gate is used for inputting a reference clock; the first pin of the second exclusive nor gate is used for inputting a second clock to be detected, and the second pin of the second exclusive nor gate is used for inputting a reference clock. According to the basic principle of the AND gate, when it is detected that the first clock to be detected and the reference clock have no phase difference, the first XOR gate outputs the first pulse with high level 1, and when it is detected that the second clock to be detected and the reference clock have no phase difference, the second XOR gate outputs the first pulse with high level 1, and at the same time, the AND gate outputs a high level 1 signal.
In other cases, the and gate outputs a low "0" signal, and other cases include: detecting that a phase difference exists between a first clock to be detected and a reference clock, outputting a first pulse of low level '0' by a first exclusive nor gate, and simultaneously, detecting that a phase difference does not exist between a second clock to be detected and the reference clock, outputting a first pulse of high level '1' by a second exclusive nor gate; detecting that the first clock to be detected and the reference clock have no phase difference, the first XOR gate outputs a first pulse with a high level 1, and simultaneously, detecting that the second clock to be detected and the reference clock have a phase difference, the second XOR gate outputs a first pulse with a low level 0; and when detecting that the phase difference exists between the first clock to be detected and the reference clock, the first XOR gate outputs a first pulse with a low level of 0, and when detecting that the phase difference exists between the second clock to be detected and the reference clock, the second XOR gate outputs a first pulse with a low level of 0.
In this embodiment, the phase difference alarm module includes a plurality of exclusive nor gates, so that the detection of multiple clock signals to be detected can be simultaneously achieved.
The embodiment of the present invention further provides a terminal device, where the terminal device can achieve the technical effect in the embodiment of the method in fig. 1, and is not described herein again to avoid repetition.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner.
While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (7)
1. The utility model provides a safety chip fault detection circuit which characterized in that, includes phase difference alarm module, false alarm filtering module and latches output module, wherein:
the phase difference alarm module is used for receiving a clock to be detected and a reference clock, and performing phase detection on the clock to be detected and the reference clock to obtain a first pulse;
the input end of the false alarm filtering module is connected with the output end of the phase difference alarm module and is used for filtering the first pulse to acquire an alarm signal;
and the input end of the latch output module is connected with the output end of the false alarm filtering module and is used for latching the alarm signal.
2. The security chip fault detection circuit of claim 1, wherein the phase difference alarm module comprises:
an exclusive-nor gate;
a first pin of the exclusive nor gate is used for inputting the clock to be detected, a second pin of the exclusive nor gate is used for inputting the reference clock, and a third pin of the exclusive nor gate is used for outputting the first pulse;
and a third pin of the exclusive nor gate is connected with the false alarm filtering module.
3. The security chip fault detection circuit of claim 1, wherein the false alarm filtering module comprises:
a delay and an OR gate;
a first pin of the delayer is connected with the phase difference alarm module, and a second pin of the delayer is connected with a second pin of the OR gate;
and a first pin of the OR gate is connected with the phase difference alarm module, and a third pin of the OR gate is connected with the latch output module.
4. The security chip failure detection circuit of claim 3, wherein the delay comprises a plurality of delay cells;
the plurality of delay units are connected in series;
the first pin of the target delay unit is connected with the second pin of the OR gate, the first pin of the target delay unit is also connected with the third pin of the delayer, and the target delay unit is any one of the plurality of delay units;
the third pin of the delayer is used for receiving a trimming selection signal.
5. The security chip failure detection circuit of claim 1, wherein the latch output module comprises a register;
the first pin of the register is connected with the third pin of the false alarm filtering module or the gate;
the second pin of the register transmits the alarm signal to the third pin of the register;
the third pin of the register outputs the alarm signal;
a fourth pin of the register receives a reset signal.
6. The security chip fault detection circuit of claim 1, wherein the phase difference alarm module comprises a plurality of exclusive nor gates and gates;
a first pin of a first exclusive nor gate in the plurality of exclusive nor gates is connected with a first clock pin to be detected of a first pin of the phase difference alarm module, and a second pin of the first exclusive nor gate in the plurality of exclusive nor gates is connected with a second pin of the phase difference alarm module;
a first pin of a second exclusive nor gate in the plurality of exclusive nor gates is connected with a second to-be-detected clock pin of the first pin of the phase difference alarm module, and a second pin of the second exclusive nor gate in the plurality of exclusive nor gates is connected with a second pin of the phase difference alarm module;
a third pin of the first exclusive nor gate is connected with a first pin of the and gate, and a third pin of the second exclusive nor gate is connected with a second pin of the and gate;
and a third pin of the AND gate is connected with the false alarm filtering module.
7. A terminal device, characterized in that it comprises a security chip failure detection circuit according to any of claims 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011300168.6A CN114518528A (en) | 2020-11-19 | 2020-11-19 | Safety chip fault detection circuit and terminal equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011300168.6A CN114518528A (en) | 2020-11-19 | 2020-11-19 | Safety chip fault detection circuit and terminal equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114518528A true CN114518528A (en) | 2022-05-20 |
Family
ID=81595270
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011300168.6A Pending CN114518528A (en) | 2020-11-19 | 2020-11-19 | Safety chip fault detection circuit and terminal equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114518528A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116298635A (en) * | 2023-03-30 | 2023-06-23 | 海信家电集团股份有限公司 | IPM fault detection system, IPM fault detection method, IPM fault detection device and storage medium |
-
2020
- 2020-11-19 CN CN202011300168.6A patent/CN114518528A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116298635A (en) * | 2023-03-30 | 2023-06-23 | 海信家电集团股份有限公司 | IPM fault detection system, IPM fault detection method, IPM fault detection device and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI614634B (en) | Method and apparatus for detecting fault injection | |
| EP1798562B1 (en) | Qualified anomaly detection | |
| US20130044003A1 (en) | Intrusion Detection and Communication | |
| US10236871B2 (en) | Pulse width filtering circuit | |
| US10489595B2 (en) | Method and detection circuit for detecting security chip operating state | |
| US20100026358A1 (en) | Protection against fault injections of an electronic circuit with flip-flops | |
| JP6968234B2 (en) | Electronic devices and methods for performing data sampling integrity checks using flip-flops with relative delay | |
| CN103712642B (en) | A kind of method and device realizing safety detector oneself detection | |
| CN103441759A (en) | Phase frequency detector | |
| CN109657464A (en) | A kind of hardware Trojan horse detection method based on path delay analysis | |
| CN106788353A (en) | A kind of skewed clock correcting method and circuit, terminal device | |
| CN114518528A (en) | Safety chip fault detection circuit and terminal equipment | |
| JP2021047850A (en) | Electronic device and method for data-sampling integrity check using gated clock | |
| JPH02283120A (en) | Noise eliminator | |
| EP3291127B1 (en) | Active tamper detection circuit with bypass detection and method therefor | |
| CN103219970A (en) | Single-particle transient pulse width expanding method and circuit | |
| US7106116B2 (en) | Pulse duty deterioration detection circuit | |
| US9251379B2 (en) | Clock signal synchronization and disturbance detector | |
| EP2983102A1 (en) | Integrated circuit with distributed clock tampering detectors | |
| CN114338463B (en) | Safety detection circuit, equipment and detection method based on pulse contraction delay chain | |
| JP4703535B2 (en) | Semiconductor integrated circuit | |
| CN113689635B (en) | Anti-disassembly circuit structure and method for preventing false triggering | |
| JPH05304477A (en) | Sampling circuit | |
| CN103675648A (en) | Device applied to phase-locked loop irradiation experiment | |
| CN111800272B (en) | Reliability self-checking circuit and method for RO PUF output response |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |