CN114338463B

CN114338463B - Safety detection circuit, equipment and detection method based on pulse contraction delay chain

Info

Publication number: CN114338463B
Application number: CN202111677323.0A
Authority: CN
Inventors: 刘冬生; 李宗霖; 胡嘉杰; 杨圆辉; 胡昂; 朱令松
Original assignee: Wuhan Weide Equity Investment Partnership LP
Current assignee: Wuhan Weide Equity Investment Partnership LP
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2023-05-16
Anticipated expiration: 2041-12-31
Also published as: CN114338463A

Abstract

The application provides a safety detection circuit, equipment and a detection method based on a pulse contraction delay chain, which comprises a clock frequency division unit, a pulse contraction unit, a pulse recovery unit and a multiplexer, wherein the clock frequency division unit is used for dividing an input clock CLK_IN to obtain a frequency division clock CLK_DIV, and the frequency division clock CLK_DIV is used as a control clock of the pulse recovery unit; the clock signal processing circuit is also used for carrying OUT pulse control on the frequency division clock CLK_DIV to obtain a pulse clock CLK_OUT; the pulse shrinking unit comprises a plurality of pulse shrinking stages and is used for obtaining a multi-bit linkage signal after step-by-step pulse shrinking of a pulse clock CLK_OUT; the pulse recovery unit is used for processing the multi-bit linkage signal to obtain a group of multi-bit state values for distinguishing pulse from non-pulse; the multiplexer is used for selecting one state value from the multi-bit state values as an output value, and comparing the output value with a preset detection threshold value to determine whether an alarm is generated.

Description

Safety detection circuit, equipment and detection method based on pulse contraction delay chain

Technical Field

The application relates to the technical field of networks, in particular to a pulse contraction delay chain-based safety detection circuit, equipment and a detection method.

Background

The security chip is a device capable of independently generating and encrypting and decrypting the key, and is internally provided with an independent processor and a storage unit, and can store the key and characteristic data to provide encryption and security authentication services. The encryption is carried out by the security chip, the secret key is stored in hardware, and the stolen data cannot be decrypted, so that the business privacy and the data security are protected. However, the working environment of the security chip is increasingly complex, and is easily affected by an abnormal working environment and a malicious fault injection attack, so that the security chip has faults such as functional failure, and even can cause the leakage of data stored in the security chip, so that a specially designed security detection circuit is required to sense and detect the external working environment, and an alarm is given out when the working environment is abnormal.

The safety detection of the chip is generally realized by a built-in analog sensor (temperature, voltage and frequency) in the current safety chip, but under the complex circuit environment, the accuracy of the built-in sensor is affected, false alarm and missing alarm are easy to occur, the analog sensor has large circuit scale and high cost, special temperature sensors, voltage sensors and clock frequency sensors are required to be respectively designed for detecting different fault injection attacks, and the requirements for simultaneously detecting various abnormal conditions such as voltage, frequency and temperature cannot be met.

Meanwhile, many of the previous circuits used for fault detection of the security chip are based on ring oscillators and common delay chains. The detection circuit based on the ring oscillator can generate a periodic clock signal, when the external environment changes, the delay of the ring oscillator changes, the output clock frequency also changes, and the environment change is sensed by using the clock count generated by the ring oscillator, but the design of the digital ring oscillator is difficult to control, is greatly affected by the process, needs a complex calibration mechanism, and only senses the temperature and voltage change of a chip.

The detection circuit based on the common delay chain consists of a plurality of time sequence paths with different delays, and under the control of a clock, level overturning excitation is continuously generated, and the sampling trigger is reached through the time sequence paths. If the operating environment of the circuit is degraded, resulting in increased delay, a timing violation may occur in the timing path with longer delay, so that the sampling flip-flop samples to an unexpected value. However, the requirement on clock consistency of the circuit is very high, particularly on clock skew, and the circuit itself works under the condition of timing violations, so that metastable state problems easily occur to cause abnormal sensing results.

In view of this, overcoming the shortcomings of the prior art products is a problem to be solved in the art.

Disclosure of Invention

The technical problem that this application mainly solves is to provide a safety inspection circuit, equipment and detection method based on pulse shrinkage delay chain, and this application can perception chip temperature, voltage and the influence that the clock frequency changes bring simultaneously, carries out fault detection, and the circuit is based on digital standard unit design, is convenient for technology transplanting to the circuit scale is little, and the cost is lower.

In order to solve the technical problems, one technical scheme adopted by the application is as follows: the safety detection circuit based on the pulse contraction delay chain comprises a clock frequency division unit, a pulse contraction unit, a pulse recovery unit and a multiplexer, wherein the clock frequency division unit is connected with the pulse contraction unit, the pulse contraction unit is connected with the pulse recovery unit, the pulse recovery unit is connected with the multiplexer, and the clock frequency division unit is also connected with the pulse recovery unit;

the clock frequency dividing unit is used for dividing the input clock CLK_IN to obtain a frequency division clock CLK_DIV, and the frequency division clock CLK_DIV is used as a control clock of the pulse recovery unit; the clock frequency division unit is also used for carrying OUT pulse control on the frequency division clock CLK_DIV to obtain a pulse clock CLK_OUT;

the pulse shrinking unit comprises a plurality of pulse shrinking stages and is used for obtaining a multi-bit linkage signal after performing step-by-step pulse shrinking on the pulse clock CLK_OUT;

the pulse recovery unit is used for processing the multi-bit linkage signal to obtain a group of multi-bit state values for distinguishing pulse from non-pulse;

the multiplexer is used for selecting one state value from the state values with multiple bits as an output value, and comparing the output value with a preset detection threshold value to determine whether an alarm is generated.

Preferably, the clock frequency dividing unit comprises a D flip-flop, an inverter and an exclusive-or gate, wherein an input end of the inverter is connected with a Q end of the D flip-flop, an output end of the inverter is connected with a D end of the D flip-flop, and a CLK end of the D flip-flop is used for receiving an input clock clk_in; one input end of the exclusive-or gate is connected with the Q end of the trigger, the other input end of the exclusive-or gate is used for receiving a PHASE selection signal PHASE, and the output end of the exclusive-or gate is connected to the pulse contraction unit;

the Q end of the D trigger is used for outputting the pulse clock CLK_OUT; the D trigger is matched with the inverter together and used for dividing the input clock CLK_IN by two to obtain a divided clock CLK_DIV;

the exclusive or gate is used for determining whether to perform inversion processing on the divided clock clk_div according to the PHASE selection signal PHASE.

Preferably, the pulse shrinking unit comprises a plurality of pulse shrinking stages which are connected in sequence, wherein the output end of the previous pulse shrinking stage is connected with the input end of the next pulse shrinking stage;

each pulse contraction stage comprises an AND gate and a buffer, wherein the buffer is used for delaying the signal output by the previous stage unit; the input end of the buffer is the input end of the pulse contraction stage, the output end of the buffer is connected with the first input end of the AND gate, the second input end of the AND gate is connected with the input end of the buffer, and the output end of the AND gate is the output end of the pulse contraction stage;

the input end of the first pulse contraction stage in the plurality of cascade pulse contraction stages is used for receiving the pulse clock CLK_OUT; the output end of each pulse contraction stage is connected with the pulse recovery unit and is used for outputting the multi-bit linkage signal.

Preferably, the pulse recovery unit comprises a plurality of first triggers, a plurality of second triggers and a finite state machine;

the D end of each first trigger is connected with a high-level signal, the CLR end of each first trigger is connected with the first output end of the finite state machine, and the CLK end of each first trigger is correspondingly connected with the output end of each pulse contraction stage one by one;

the Q end of each first trigger is connected with the D end of each corresponding second trigger, the CE end of each second trigger is connected with the second output end of the finite state machine, and the CLK end of each second trigger is connected with a frequency division clock CLK_DIV;

the first trigger is used for selectively outputting a high-level signal or a low-level signal according to the shrinkage condition of the interlocking signal received by the CLK end;

the first output end of the finite state machine is used for outputting a zero clearing signal so as to periodically zero the output of the first trigger;

the second output end of the finite state machine is used for outputting a clock enabling signal CE so that the second trigger selectively outputs a signal currently output by the first trigger or latches original data according to the value of the clock enabling signal CE to obtain a group of multi-bit state values for distinguishing pulse from non-pulse.

Preferably, the first flip-flop is a D flip-flop with an asynchronous zero clearing function, and the output is zero cleared when clr=1.

Preferably, the second flip-flop is a D flip-flop with an enabling function, when ce=1, the Q terminal outputs D terminal data when a clock rising edge arrives, otherwise, the Q terminal locks the original data. Preferably, the pulse shrinking unit comprises 8 pulse shrinking stages, and the pulse recovering unit comprises 8 first triggers and 8 second triggers.

In order to solve the foregoing problems, another technical solution adopted in the present application is: providing an electronic device comprising a security detection circuit as described herein, one or more security detection circuits disposed at one or more locations of the circuit;

for each of the safety detection circuits, determining an optimal detection performance boundary according to the characteristics of the protected circuit itself to determine whether to generate an alarm according to the optimal detection performance boundary; when one or more of the security detection circuits issues an alarm, the electronic device generates an alarm and sends the alarm to an alarm processing system.

Preferably, the plurality of detection circuits are configured with different PHASE selection signals PHASE.

In order to solve the foregoing problem, another technical solution is adopted in the embodiments of the present application: the method for detecting the working state of the safety chip is applied to the safety detection circuit, and comprises the following steps:

when the working environment is normal, determining a detection performance boundary Fn1 of the safety detection circuit;

simulating an abnormal working environment, and determining a detection performance boundary Fn2 of a safety detection circuit;

determining an optimal detection performance boundary Fn0 according to the characteristics of the protected circuit, wherein Fn2 is smaller than Fn0 and smaller than Fn1, and each of Fn0, fn1 and Fn2 represents a bit number;

the multiplexer is configured to select a state value corresponding to the output detection performance boundary Fn0 as an output value, and compare the output value with a preset detection threshold value to determine whether an alarm is generated.

The embodiment of the application provides a safety detection circuit based on pulse shrinkage delay chain, the safety detection circuit is with the influence of environmental factors such as chip voltage, temperature for pulse shrinkage delay chain delay characteristic's unit shrink width produces the change for the periodic pulse that has certain pulse width, and under different delay characteristics, its pulse shrinkage is to the number of times difference of zero, based on this characteristic, can distinguish environmental factors's influence to the circuit production, realizes the function of perception external environment change.

Further, the purpose of the security detection circuit is to protect a specific circuit (e.g. an encryption circuit), and the security detection circuit senses a change in environment and issues an alarm to notify the alarm processing system to take security measures for the protected circuit when the working environment is abnormal. The safety detection circuit thus operates with the same clock as the circuit to be protected and generates periodic pulses with a certain pulse width under the control of this clock. When clock characteristics change (such as clock frequency is fast and clock burrs exist) due to fault injection or external environment deterioration of the clock, the generated periodic pulse width changes, and when the pulse passes through a pulse contraction stage, the pulse is contracted to zero times to be different, and based on the characteristics, the influence of the clock changes on a circuit can be distinguished, so that the perception of clock faults is realized.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following description will briefly explain the drawings that are required to be used in the embodiments of the present application. It is obvious that the drawings described below are only some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

Fig. 1 is a diagram of an overall structure of a security detection circuit according to an embodiment of the present application;

FIG. 2 is a detailed block diagram of each unit of a security detection circuit according to an embodiment of the present application;

FIG. 3 is a timing diagram of the operation of the safety detection circuit under different environments and clock characteristics according to the embodiment of the present application;

FIG. 4 is a schematic diagram of a detection method according to an embodiment of the present disclosure;

FIG. 5 is a graph of reference relationships between Fn and different environments and clock characteristics provided by embodiments of the present application;

FIG. 6 is a schematic diagram of a first example of a security detection circuit deployment provided in an embodiment of the present application;

fig. 7 is a second example of a deployment of a security detection circuit according to an embodiment of the present application;

fig. 8 is a flowchart of a method for detecting an operating state of a security chip according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

In the description of the present application, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate an orientation or positional relationship based on that shown in the drawings, merely for convenience of description and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In this application, the term "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the application. In the following description, details are set forth for purposes of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been shown in detail to avoid obscuring the description of the present application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

It should be noted that, because the method in the embodiment of the present application is executed in the electronic device, the processing objects of each electronic device exist in the form of data or information, for example, time, which is substantially time information, it can be understood that in the subsequent embodiment, if the size, the number, the position, etc. are all corresponding data, so that the electronic device processes the data, which is not described herein in detail.

Example 1:

fig. 1 is a diagram of an overall structure of a security detection circuit according to an embodiment of the present application. The safety detection circuit in this embodiment is described with reference to fig. 1 and fig. 2-3. The safety detection circuit comprises a clock frequency division unit, a pulse contraction unit, a pulse recovery unit and a multiplexer. The clock frequency division unit is connected with the pulse contraction unit, the pulse contraction unit is connected with the pulse recovery unit, the pulse recovery unit is connected with the multiplexer, and the clock frequency division unit is also connected with the pulse recovery unit; the clock frequency dividing unit is used for dividing the input clock CLK_IN to obtain a frequency division clock CLK_DIV, and the frequency division clock CLK_DIV is used as a control clock of the pulse recovery unit; the clock frequency division unit is also used for carrying OUT pulse control on the frequency division clock CLK_DIV to obtain a pulse clock CLK_OUT; the pulse shrinking unit comprises a plurality of pulse shrinking stages and is used for obtaining a multi-bit linkage signal after performing step-by-step pulse shrinking on the pulse clock CLK_OUT; the pulse recovery unit is used for processing the multi-bit linkage signal to obtain a group of multi-bit state values for distinguishing pulse from non-pulse; the multiplexer is used for selecting one state value from the state values with multiple bits as an output value, and comparing the output value with a preset detection threshold value to determine whether an alarm is generated.

The clock frequency dividing unit comprises a D trigger, an inverter and an exclusive-OR gate, wherein the input end of the inverter is connected with the Q end of the trigger, the output end of the inverter is connected with the D end of the D trigger, and the CLK end of the D trigger is used for receiving an input clock CLK_IN; one input end of the exclusive-or gate is connected with the Q end of the D trigger, the other input end of the exclusive-or gate is used for receiving a PHASE selection signal PHASE, and the output end of the exclusive-or gate is connected to the pulse contraction unit; the Q end of the D trigger is used for outputting a pulse clock CLK_OUT; the D trigger is matched with the inverter together and used for dividing the input clock CLK_IN by two to obtain a divided clock CLK_DIV; the exclusive or gate is used for determining whether to perform inversion processing on the divided clock clk_div according to the PHASE selection signal PHASE.

Specifically, the clock frequency dividing unit is composed of a D trigger, a two-input exclusive-OR gate and an inverter. The input clock CLK_IN is input from the end of the D trigger CLK, the initial state output 0 of the end Q of the D trigger is set, the output passes through an inverter, the end Q of the D trigger is set at 1, when the rising edge of the input clock CLK_IN arrives, the output passes through the inverter, the end D is set at 0, and when the rising edge of the CLK_IN arrives again, the end Q of the D trigger outputs 0. As shown IN fig. 3, after rising edges of clk_in come twice, the Q end of the D flip-flop outputs an initial state 0, thereby implementing frequency division of the input clock clk_in and obtaining the divided clock clk_div as a control clock of the pulse recovery unit. The divided clock clk_div is also a periodic pulse with a certain pulse width, which is connected to the exclusive or gate input, controlled by another PHASE selection signal PHASE connected to the exclusive or gate input. When phase=0, the output signal clk_out=clk_div; when phase=1, the output signal clk_out is an inverted signal of clk_div, and the low-level pulse width of clk_div becomes the high-level pulse width of clk_out, and passes through the pulse-shrinking stage as an input of the pulse-shrinking unit.

The pulse contraction unit comprises a plurality of pulse contraction stages which are connected in sequence, wherein the output end of the previous pulse contraction stage is connected with the input end of the next pulse contraction stage; each pulse contraction stage comprises an AND gate and a buffer, wherein the buffer is used for delaying the signal output by the previous stage unit; the input end of the buffer is the input end of the pulse contraction stage, the output end of the buffer is connected with the first input end of the AND gate, the second input end of the AND gate is connected with the input end of the buffer, and the output end of the AND gate is the output end of the pulse contraction stage; the input end of the first pulse contraction stage in the plurality of cascade pulse contraction stages is used for receiving the pulse clock CLK_OUT; the output end of each pulse contraction stage is connected with the pulse recovery unit and is used for outputting the multi-bit linkage signal.

In an alternative embodiment, the pulse shrinking unit comprises 8 pulse shrinking stages,

for the first-stage pulse contraction stage, the upper-stage unit refers to a clock frequency division unit, namely, the output end of the exclusive-or gate is connected with one input end of an and gate (first-stage pulse contraction stage) after passing through a buffer (first-stage pulse contraction stage), and the other input end of the and gate is directly connected with the output end of the exclusive-or gate; the buffer is used for delaying the signal output by the previous stage unit.

For other stages of pulse-shrinking stages, the upper stage unit refers to the upper stage of pulse-shrinking stage.

In the embodiment shown in fig. 2, the pulse shrinking unit includes 8 pulse shrinking stages, and the periodic pulse clk_out with a certain pulse width generated by the clock frequency dividing unit is subjected to progressive pulse shrinking. The pulse contraction unit consists of two input AND gates, contracts the high-level pulse width of CLK_OUT, and outputs the pulse chain after each pulse width contraction bit by bit in parallel to obtain 8-bit signals chain [7:0]. Wherein, each bit of chain is gradually narrowed in pulse width along with the rising of the bit number, such as the pulse width of chain [0], chain [1] and chain [2] in the case of A in FIG. 3; it may also be fully contracted with a signal of a continuously low level, such as chain 3. The chain i-1 generated in the previous stage is delayed by two inputs of an AND gate, one of which is delayed by a buffer and the other of which is not delayed by a specific delay, and forms a delay difference delta t. As shown in FIG. 3, after the pulse passes through the AND gate, the high pulse width of chain [ i ] generated at this stage is reduced by a width of Δt.

In this embodiment, the pulse recovery unit includes a plurality of first flip-flops, a plurality of second flip-flops, and a finite state machine; the D end of each first trigger is connected with a high-level signal, the CLR end of each first trigger is connected with the first output end of the finite state machine, and the CLK end of each first trigger is connected with the output end of each pulse contraction stage in a one-to-one correspondence manner; the Q end of each first trigger is correspondingly connected with the D end of one second trigger, the CE end of each second trigger is connected with the second output end of the finite state machine, and the CLK end of each second trigger is connected with a frequency division clock CLK_DIV;

the first output end of the finite state machine is used for outputting a zero clearing signal so as to periodically zero the output of the first trigger; the second output end of the finite state machine is used for outputting a clock enabling signal CE so that the second trigger selectively outputs a signal currently output by the first trigger or latches original data according to the value of the clock enabling signal CE to obtain a group of multi-bit state values for distinguishing pulse from non-pulse.

Specifically, when the CLK end of the first trigger receives the interlock signal chian [ i ] and is not completely contracted, the first trigger continuously outputs a high level signal under the condition that the first trigger does not have a clear signal, and when the CLK end of the first trigger receives the interlock signal chian [ i ] and is completely contracted, the first trigger continuously outputs a low level signal;

the first output end of the finite state machine is used for outputting a zero clearing signal so as to periodically zero the output of the first trigger; the second output terminal of the finite state machine is used for outputting a clock enable signal CE to control the second trigger to output the signal output by the first trigger, so as to obtain a group of multi-bit binary state values for distinguishing pulse from non-pulse.

The first flip-flop is a D flip-flop with an asynchronous zero clearing function, and the output is zero cleared when clr=1. The second trigger is a D trigger with an enabling function, when ce=1, the Q terminal outputs D terminal data when the clock rising edge arrives, otherwise, the Q terminal locks the original data.

In the embodiment shown in fig. 2, the pulse recovery unit includes 8 first flip-flops and 8 second flip-flops, where the first flip-flop is a D flip-flop with an asynchronous zero clearing function, and the output is zero cleared when clr=1; the second trigger is a D trigger with an enabling function, when CE=1, the Q end outputs D end data when the clock rising edge arrives, otherwise, the Q end locks the original data; and a finite state machine FSM that controls the timing of these flip-flops. The first flip-flop and the second flip-flop process the multi-bit signal chain [7:0] generated by the pulse shrinking unit.

Specifically, the first flip-flop is controlled by a signal chain [7:0] generated by the pulse shrinking unit, and if a signal chain [ i ] is a periodic pulse, under the triggering of the pulse rising edge, the first flip-flop D is terminated with 1, so that status_inv [ i ] =1. If a pulse width is fully contracted, the first flip-flop is not triggered with a continuously low signal, status_inv [ i ] =0. The FSM is used for generating a proper clear signal CLR, and carrying out periodic clear on the first trigger, so that the first trigger can be reset after being triggered by the signal, and waiting for the next signal trigger. At the same time, FSM generates a proper clock enable signal CE, which allows the second flip-flop to output the output value status_inv [7:0] of the first flip-flop under the action of the control clock CLK_DIV generated by the clock frequency division unit, so as to obtain a group of 8-bit binary state values STATUS [7:0] for distinguishing pulse from non-pulse, and the corresponding bit of the corresponding state value of the contraction result (whether the pulse width is completely contracted) of each stage of pulse contraction stage is 1 if the pulse width is not completely contracted, otherwise, the corresponding bit is 0.

Specifically, the FSM is configured to generate a suitable timing sequence, which is composed of a plurality of D flip-flops and basic logic gates, and controls the clear signal CLR of the first flip-flop and the clock enable signal CE of the second flip-flop. The state machine consists of four states, namely CLEAR (CLEAR), WAIT TRIGGER (WAIT 0), WAIT TRIGGER (WAIT 1) and TRIGGER (TRIGGER), and is sequentially and circularly switched under the control of a working clock CLK_DIV.

In the CLEAR state, the state machine ce=0 and clr=1, CLEARs the first flip-flop output, status_inv [ i ] =0.

In WAIT0 state, ce=0, clr=0; in WAIT1 state, ce=1, clr=0. In the WAIT0 and WAIT1 states, the first trigger WAITs for the signal chain [ i ] generated by the pulse shrinking unit to trigger. Since clk_out generated by the clock dividing unit is a periodic signal, and the generated chain i is also a periodic pulse, the first flip-flop is triggered by the rising edge of the chain i pulse during WAIT0 and WAIT1, so that status_inv i=1. For the fully contracted digital pulse width, the signal chain [ j ] with continuous low level is not triggered, and the status_inv [ j ] =0 is kept.

In the TRIGGER state, since ce=1, the second flip-flop outputs status=status_inv on the rising edge of clk_div, and causes ce=0. Since CLK_OUT generated by the clock dividing unit is a periodic signal, and the chain [7:0] and status_inv [7:0] generated by the signal are periodic, if the clock characteristics or the working environment are not changed, the status_inv value acquired by the second flip-flop at the rising edge of the clock is the same in each TRIGGER state, and the obtained STATUS [7:0] is stable and unchanged.

For each case shown in fig. 3, the pulse is completely contracted in chain [3] (a clock frequency is normal), chain [2] (B clock has burrs), chain [1] (C clock frequency is increased), chain [2] (D clock frequency is unchanged, temperature voltage is deteriorated, Δt is increased to Δt'), and thus the obtained state values STATUS are 0000_0111, 0000_0011, 0000_0001, 0000_0011, respectively.

In the embodiment shown in fig. 2, the multiplexer MUX is controlled by one or more bit select signals sel to select the STATUS output generated by the one bit pulse recovery unit. The state value reflects the shrinking result of each pulse shrinking stage, specifically, when a periodic pulse with a certain pulse width passes through the multi-stage pulse shrinking stage, the pulse width is shrunk but not shrunk to zero, the corresponding multi-bit state value is 1, and after a certain stage is completely shrunk to zero, the state value of the bit and the following states is 0.

Illustratively, referring to the case a of fig. 3, after the pulse is contracted by the 1 st-3 rd pulse contraction stage, the pulse width is narrowed stepwise; after passing through the 4 th pulse contraction stage, the pulse is completely contracted to 0, so that status=0000_0111, the lower three-bit values are all 1, and the fourth and higher bit values are all 0.

Example 2:

the present application also provides an electronic device, which includes the security detection circuit according to embodiment 1, where one or more security detection circuits are disposed at one or more locations of the circuit, and for each of the security detection circuits, an optimal detection performance boundary is determined according to a characteristic of the protected circuit itself, so as to determine whether to generate an alarm according to the optimal detection performance boundary, and when one or more of the security detection circuits generate an alarm, the alarm is generated and sent to an alarm processing system.

Referring to fig. 6, when the area of the protected circuit is large, local attack (such as laser irradiation) may cause different positions of the circuit, the working environment is greatly different, or the protection circuit uses a plurality of working clocks. Thus, in embodiments of the present application, a first deployment example may be employed, where one or more security detection circuits may be deployed at one or more locations in a circuit, each security detection circuit determining its respective detection performance boundary, and when one or more of the security detection circuits raise an alarm, an alarm is generated and sent to an alarm processing system.

Still further referring to fig. 7, in an embodiment of the present application, in combination with the circuit embodiment provided in the first aspect, a second deployment example may be employed. In this example, a plurality of detection circuits are configured with different PHASE selection signals PHASE, some circuits operate with phase=0, and the high-level pulse width of the original input clock is shrunk and detected; the remaining circuit may operate with phase=1, convert the low level pulse width of the original input clock into the high level pulse width, shrink, and detect. In this example, both the high and low pulse widths of the clock are contracted and detected, and when one or more of the security detection circuits raise an alarm, an alarm is generated and sent to the alarm processing system. Compared with the first deployment example, the detection sensitivity and the fault perception universality of the safety detection circuit are improved, and particularly when the clock duty ratio is changed due to the change of external conditions, the fault can be effectively detected when the protected circuit works abnormally.

Example 3:

the present embodiment provides a method for detecting an operating state of a security chip, which is applied to the security detection circuit described in embodiment 1, and the method includes:

s1: when the working environment is normal, determining a detection performance boundary Fn1 of the safety detection circuit;

s2: simulating an abnormal working environment, and determining a detection performance boundary Fn2 of a safety detection circuit;

s3: determining an optimal detection performance boundary Fn0 according to the characteristics of the protected circuit, wherein Fn2 is smaller than Fn0 and smaller than Fn1, and each of Fn0, fn1 and Fn2 represents a bit number;

s4: the multiplexer is configured to select a state value corresponding to the output detection performance boundary Fn0 as an output value, and compare the state value with a preset detection threshold value to determine whether an alarm is generated.

First, referring to fig. 4 and 5, when the operating environment is normal, the detection performance boundary Fn1 of the safety detection circuit is determined.

In the state value STATUS, a bit value is 1, and a bit number of which the value of the next bit is 0 is Fn, if the working environment of the circuit is deteriorated, the clock pulse width is narrowed or the delay deltat is increased, the pulse is shrunk to zero at the earlier pulse shrinking stage, so that the STATUS representing the pulse shrinking state is changed from 1 to 0 at the lower bit, fn is reduced, and the influence of the working environment and the clock characteristic change on Fn is reflected in fig. 5.

Referring to fig. 4, when the circuit operating environment is normal, the selection signal sel of the MUX is changed, and the output is selected from bit 1 of the STATUS, so that the output of bit i is selected by the MUX to be 1, and the output of bit i+1 is 0, and fn1=i is the performance boundary of the safety detection circuit in the normal operating environment.

Second, in combination with fig. 4 and 5, the abnormality of the working environment is simulated, and the detection performance boundary Fn2 of the safety detection circuit is determined.

Specifically, by increasing the clock frequency of the target circuit, increasing the working temperature of the chip, reducing the working voltage of the chip, and the like, the abnormal working environment is simulated, especially when the function of the protected circuit is inconsistent with the expected one, the selection signal sel of the MUX is changed, the 1 st bit of the STATUS is selected to output, the j-th bit is selected to output, the j+1 bit is 0, FN2=j is the performance boundary of the safety detection circuit in the abnormal working environment, and the abnormal working environment usually causes Fn2 to be smaller than Fn1.

In the third step and the fourth step, referring to fig. 4 and fig. 5, an optimal detection performance boundary Fn0 is determined according to the characteristics of the protected circuit, and the MUX selects and outputs a state value corresponding to the detection performance boundary Fn0 as an output value, and compares the state value with a preset detection threshold value to determine whether an alarm is generated.

Specifically, the selection signal sel of the MUX is changed, and any one bit of outputs from Fn2 to Fn1 of the STATUS is selected, so that when the working environment of the circuit is in a critical condition of normal and abnormal, the output is 0, and a safety alarm is sent. Otherwise, the output is 1. The detection performance boundary Fn0 is determined according to the requirement of circuit detection and the characteristics of the protected circuit, if the protected circuit is easily influenced by environment to fail, and higher detection sensitivity is required, the selected bit number should be closer to Fn2, otherwise, in order to reduce the probability of false alarm generated by the detection circuit, the selected bit number should be closer to Fn1.

Compared with the prior art, the application has the remarkable advantages that:

(1) Compared with an analog sensor and a circuit based on a ring oscillator, the circuit can sense the influence caused by the temperature, the voltage and the clock frequency change of the chip at the same time, performs fault detection, is based on digital standard unit design, is convenient for process transplantation, has small circuit scale and is low in cost.

(2) Compared with a detection circuit based on a common delay chain, the sensing of the working environment is not based on the idea of whether the time sequence path is illegal, the risk of metastable state generated by the output of the sampling trigger is reduced, and the reliability of the safety detection circuit is improved.

The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the patent application, and all equivalent structures or equivalent processes using the descriptions and the contents of the present application or other related technical fields are included in the scope of the patent application.

Claims

1. The safety detection circuit based on the pulse contraction delay chain is characterized by comprising a clock frequency division unit, a pulse contraction unit, a pulse recovery unit and a multiplexer, wherein the clock frequency division unit is connected with the pulse contraction unit, the pulse contraction unit is connected with the pulse recovery unit, the pulse recovery unit is connected with the multiplexer, and the clock frequency division unit is also connected with the pulse recovery unit;

2. The safety detection circuit according to claim 1, wherein the clock frequency dividing unit includes a D flip-flop, an inverter, and an exclusive-or gate, an input terminal of the inverter is connected to a Q terminal of the D flip-flop, an output terminal of the inverter is connected to a D terminal of the D flip-flop, and a CLK terminal of the D flip-flop is configured to receive the input clock clk_in; one input end of the exclusive-or gate is connected with the Q end of the trigger, the other input end of the exclusive-or gate is used for receiving a PHASE selection signal PHASE, and the output end of the exclusive-or gate is connected to the pulse contraction unit;

3. The safety detection circuit according to claim 1, wherein the pulse shrinking unit comprises a plurality of pulse shrinking stages connected in sequence, wherein the output end of the previous pulse shrinking stage is connected with the input end of the next pulse shrinking stage;

4. A safety detection circuit according to claim 3, wherein the pulse recovery unit comprises a plurality of first flip-flops, a plurality of second flip-flops and a finite state machine;

the Q end of each first trigger is correspondingly connected with the D end of each corresponding second trigger, the CE end of each second trigger is connected with the second output end of the finite state machine, and the CLK end of each second trigger is connected with a frequency division clock CLK_DIV;

5. The security detection circuit of claim 4 wherein the first flip-flop is a D flip-flop with an asynchronous zero function, the output zero when CLR = 1.

6. The security detection circuit of claim 4, wherein the second flip-flop is a D flip-flop with an enable function, and when ce=1, the Q terminal outputs D terminal data when a clock rising edge arrives, otherwise the Q terminal latches the original data.

7. A safety detection circuit according to claim 3, wherein the pulse shrinking unit comprises 8 pulse shrinking stages, and the pulse recovering unit comprises 8 first flip-flops and 8 second flip-flops.

8. An electronic device comprising a security detection circuit as claimed in any one of claims 1 to 7, one or more security detection circuits being disposed at one or more locations of the circuit;

9. The electronic device of claim 8, wherein the plurality of detection circuits configure different PHASE selection signals PHASE.

10. A method for detecting the operation state of a security chip, wherein the method is applied to the security detection circuit as claimed in any one of claims 1 to 7, and comprises the following steps:

the multiplexer is configured to select a state value corresponding to the output detection performance boundary Fn0 as an output value, and compare the state value with a preset detection threshold value to determine whether an alarm is generated.