CN114513167A - Communication module and battery management system - Google Patents
Communication module and battery management system Download PDFInfo
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- CN114513167A CN114513167A CN202210413538.XA CN202210413538A CN114513167A CN 114513167 A CN114513167 A CN 114513167A CN 202210413538 A CN202210413538 A CN 202210413538A CN 114513167 A CN114513167 A CN 114513167A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/001—Details of arrangements applicable to more than one type of frequency demodulator
- H03D3/003—Arrangements for reducing frequency deviation, e.g. by negative frequency feedback
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
- H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
- H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
- H01M2010/4278—Systems for data transfer from batteries, e.g. transfer of battery parameters to a controller, data transferred between battery controller and main controller
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
Abstract
The invention discloses a communication module and a battery management system. The communication module comprises a high-pass filter, a counting unit and an adjusting unit, wherein the input end of the counting unit is connected with the output end of the high-pass filter, the output end of the counting unit is connected with the adjusting unit, and the output end of the adjusting unit is connected with the output end of the high-pass filter. The invention solves the problem that the high-pass filter can generate time delay, so that the voltage at the tail end of the continuous pulses of the output end signal of the high-pass filter can only gradually recover to the common mode level, and finally the duty ratio of a demodulated signal deviates.
Description
Technical Field
The invention relates to the technical field of new energy, in particular to a communication module and a battery management system.
Background
In a battery management system, when a modulated signal is received, a communication module of the battery management system needs to firstly process the modulated signal through a high-pass filter to form a signal which is convenient for being processed by a detector, and then demodulate a signal at an output end of the high-pass filter through the detector. However, the high-pass filter is built by a resistor and a capacitor, and the resistor and the capacitor generate time delay, so when the output end signal jumps to the common mode level, the common mode level is not directly jumped to but gradually restored to the common mode level. When the detector demodulates the signal, the voltage of the signal needs to be restored to be close to the common mode level so as to be demodulated into a low-level signal, the gradual restoration process is mistakenly demodulated into a high-level signal, and finally, when the detector detects the signal, the duty ratio of the output demodulated signal is larger.
Disclosure of Invention
The invention mainly aims to provide a communication module, aiming at solving the problem of duty ratio deviation of a demodulation signal of the communication module.
In order to achieve the above object, the present invention provides a communication module applied in a battery management system, wherein the communication module includes a high-pass filter, the number of pulses of consecutive pulses of an output signal of the high-pass filter is M, and the communication module further includes:
the counting unit is used for outputting corresponding counting trigger signals when detecting that the number of rising edges of signals at the output end of the high-pass filter reaches M or the number of falling edges reaches M minus 1;
the adjusting unit is respectively connected with the output end of the counting unit and the output end of the high-pass filter, and is used for adjusting the voltage of the output end signal of the high-pass filter to a common-mode level when receiving the counting trigger signal;
wherein M is greater than 1.
In one embodiment, the counting unit includes:
the counter is used for sequentially outputting corresponding counting signals when each rising edge or each falling edge of the output end signal of the high-pass filter is detected;
the multi-selection switch is used for selecting one of the plurality of counting signals as the counting trigger signal to be output to the adjusting unit according to the duty ratio adjusting requirement of the demodulation signal corresponding to the output end signal of the high-pass filter or the number of continuous pulses of the output end signal of the high-pass filter.
In one embodiment, the counter comprises:
the input end of the first-stage D trigger is connected with a first level signal, the input ends of the second-stage to Nth-stage D triggers are connected with the output end of the previous-stage D trigger, and the output end of each-stage D trigger outputs one path of counting signal; the reset ends of the D triggers of each stage are interconnected, and the interconnected end is used as the reset end of the counter; the clock ends of the D flip-flops of each stage are interconnected, and the interconnection ends are used for accessing signals at the output end of the high-pass filter;
and the N is more than or equal to the M.
In one embodiment, the adjusting unit includes:
the delay circuit is used for delaying the counting trigger signal when receiving the trigger signal and sequentially outputting a first delay signal and a second delay signal with the phase opposite to that of the first delay signal;
the AND logic unit is used for outputting an opening control signal when receiving the first delay signal and outputting a closing control signal when receiving the first delay signal and the second delay signal;
the controlled end of the switch unit is connected with the output end of the logic unit, the output end of the switch unit is connected with the output end of the high-pass filter, the switch unit is switched on when receiving the starting control signal so as to adjust the voltage of the output end signal of the high-pass filter to the common mode level, and the switch unit is switched off when receiving the closing control signal so as to stop adjusting the voltage of the output end signal of the high-pass filter to the common mode level.
In one embodiment, the delay circuit includes:
the input end of the first delayer is connected with the counting unit, and the first delayer is used for delaying the counting trigger signal and outputting a first delayed signal;
and the input end of the second delayer is connected with the output end of the first delayer, and the second delayer is used for delaying and inverting the first delay signal so as to output the second delay signal.
In one embodiment, the second delay device comprises an odd number of inverters connected in series in sequence.
In an embodiment, the delay circuit is further configured to output a third delay signal to a reset terminal of the counting unit when receiving the counting trigger signal, so as to reset the counting unit; wherein the delay time of the third delay signal is greater than the delay time of the second delay signal.
In one embodiment, the delay circuit includes:
and the input end of the third delayer is connected with the output end of the second delayer, and the output end of the third delayer is used for delaying the second delay signal so as to output the third delay signal.
In one embodiment, the switching unit includes a MOS transistor.
The invention also provides a battery management system which comprises the communication module.
According to the technical scheme, the number of rising edges or the number of falling edges of the output end signal of the high-pass filter is calculated by the counting unit, and when the number of the rising edges reaches the number M of continuous pulses of the high-pass filter or the number of the falling edges reaches the number M of the continuous pulses minus 1, the counting trigger signal is output to the adjusting unit, so that the adjusting unit can rapidly pull down the potential of the signal at the output end of the high-pass filter to a common mode level instead of gradually recovering to the common mode level when receiving the counting trigger signal, and the duty ratio cannot deviate when a detector at the rear stage demodulates the signal. Compared with the traditional scheme of adjusting the duty ratio of the signal at the output end of the high-pass filter according to the pre-stored time constant to eliminate the deviation of the duty ratio caused by the time constant, the invention only needs to detect the number of the rising edges or the falling edges of the signal at the output end of the high-pass filter, does not need to acquire the time constant of the high-pass filter, can be suitable for the high-pass filters with different time constants, has stronger compatibility, can not cause the problem of inaccurate duty ratio adjustment precision because the time constant of the pre-stored time constant is different from the actual time constant even if the high-pass filters of the same type are different, and has higher adjustment precision.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a circuit diagram of a communication module according to an embodiment of the present invention;
FIG. 2 is a waveform diagram of a key node circuit according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of another embodiment of a communication module of the present invention;
fig. 4 is a circuit diagram of a communication module according to another embodiment of the present invention.
the implementation, functional features and advantages of the present invention will be further described with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In addition, the descriptions related to "first", "second", etc. in the present invention are only for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The invention provides a communication module applicable to a battery management system, which can solve the problem that the duty ratio of a demodulation signal demodulated by a detector is deviated due to time delay generated by a high-pass filter in the communication module.
Referring to fig. 1, fig. 1 is a circuit block diagram of a communication module according to an embodiment of the present invention. In an embodiment, the communication module comprises a high pass filter 30, a counting unit 10 and an adjusting unit 20. The high-pass filter 30 receives the modulated signal and outputs the modulated signal after processing, specifically referring to fig. 2, fig. 2 is a schematic diagram of waveforms of the modulated signal and a signal at an output end of the high-pass filter, and A, B waveforms are both differential waveforms as an example; the waveform A is a modulated signal, the waveform B is an output end signal of a high-pass filter, and the output end signal of the high-pass filter changes up and down by taking a common mode level as a center and comprises a continuous pulse and a low level. Wherein the number of consecutive pulses coincides with the number of consecutive pulses of the modulated signal.
The counting unit 10 is configured to output a corresponding counting trigger signal when detecting that the number of rising edges of the signal at the output end of the high-pass filter reaches M or the number of falling edges reaches M minus 1.
The adjusting unit 20 is respectively connected to the output end of the counting unit 10 and the output end of the high-pass filter 30, and the adjusting unit 20 is configured to adjust the signal voltage at the output end of the high-pass filter to a common mode level when receiving the counting trigger signal; wherein M is greater than 1.
In the present embodiment, the count scale of the counting unit 10 is greater than or equal to M. But only needs to trigger the output of the count trigger signal when the count reaches M. For example, when the count number is greater than M, a data selector may be provided to select an output terminal with the count number M to output a count trigger signal. When the counting unit 10 counts that the number of rising edges of the output end signal of the high-pass filter reaches M or the number of falling edges reaches M minus 1, it can be determined that the continuous pulse of the output end signal of the high-pass filter has ended, which means that the output end signal of the high-pass filter needs to jump to a low level, and at this time, the counting unit 10 outputs a counting trigger signal to control the operation of the adjusting unit. It should be explained that the counting scale is M, which can be interpreted as outputting the counting trigger signal when the counting unit 10 counts to M.
The adjusting unit 20 can instantly pull down the potential of the output signal of the high-pass filter to the common mode level in a short time when receiving the counting trigger signal, so as to eliminate the delay problem of the last falling edge of the continuous pulse of the output signal of the high-pass filter, and further, when the signal at the output end of the high-pass filter is demodulated by the later-stage detector, the duty ratio is not deviated. Specifically, referring to fig. 3, the adjusting unit 20 may include a control unit and a switching unit 23, the control unit is connected to a controlled terminal of the switching unit 23, and an output terminal of the switching unit 23 is connected to an output terminal of the high pass filter 30. The control unit 23 may output a start control signal to the controlled terminal of the switch unit 23 when receiving the count trigger signal, so that the output terminal of the switch unit 23 may regulate the voltage at the output terminal of the high pass filter to the common mode level. In addition, the control unit is also used for outputting a reset signal to reset the counting unit 10 so as to wait for the next continuous pulse of the output end signal of the high-pass filter and carry out duty ratio adjustment. The control unit can be built by adopting a pure hardware circuit and is arranged in the chip.
According to the technical scheme, the counting unit 10 is used for calculating the number of rising edges or the number of falling edges of the signal at the output end of the high-pass filter 30, and when the number of the rising edges reaches the number M of continuous pulses of the signal or the number of the falling edges reaches the number M of the continuous pulses minus 1, the counting trigger signal is output to the adjusting unit 20, so that the adjusting unit 20 can rapidly pull down the potential of the signal at the output end of the high-pass filter 30 to the common mode level instead of gradually recovering to the common mode level when receiving the counting trigger signal, and the duty ratio is not deviated when a later-stage detector demodulates the signal. Compared with the traditional scheme of adjusting the duty ratio of the signal at the output end of the high-pass filter 30 according to the pre-stored time constant to eliminate the deviation of the duty ratio caused by the time constant, the invention only needs to detect the number of the rising edges or the falling edges of the signal at the output end of the high-pass filter 30, does not need to acquire the time constant of the high-pass filter 30, can be suitable for the high-pass filters 30 with different time constants, has stronger compatibility, can not cause the problem of inaccurate duty ratio adjustment precision due to the difference of the pre-stored time constant and the actual time constant even if the time constants of the high-pass filters 30 of the same type are different, and has higher adjustment precision.
Referring to fig. 3 and 4, in an embodiment, the counting unit 10 includes a counter 11 and a one-out-of-multiple switch 12, where the counter 11 is configured to sequentially output a corresponding counting signal when each rising edge or falling edge of the output signal of the high-pass filter is detected; a plurality of input ends of the one-out-of-multiple switch 12 are respectively connected to a plurality of paths of counting signals, an output end of the one-out-of-multiple switch 12 is connected to the adjusting unit 20, and the one-out-of-multiple switch 12 is configured to select one of the plurality of paths of counting signals as the counting trigger signal to be output to the adjusting unit 20 according to a duty ratio adjusting requirement of a demodulation signal or according to the pulse number of continuous pulses of an output end signal of a high-pass filter. The counter 11 may be formed by a D flip-flop, and the one-out-of-multiple switch 12 may be implemented by a data selector or a switch tube.
In this embodiment, the one-out-of-multiple switch 12 may select one of the plurality of paths of the counting signal as the counting trigger signal to be output to the adjusting unit 20 according to the pulse number of the continuous pulses of the output signal of the high-pass filter. Referring to FIG. 4, for example, the rising edge count, the first to fourth stage D flip-flops D1 to D4 sequentially output the first to fourth count signals Q1 to Q4. The one-out-of-multiple switch 12 may gate the count signal Q2 to the adjusting unit 20 when the number of pulses of consecutive pulses of the output signal of the high pass filter is 2, and the one-out-of-multiple switch 12 may gate the count signal Q4 to the adjusting unit 20 when the number of pulses of consecutive pulses of the output signal of the high pass filter is 4. So that at the end of the successive pulses, a count trigger signal is immediately output to the adjustment unit to pull down the level of the output signal of the high-pass filter to the common mode level. That is, the communication module of the present embodiment can be applied to a plurality of modulated signals with different numbers of pulses in consecutive pulses.
Furthermore, the earlier the adjusting unit 20 receives the count trigger signal, the earlier the potential of the output signal of the high-pass filter is pulled down to the common mode level, and the duty ratio of the demodulated signal is smaller. Therefore, the one-out-of-multiple switch 12 in the present embodiment may also select a counting signal with a larger counting number as the counting trigger signal to be output to the adjusting unit 20 when the duty ratio of the demodulation signal is required to be larger. For example, referring to fig. 4, the duty ratio of the demodulated signal obtained when the third count signal Q3 is gated to the adjusting unit 20 is smaller than the duty ratio of the demodulated signal obtained when the fourth count signal Q4 is gated to the adjusting unit 20. Therefore, the one-out-of-multiple switch 12 of the present embodiment can also select the counting signals with different counting numbers to be output to the adjusting unit 20 according to the duty ratio requirement, so as to adjust the duty ratio of the demodulated signal, thereby achieving the purpose of adjusting the duty ratio of the demodulated signal.
Referring to fig. 4, in an embodiment, the counter 11 includes N sequentially cascaded D flip-flops, where N is greater than or equal to M.
An input end D of the first-stage D1 is connected with a first level signal Data, input ends D of the second-stage to Nth-stage D1 are connected with an output end of the previous-stage D trigger, and an output end Q of each-stage D trigger outputs one path of counting signal; reset terminals Reset of the D flip-flops of each stage are interconnected, an interconnection terminal serves as a Reset terminal of the counter 11 and also serves as a Reset terminal of the counting unit, clock terminals Clk of the D flip-flops of each stage are interconnected, and the interconnection terminal serves as a clock terminal of the counter 11 and is used for accessing an output terminal signal of the high-pass filter to serve as a clock signal of the counter.
Referring to fig. 4, N is equal to 4, the counter 11 is used to detect the number of falling edges of the output signal of the high pass filter, and the first level signal Data is a high level signal. The first-level to fourth-level D flip-flops D1-D4 are triggered by rising edges.
When the high-pass filter works, continuous pulses of signals at the output end of the high-pass filter are output to the inverter U1, the falling edges of the continuous pulses are inverted through the inverter U1 and changed into rising edges to be output to the clock end of the counter 11, and the first-stage D flip-flops to the fourth-stage D flip-flops are triggered to work. Specifically, when the first falling edge of the continuous pulse of the output signal of the high-pass filter comes, the first stage D flip-flop D1 is triggered and outputs the first count signal Q1, when the second falling edge of the continuous pulse comes, the second stage D flip-flop D2 is triggered and outputs the second count signal Q2, and so on, when the third and fourth falling edges of the continuous pulse come, the third stage D flip-flop D3 and the fourth stage D flip-flop D4 sequentially output the third count signal Q3 and the fourth count signal Q4. The output of multi-path counting signals Q1-Q4 is realized.
Referring to fig. 3, in an embodiment, the adjusting unit 20 includes a delay circuit 21, an and logic unit 22, and a switch unit 23. The delay circuit 21 is configured to delay the counting trigger signal when receiving the trigger signal, and sequentially output a first delay signal out1 and a second delay signal out2 with a phase opposite to that of the first delay signal out 1; the first input terminal of the and logic unit 22 is configured to be connected to the first delay signal out1, the second input terminal of the and logic unit 22 is configured to be connected to the second delay signal out2, the and logic unit 22 outputs an on control signal when receiving the first delay signal out1, and outputs an off control signal when receiving the first delay signal out1 and the second delay signal out 2; the first delay signal may be a high level signal, and the second delay signal may be a low level signal. The controlled end of the switch unit 23 is connected to the output end of the and logic unit 22, the output end of the switch unit 23 is connected to the output end of the high-pass filter 30, the switch unit 23 is turned on when receiving the on control signal to adjust the voltage of the output end signal of the high-pass filter to the common mode level, and is turned off when receiving the off control signal to stop adjusting the voltage of the output end signal of the high-pass filter to the common mode level. The switch unit 23 may include an MOS transistor, for example, the switch unit is an N-type MOS transistor, a gate of the N-type MOS transistor may receive an on control signal or an off control signal, a drain of the N-type MOS transistor is connected to the output end of the high-pass filter, and a source of the N-type MOS transistor is grounded.
Referring to fig. 4, the delay circuit 21 in this embodiment may include a first delay 211 and a second delay 212, wherein an input terminal of the first delay 211 is connected to the counting unit 10 to delay the counting trigger signal and output the first delayed signal out 1. The input terminal of the second delay 212 is connected to the output terminal of the first delay 211, and the second delay 212 is configured to delay and invert the first delayed signal out1 to output the second delayed signal out 2. The first delayer 211 can be formed by connecting an even number of inverters in series, and the second delayer 212 can be formed by connecting an odd number of inverters in series to be disposed on a chip. The delayer formed by connecting odd inverters in series has the functions of delaying time and inverting at the same time. Of course, other delay schemes may be used, and are not limited herein.
In this embodiment, before the count trigger signal is received, the second input terminal of the and logic unit is in a high impedance state. When the count trigger signal is received, the first delay unit 211 delays the count trigger signal, and then the first delay signal out1 reaches the first input terminal of the and logic unit 22, so that the and logic unit 22 outputs a high level, that is, the on control signal vout controls the switch unit 23 to be turned on, so as to pull down the potential of the output signal of the high pass filter to the common mode level. Meanwhile, the second delay unit 212 receives the first delay signal out1, delays it and outputs the second delay signal out2 to the second input terminal of the and logic unit 22, and since the second delay unit has an inverting function, the second delay signal out2 and the first delay signal out1 are in opposite phases, so that the and logic unit 22 outputs a low level, that is, the switch unit 23 is controlled to be turned off by turning off the control signal.
Therefore, the output time of the counting trigger signal is the rising edge time of the last pulse of the continuous pulse or the falling edge time of the last pulse, which has a certain time difference with the real end time of the continuous pulse signal, namely the falling edge of the last pulse. Therefore, in this embodiment, the delay time of the first delay 211 is set to be equal to the time difference, so that when the adjusting unit receives the counting trigger signal, the adjusting unit delays the time difference, and then pulls down the output signal of the high-pass filter, thereby eliminating the influence caused by the time difference.
Meanwhile, the pulse width of the on control signal vout output by the logic unit 22, that is, the on duration of the switch unit 23 is equal to the delay time of the second delay 212. The present embodiment can increase the on-duration of the switch unit 23 by selectively adjusting the delay time of the second delay 212, for example, 50ms, to obtain more pull-down time, so as to sufficiently pull down the output signal of the high pass filter to the common mode level, thereby ensuring the circuit stability.
In this embodiment, the setting of the first delayer and the second delayer may include the following three schemes: the first delay 211 is set as a controllable delay, and the delay time of the first delay 211 is adjusted according to the duty ratio requirement, so as to adjust the duty ratio of the demodulated signal.
Alternatively, the second delay 212 is set as a controllable delay, and the on time of the switching unit 23 is adjusted to adjust the duration of the low level (common mode level) of the output signal of the high-pass filter, so as to adjust the duty ratio of the demodulated signal. The counting unit 10 and the adjusting unit 20 of the present embodiment are both built by pure hardware circuits, so that the circuit has a smaller volume and is suitable for being integrated in a chip.
Or a combination of the two approaches.
Referring to fig. 3 and 4, the delay circuit 21 is further configured to output a third delay signal rstn to the reset terminal of the counting unit 10 when receiving the counting trigger signal, so as to reset the counting unit 10; the delay time of the third delay signal rstn is longer than the delay time of the second delay signal out2, that is, the third delay signal rstn occurs after the second delay signal out 2.
In some embodiments, the second delayed signal out2 may be used as a reset signal for the counting unit 10. When the second delay signal out2 appears, the switch unit is turned off, so that the counting unit 10 is reset after the switch unit is turned off, and at this time, the switch unit 23 has been turned on for a period of time (the delay time of the second delay unit) so that the turn-on control signal vout that the switch unit 23 is connected to has enough time to pull down the potential of the output signal of the high pass filter to the common mode level, thereby ensuring that the potential of the output signal of the high pass filter is completely pulled down to the common mode level. However, compared to the second delay signal out2, the embodiment further uses the third delay signal rstn with longer delay time to reset the counting unit 10, so that after all modules of the whole circuit are completely operated, the counting unit 10 is reset to ensure the stable operation of the whole circuit.
The third delay signal rstn can be obtained by directly and individually setting a delay unit with a delay time longer than the sum of the first delay unit 211 and the second delay unit 212, and delaying the counting trigger signal to output the third delay signal rstn with a delay time longer than the second delay signal out 2.
However, this embodiment may be alternatively configured to provide a third delay 213, wherein an input terminal of the third delay 213 is connected to an output terminal of the second delay 212, and an output terminal of the third delay 213 is used for delaying the second delay signal out2 and outputting the third delay signal rstn. Compared to directly setting a delay having a delay time greater than the sum of the first delay 211 and the second delay 212 alone. In this embodiment, the third delay unit 213 is connected to the output end of the second delay unit to delay the second delay signal out2, and a delay unit with a smaller delay time may be selected, so as to reduce the volume of the third delay unit 213.
The invention also provides a battery management system, which comprises the communication module; the specific structure of the communication module refers to the above embodiments, and since the battery management system adopts all technical solutions of all the above embodiments, at least all the beneficial effects brought by the technical solutions of the above embodiments are achieved, and no further description is given here.
The above description is only an alternative embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A communication module for use in a battery management system, the communication module comprising a high-pass filter, the number of pulses of consecutive pulses of an output signal of the high-pass filter being M, the communication module further comprising:
the counting unit is used for outputting corresponding counting trigger signals when detecting that the number of rising edges of signals at the output end of the high-pass filter reaches M or the number of falling edges reaches M minus 1;
the adjusting unit is respectively connected with the output end of the counting unit and the output end of the high-pass filter, and is used for adjusting the voltage of the output end signal of the high-pass filter to a common-mode level when receiving the counting trigger signal;
wherein M is greater than 1.
2. The communication module of claim 1, wherein the counting unit comprises:
the counter is used for sequentially outputting corresponding counting signals when each rising edge or each falling edge of the output end signal of the high-pass filter is detected;
the multi-selection switch is used for selecting one of the plurality of counting signals as the counting trigger signal to be output to the adjusting unit according to the duty ratio adjusting requirement of the demodulation signal corresponding to the output end signal of the high-pass filter or the number of continuous pulses of the output end signal of the high-pass filter.
3. The communication module of claim 2, wherein the counter comprises:
the input end of the first-stage D trigger is connected with a first level signal, the input ends of the second-stage to Nth-stage D triggers are connected with the output end of the previous-stage D trigger, and the output end of each-stage D trigger outputs one path of counting signal; the reset ends of the D triggers of each stage are interconnected, and the interconnected end is used as the reset end of the counter; the clock ends of the D flip-flops of each stage are interconnected, and the interconnection ends are used for accessing signals at the output end of the high-pass filter;
and the N is more than or equal to the M.
4. The communication module of claim 1, wherein the adjustment unit comprises:
the delay circuit is used for delaying the counting trigger signal when receiving the trigger signal and sequentially outputting a first delay signal and a second delay signal with the phase opposite to that of the first delay signal;
the AND logic unit is used for outputting an opening control signal when receiving the first delay signal and outputting a closing control signal when receiving the first delay signal and the second delay signal;
the controlled end of the switch unit is connected with the output end of the logic unit, the output end of the switch unit is connected with the output end of the high-pass filter, the switch unit is switched on when receiving the starting control signal so as to adjust the voltage of the output end signal of the high-pass filter to the common mode level, and the switch unit is switched off when receiving the closing control signal so as to stop adjusting the voltage of the output end signal of the high-pass filter to the common mode level.
5. The communication module of claim 4, wherein the delay circuit comprises:
the input end of the first delayer is connected with the counting unit, and the first delayer is used for delaying the counting trigger signal and outputting a first delayed signal;
and the input end of the second delayer is connected with the output end of the first delayer, and the second delayer is used for delaying and inverting the first delay signal so as to output the second delay signal.
6. The communication module of claim 5, wherein the second delay comprises an odd number of inverters serially connected in series.
7. The communication module of claim 5, wherein the delay circuit is further configured to output a third delay signal to the reset terminal of the counting unit to reset the counting unit when receiving the counting trigger signal; wherein the delay time of the third delay signal is greater than the delay time of the second delay signal.
8. The communication module of claim 7, wherein the delay circuit comprises:
and the input end of the third delayer is connected with the output end of the second delayer, and the output end of the third delayer is used for delaying the second delay signal so as to output the third delay signal.
9. The communication module of claim 4, wherein the switching unit comprises a MOS transistor.
10. A battery management system, characterized in that it comprises a communication module according to any one of claims 1-9.
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