CN114512539B - Novel Si-SiC heterojunction tunneling MOSFET device and integrated device thereof - Google Patents
Novel Si-SiC heterojunction tunneling MOSFET device and integrated device thereof Download PDFInfo
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- 230000005641 tunneling Effects 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 126
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 118
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 85
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 49
- 239000010703 silicon Substances 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims description 11
- 230000000694 effects Effects 0.000 abstract description 10
- 238000002955 isolation Methods 0.000 abstract description 6
- 230000009291 secondary effect Effects 0.000 abstract description 5
- 230000007704 transition Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 238000005036 potential barrier Methods 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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Abstract
The invention belongs to the technical field of semiconductor devices, and provides a novel Si-SiC heterojunction tunneling MOSFET device and an integrated device thereof, which are used for overcoming the secondary effect of a traditional silicon-based MOSFET. The invention adopts an Si-SiC heterojunction structure formed between an N-type silicon semiconductor region and a P-type silicon carbide semiconductor region or between the N-type silicon carbide semiconductor region and the P-type silicon semiconductor region, and the effective channel of the device is the junction surface of the Si-SiC heterojunction, namely, the effective channel length is infinitely short, so that the channel length modulation effect is not existed, the secondary effect is effectively eliminated, and the problem of low electron mobility in transition of an inversion layer in SiC is further solved; meanwhile, the device structure can realize the isolation of NMOS and PMOS on the same substrate, further realize the structure of an inverter and the like, and has wide application prospect in the fields of SiC integrated circuits and SiC power integrated circuits.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, relates to a tunneling field effect transistor semiconductor device, and particularly relates to a novel Si (silicon) -SiC (silicon carbide) heterojunction tunneling MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device and an integrated circuit technology.
Background
The silicon carbide semiconductor material is used as a wide forbidden band semiconductor material, and has the advantages of large forbidden band width, high breakdown field strength, high carrier saturation drift speed, small dielectric constant and the like; the performance of the power device and the power integrated circuit prepared from the silicon carbide material is higher than that of the power device prepared from the common silicon material, so that the silicon carbide material has wider application prospect.
On the other hand, as the channel length of MOSFETs is continuously shortened, many negligible effects become significant, collectively referred to as short channel effects; when the channel length of the MOSFET is shortened to be comparable to the junction depths of the source and drain regions, the threshold voltage will decrease as the channel length L is shortened, which is a short channel effect of the threshold voltage. When the channel length is reduced, a drain induced barrier lowering effect (DIBL) occurs, and punch-through occurs, so that a large leakage current is generated between the source and the drain.
In order to overcome the problems of low electron mobility of an inversion layer in SiC, the invention provides an integrated circuit technology and a new implementation way for the SiC integrated circuit and power integrated circuit technology.
Disclosure of Invention
The invention aims to provide a novel Si (silicon) -SiC (silicon carbide) heterojunction tunneling MOSFET device which is used for overcoming the secondary effect of a traditional silicon-based MOSFET; compared with the traditional MOSFET, the grid electrode in the device structure can be infinitely short, and a zero channel length structure is realized, namely, the channel length modulation effect is not generated, so that the channel mobility is not limited by the channel length, and the limitation of the channel mobility on the on-resistance is eliminated; meanwhile, the SiC material has good heat conductivity and high-temperature characteristics, so that a choice is provided for the high-temperature integrated circuit technology.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
a novel Si-SiC heterojunction tunneling MOSFET device comprising: a SiC substrate, an NMOS on the SiC substrate; characterized in that the NMOS comprises: the N-type silicon carbide semiconductor region is provided with a heavily doped N-type semiconductor region, a metalized drain electrode is arranged on the heavily doped N-type semiconductor region, a heavily doped P-type semiconductor region is arranged in the P-type silicon semiconductor region, a metalized source electrode is arranged on the heavily doped P-type semiconductor region, and a metal grid is bridged at the abutting position of the N-type silicon carbide semiconductor region and the P-type silicon semiconductor region.
A novel Si-SiC heterojunction tunneling MOSFET device comprising: a SiC substrate, a PMOS located on the SiC substrate; wherein the PMOS comprises: the N-type silicon carbide semiconductor region is provided with a heavily doped N-type semiconductor region, a metalized source electrode is arranged on the heavily doped N-type semiconductor region, the P-type silicon carbide semiconductor region is provided with a heavily doped P-type semiconductor region, a metalized drain electrode is arranged on the heavily doped P-type semiconductor region, and a metal grid electrode is bridged at the abutting position of the N-type silicon semiconductor region and the P-type silicon carbide semiconductor region.
Further, in the two devices, the metal gate is a surface gate structure or a trench gate structure.
A novel Si-SiC heterojunction tunneling MOSFET device comprising: the semiconductor device comprises an N-type silicon carbide semiconductor region, a heavily doped N-type semiconductor region arranged below the N-type silicon carbide semiconductor region, a metalized drain arranged below the heavily doped N-type semiconductor region, a P-type silicon semiconductor region arranged on the N-type silicon carbide semiconductor region, a heavily doped P-type semiconductor region arranged on the P-type silicon semiconductor region, a metalized source arranged on the heavily doped P-type semiconductor region and a trench type metal gate penetrating into the P-type silicon semiconductor region and the N-type silicon carbide semiconductor region.
An NMOS and PMOS based inverter comprising: a SiC substrate, and PMOS and NMOS adjacently arranged on the SiC substrate; the PMOS is connected with the drain electrode of the NMOS as the output end of the inverter, the NMOS is connected with the grid electrode of the PMOS as the input end of the inverter, the source electrode of the NMOS is grounded, and the source electrode of the PMOS is connected with the power supply voltage.
An NMOS and PMOS based inverter comprising: the semiconductor device comprises a silicon substrate, an insulating layer substrate arranged on the silicon substrate, and a PMOS and an NMOS which are separated and arranged in the insulating layer substrate; the NMOS is connected with the drain electrode of the PMOS and is used as the output end of the inverter, the NMOS is connected with the grid electrode of the PMOS and is used as the input end of the inverter, the source electrode of the NMOS is grounded, and the source electrode of the PMOS is connected with the power supply voltage.
The invention has the beneficial effects that:
the invention provides a novel Si-SiC heterojunction tunneling MOSFET device, which adopts an N-type silicon semiconductor region and a P-type silicon carbide semiconductor region or a Si-SiC heterojunction structure formed between the N-type silicon carbide semiconductor region and the P-type silicon semiconductor region; meanwhile, the device structure can realize the isolation of NMOS and PMOS on the same substrate, further realize the structure of an inverter and the like, and has wide application prospect in the fields of SiC integrated circuits and SiC power integrated circuits.
Drawings
Fig. 1 is a schematic cross-sectional structure of a Si-SiC heterojunction tunneling NMOSFET device according to embodiment 1 of the present invention.
Fig. 2 is a schematic cross-sectional structure of a Si-SiC heterojunction tunneling PMOSFET device according to embodiment 2 of the present invention.
Fig. 3 is a schematic cross-sectional structure of an integrated device for implementing NMOS and PMOS on the same substrate according to embodiment 2 of the present invention.
Fig. 4 is a schematic cross-sectional structure of an integrated device for implementing NMOS and PMOS on the same substrate according to embodiment 2 of the present invention.
Fig. 5 is a schematic cross-sectional structure of an NMOS and PMOS based inverter according to embodiment 3 of the present invention.
Fig. 6 is a schematic cross-sectional structure of an NMOS and PMOS based inverter according to embodiment 4 of the present invention.
Fig. 7 is a schematic cross-sectional structure of a Si-SiC heterojunction tunneling MOSFET device according to embodiment 5 of the present invention.
Fig. 8 is a schematic cross-sectional structure of a Si-SiC heterojunction tunneling MOSFET device according to embodiment 6 of the present invention.
FIG. 9 is a graph of threshold voltage of a Si-SiC heterojunction tunneling MOSFET device in accordance with an embodiment of the present invention; wherein, (1) is an N-type MOSFET, and (2) is a P-type MOSFET.
Fig. 10 is a graph of output characteristics of a Si-SiC heterojunction tunneling MOSFET device in accordance with an embodiment of the present invention.
Fig. 11 is a band diagram of a Si-SiC heterojunction tunneling MOSFET device in an embodiment of the invention.
Fig. 12 is a schematic circuit diagram of an NMOS and PMOS based inverter in an embodiment of the invention.
FIG. 13 is a voltage input/output curve of an NMOS and PMOS based inverter according to an embodiment of the present invention.
Detailed Description
The invention will be described in further detail with reference to the drawings and examples.
Example 1
The embodiment provides a novel Si-SiC heterojunction tunneling MOSFET device, the structure of which is shown in figure 1, comprising: an unintentionally doped or undoped SiC substrate 1, a semiconductor layer (NMOS) located on the semiconductor substrate; the semiconductor layer includes: the N-type silicon carbide semiconductor region 2-1 and the P-type silicon semiconductor region 3-1 which are adjacent to each other, wherein a heavily doped N-type semiconductor region 4 is arranged in the N-type silicon carbide semiconductor region 2-1, a metalized drain (D) 6 is arranged on the heavily doped N-type semiconductor region 4, a heavily doped P-type semiconductor region 5 is arranged in the P-type silicon semiconductor region 3-1, a metalized source (S) 8 is arranged on the heavily doped P-type semiconductor region 5, and a metalized gate 7 is arranged on an N-type polysilicon gate 9,N type polysilicon gate 9 which is arranged on the N-type silicon carbide semiconductor region 2-1 and the P-type silicon semiconductor region 3-1 in a bridging manner; the N-type silicon carbide semiconductor region 2-1 and the P-type silicon semiconductor region 3-1 form Si-SiC heterojunction at the adjacent position, and the surface gate (formed by the N-type polysilicon gate 9 and the metalized gate 7) is arranged corresponding to the Si-SiC heterojunction.
The working principle of this embodiment is as follows:
in the novel Si-SiC heterojunction tunneling MOSFET device, N-type silicon carbide and P-type silicon semiconductors are used, and as the majority carriers are electrons on one side of the N-type silicon carbide semiconductor region 2-1, the threshold voltage is positive as can be seen from FIG. 9 (1), so that the heterojunction tunneling N-MOSFET device is formed; the electrode connection mode during conduction is as follows: the metalized drain (D) 6 is connected with high potential, the metalized source (S) 8 is connected with low potential, and the metalized gate (G) 7 is connected with high potential. Since the energy bands of silicon carbide are different from those of silicon, it can be seen from the energy band diagram of fig. 11 (1) that when the metalized drain (D) 6 is connected to a high potential, the conduction band on the side of the N-type silicon carbide semiconductor region 2-1 is located below the conduction band of the P-type silicon semiconductor region 3-1, forming a potential barrier for electrons, which cannot cross the potential barrier, and thus cannot form a current; as is clear from fig. 11 (2), when the metalized gate (G) 7 is connected to a high potential, the energy bands of the N-type silicon carbide semiconductor region 2-1 and the P-type silicon semiconductor region 3-1 are changed, so that the conduction band on the side of the N-type silicon carbide semiconductor region 2-1 and the valence band on the side of the P-type silicon semiconductor region 3-1 overlap, and when the gate voltage is high to a certain extent, the band-band tunneling effect occurs for electrons, that is, electrons in the conduction band on the side of the N-type silicon carbide region 2-1 tunnel into the valence band on the side of the P-type silicon region 3-1 to become holes, and since the majority carriers in the P-type silicon region 3-1 are holes, the holes are extracted by the metalized source (S) 8, so as to form a continuous current.
The effective channel in the device structure is a junction surface of the Si-SiC heterojunction, and is different from the channel of the traditional MOSFET structure which is an inversion layer channel under a grid electrode, namely the effective channel length of the device structure is infinitely short, the zero channel length structure is realized, the channel length modulation effect is not existed, the secondary effect is effectively eliminated, and the problem of low electron mobility in the inversion layer in SiC is further solved. As shown in fig. 10, the output characteristic curves of the device structure of the present invention are shown, and the current of the device can be gradually saturated with the rise of the drain voltage when the gate voltage is 15V and 20V at the temperatures of 300K and 400K.
Example 2
The embodiment provides a novel Si-SiC heterojunction tunneling MOSFET device, the structure of which is shown in figure 1, comprising: an unintentionally doped or undoped SiC substrate 1, a semiconductor layer (PMOS) located on the semiconductor substrate; the semiconductor layer includes: the N-type silicon carbide semiconductor region 2-2 and the P-type silicon carbide semiconductor region 3-2 which are adjacent to each other, wherein a heavily doped N-type semiconductor region 4 is arranged in the N-type silicon semiconductor region 2-2, a metalized source electrode (S) 6 is arranged on the heavily doped N-type semiconductor region 4, a heavily doped P-type semiconductor region 5 is arranged in the P-type silicon carbide semiconductor region 3-2, a metalized drain electrode (D) 8 is arranged on the heavily doped P-type semiconductor region 5, and a metalized gate electrode 7 is arranged on an N-type polysilicon gate 9,N type polysilicon gate 9 which is arranged on the N-type silicon semiconductor region 2-2 and the P-type silicon carbide semiconductor region 3-2 in a bridging manner; the N-type silicon semiconductor region 2-2 and the P-type silicon carbide semiconductor region 3-2 form Si-SiC heterojunction at the adjacent position, and the surface gate (formed by the N-type polysilicon gate 9 and the metalized gate 7) is arranged corresponding to the Si-SiC heterojunction.
The working principle of this embodiment is as follows:
the novel Si-SiC heterojunction tunneling MOSFET device uses N-type silicon and P-type silicon carbide semiconductors, and the threshold voltage is negative as can be seen from FIG. 9 (2), so that the heterojunction tunneling P-MOSFET device is formed; the electrode connection mode during conduction is as follows: the metalized drain (D) 8 is connected to a low potential, the metalized source (S) 6 is connected to a high potential, and the metalized gate (G) 7 is connected to a low potential relative to the metalized drain (D). Because the energy band of silicon carbide is different from that of silicon, when the metallized source electrode (S) 6 is connected with high potential, the conduction on one side of the P-type silicon carbide semiconductor region 3-2 is positioned above the conduction band of the N-type silicon semiconductor region 2-2, so that a potential barrier for electrons is formed, the electrons cannot cross the potential barrier, and therefore, current cannot be formed; when the metalized gate (G) 7 is connected to a low potential relative to the metalized drain (D), the energy bands of the P-type silicon carbide semiconductor region 3-2 and the N-type silicon semiconductor region 2-2 are changed, so that the conduction band on the P-type silicon carbide semiconductor region 3-2 side and the valence band on the N-type silicon semiconductor region 2-2 side overlap, and when the gate voltage is low to a certain extent, a band-band tunneling effect occurs for electrons, that is, electrons in the conduction band on the N-type silicon region 2-2 side tunnel into the valence band on the P-type silicon carbide region 3-2 side to become holes, and since the majority carriers in the P-type silicon carbide region 3-2 are holes, the holes are extracted by the metalized drain (D) 8 to form a continuous current.
The effective channel in the device structure is a junction surface of the Si-SiC heterojunction, and is different from the channel of the traditional MOSFET structure which is an inversion layer channel under a grid electrode, namely the effective channel length of the device structure is infinitely short, the zero channel length structure is realized, the channel length modulation effect is not existed, the secondary effect is effectively eliminated, and the problem of low electron mobility in the inversion layer in SiC is further solved.
In addition, because the undoped SiC substrate and the silicon material naturally have an electronic barrier, the isolation of NMOS and PMOS can be realized on the same substrate, as shown in figure 3; the structure does not need to use the well process in the CMOS process, namely, the PMOS is realized in the N well and the NMOS is realized in the P well respectively, thus due to the natureThe process is simpler to implement. Further, to enhance isolation between devices, an insulating layer is filled between the devices, the insulating layer material is typically SiO 2 As shown in fig. 4, the structure does not need to use a well process in a CMOS process, that is, NMOS is implemented in PMOS and P wells respectively in an N well, so that the process implementation is simpler due to natural isolation.
Example 3
The present embodiment provides an inverter structure composed of NMOS and PMOS, as shown in fig. 5, including: an unintentionally doped or undoped SiC substrate, and PMOS and NMOS disposed adjacent to each other on the SiC substrate; the NMOS and the PMOS are Si-SiC heterojunction tunneling MOSFET devices in the embodiment 1 and the embodiment 2 respectively, the NMOS and the PMOS share an unintentionally doped or undoped SiC substrate, the NMOS is connected with the drain electrode of the PMOS and is used as the output end of the inverter, the NMOS is connected with the grid electrode of the PMOS and is used as the input end of the inverter, the source electrode of the NMOS is grounded, and the source electrode of the PMOS is connected with the power supply voltage.
The working principle of this embodiment is as follows:
the principle of the inverter is shown in FIG. 12, in which the metalized drains (D) of the PMOS and NMOS are connected together, and the metalized drains (D) are simultaneously contacted with the heavily doped N-type semiconductor region 4 in the heavily doped N-type silicon carbide semiconductor region of the NMOS and the heavily doped P-type semiconductor region in the P-type silicon carbide semiconductor region of the PMOS, the metalized source (S) of the NMOS is connected to the low potential, i.e. the Ground (GND), and the metalized source (S) of the PMOS is connected to the high potential, i.e. the V DD The method comprises the steps of carrying out a first treatment on the surface of the The metalized gates (G) of NMOS and PMOS are simultaneously connected together as inputs. When the input terminal is high voltage and the voltage value is larger than the threshold voltage value of the NMOS, the NMOS tube at the lower part in FIG. 12 is conducted, and the output is low level, namely the output is Grounded (GND); when the input terminal is negative voltage and the absolute value of the voltage is larger than the absolute value of the threshold voltage of the PMOS, the PMOS tube at the upper part in FIG. 12 is turned on and outputs high level, i.e. the output is connected with V DD The inverter functions as an inverter, i.e., outputs a low level when the input is a high level, outputs a high level when the input is a low level, and the input-output curves are shown in fig. 13.
Example 4
The present embodiment provides an inverter structure composed of NMOS and PMOS, as shown in fig. 6, including: a silicon substrate 10, an insulating layer substrate 11 provided on the silicon substrate, and separate PMOS and NMOS provided in the insulating layer substrate 11; the NMOS and the PMOS are Si-SiC heterojunction tunneling MOSFET devices in the embodiment 1 and the embodiment 2 respectively, the NMOS and the PMOS share the silicon substrate 10 and the insulating layer substrate 11, the NMOS is connected with the drain electrode of the PMOS and used as the output end of the inverter, the NMOS is connected with the grid electrode of the PMOS and used as the input end of the inverter, the source electrode of the NMOS is grounded, and the source electrode of the PMOS is connected with the power supply voltage.
The working principle of the embodiment is similar to that of embodiment 3, but the embodiment can realize better isolation between devices and reduce parasitic effects.
Example 5
The present embodiment provides a novel Si-SiC heterojunction tunneling MOSFET device, whose structure is shown in fig. 7, and the only difference from embodiment 1 is that: the groove gate is adopted to replace the plane gate, and is bridged in the N-type silicon carbide semiconductor region 2-1 and the P-type silicon semiconductor region 3-1; the operation principle of this embodiment is the same as that of embodiment 1, and since the trench type metalized gate (G) 7 goes deep into the N type silicon carbide semiconductor region 2-1, there is a larger contact area, and when the trench type metalized gate (G) 7 is connected to a high potential, a larger on-current can be realized due to the larger contact area.
Similarly, the si—sic heterojunction tunneling MOSFET device of example 2 can also employ a trench gate.
Example 6
The embodiment provides a novel Si-SiC heterojunction tunneling MOSFET device, which adopts a longitudinal structure, as shown in fig. 8, and includes: the semiconductor device comprises an N-type silicon carbide semiconductor region 2-1, a heavily doped N-type semiconductor region 4 arranged below the N-type silicon carbide semiconductor region 2-1, a metalized drain (D) 6 arranged below the heavily doped N-type semiconductor region 4, a P-type silicon semiconductor region 3-1 arranged on the N-type silicon carbide semiconductor region 2-1, a heavily doped P-type semiconductor region 5 arranged on the P-type silicon semiconductor region 3-1, a metalized source (S) 8 arranged on the heavily doped P-type semiconductor region 5, and a grooved metal gate penetrating into the P-type silicon semiconductor region 3-1 and the N-type silicon carbide semiconductor region 2-1, wherein the grooved metal gate consists of an N-type polysilicon gate 9 positioned on a groove wall and a metalized gate (G) 7 filled in the groove.
The working principle of this embodiment is as follows:
the novel Si-SiC heterojunction tunneling MOSFET device is of a longitudinal structure, has the same working principle as that of the transverse structure in the embodiment 1, and the groove-type metal grid extends into the P-type silicon semiconductor region 3-1 and the N-type silicon carbide semiconductor region 2-1, and the metalized source electrode (S) 5 and the metalized source electrode (D) 6 are respectively positioned on two sides of the chip, so that the area occupied by the device can be greatly reduced by the structure similar to that of a VDMOS.
While the invention has been described in terms of specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the equivalent or similar purpose, unless expressly stated otherwise; all of the features disclosed, or all of the steps in a method or process, except for mutually exclusive features and/or steps, may be combined in any manner.
Claims (4)
1. A novel Si-SiC heterojunction tunneling MOSFET device comprising: a SiC substrate, an NMOS on the SiC substrate; characterized in that the NMOS comprises: the N-type silicon carbide semiconductor region is provided with a heavily doped N-type semiconductor region, a metalized drain electrode is arranged on the heavily doped N-type semiconductor region, a heavily doped P-type semiconductor region is arranged in the P-type silicon semiconductor region, a metalized source electrode is arranged on the heavily doped P-type semiconductor region, and a metal grid is bridged at the adjacent position of the N-type silicon carbide semiconductor region and the P-type silicon semiconductor region; the metal gate is of a surface gate structure or a groove-shaped gate structure.
2. A novel Si-SiC heterojunction tunneling MOSFET device comprising: a SiC substrate, a PMOS located on the SiC substrate; wherein the PMOS comprises: the N-type silicon carbide semiconductor region is provided with a heavily doped N-type semiconductor region, a metalized source electrode is arranged on the heavily doped N-type semiconductor region, the P-type silicon carbide semiconductor region is provided with a heavily doped P-type semiconductor region, a metalized drain electrode is arranged on the heavily doped P-type semiconductor region, and a metal grid is bridged at the adjacent position of the N-type silicon semiconductor region and the P-type silicon carbide semiconductor region; the metal gate is of a surface gate structure or a groove-shaped gate structure.
3. An NMOS and PMOS based inverter comprising: a SiC substrate, and PMOS and NMOS adjacently arranged on the SiC substrate; wherein the PMOS is the PMOS of claim 2 and the NMOS is the NMOS of claim 1; the PMOS is connected with the drain electrode of the NMOS as the output end of the inverter, the NMOS is connected with the grid electrode of the PMOS as the input end of the inverter, the source electrode of the NMOS is grounded, and the source electrode of the PMOS is connected with the power supply voltage.
4. An NMOS and PMOS based inverter comprising: the semiconductor device comprises a silicon substrate, an insulating layer substrate arranged on the silicon substrate, and a PMOS and an NMOS which are separated and arranged in the insulating layer substrate; the PMOS is the PMOS of claim 2 and the NMOS is the NMOS of claim 1; the NMOS is connected with the drain electrode of the PMOS and is used as the output end of the inverter, the NMOS is connected with the grid electrode of the PMOS and is used as the input end of the inverter, the source electrode of the NMOS is grounded, and the source electrode of the PMOS is connected with the power supply voltage.
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| US8048765B2 (en) * | 2009-08-28 | 2011-11-01 | Broadcom Corporation | Method for fabricating a MOS transistor with source/well heterojunction and related structure |
| US10147813B2 (en) * | 2016-03-04 | 2018-12-04 | United Silicon Carbide, Inc. | Tunneling field effect transistor |
| US11139394B2 (en) * | 2019-08-30 | 2021-10-05 | Semiconductor Components Industries, Llc | Silicon carbide field-effect transistors |
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| EP1835543A1 (en) * | 2006-03-14 | 2007-09-19 | Nissan Motor Co., Ltd. | Method for manufacturing semiconductor device |
| CN106876458A (en) * | 2017-01-11 | 2017-06-20 | 西安电子科技大学 | A kind of groove grid enhanced AlGaN/GaN HFETs |
| CN107994071A (en) * | 2017-12-11 | 2018-05-04 | 电子科技大学 | A kind of hetero-junctions channel insulation grid-type field-effect tube |
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