CN114512537A - Manufacturing method of insulated gate bipolar transistor IGBT - Google Patents

Manufacturing method of insulated gate bipolar transistor IGBT Download PDF

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Publication number
CN114512537A
CN114512537A CN202210411916.0A CN202210411916A CN114512537A CN 114512537 A CN114512537 A CN 114512537A CN 202210411916 A CN202210411916 A CN 202210411916A CN 114512537 A CN114512537 A CN 114512537A
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China
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igbt
manufacturing
film
contact hole
bipolar transistor
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赵东艳
王于波
陈燕宁
付振
张泉
尹强
肖超
田俊
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Beijing Smartchip Microelectronics Technology Co Ltd
Beijing Core Kejian Technology Co Ltd
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Beijing Smartchip Microelectronics Technology Co Ltd
Beijing Core Kejian Technology Co Ltd
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Priority to CN202210411916.0A priority Critical patent/CN114512537A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET

Abstract

The embodiment of the invention provides a manufacturing method of an Insulated Gate Bipolar Transistor (IGBT), belonging to the technical field of chips. The manufacturing method of the insulated gate bipolar transistor IGBT comprises the following steps: forming a basic structure of the IGBT on the front surface of a first material substrate; depositing a second material film on the surface of the base structure; depositing an interlayer dielectric layer film on the surface of the second material film to form a structure to be etched; and etching the contact hole of the structure to be etched by a contact hole etching process and by preselected gas with high selectivity ratio to the third material and the second material and preselected gas with high selectivity ratio to the second material and the first material to form a contact hole groove. The embodiment of the invention can improve the etching depth uniformity of the contact holes in each region in the single crystal wafer and ensure that the IGBT device is more stable in latch-up resistance.

Description

Manufacturing method of insulated gate bipolar transistor IGBT
Technical Field
The invention relates to the technical field of chips, in particular to a manufacturing method of an Insulated Gate Bipolar Transistor (IGBT).
Background
An Insulated Gate Bipolar Transistor (IGBT) chip is a composite fully-controlled voltage-driven power semiconductor device composed of a Bipolar Transistor BJT and an Insulated Gate field effect Transistor MOS, and has the advantages of both high input impedance of a MOSFET and low on-state voltage drop of a power Transistor GTR. The GTR saturation voltage is reduced, the current carrying density is high, but the driving current is large; the MOSFET has small driving power, high switching speed, large conduction voltage drop and small current carrying density. The IGBT integrates the advantages of the two devices, and has small driving power and reduced saturation voltage. The method is very suitable for being applied to the fields of current transformation systems with direct-current voltage of 600V or more, such as alternating-current motors, frequency converters, switching power supplies, lighting circuits, traction transmission and the like.
The dynamic latch failure is a common failure phenomenon of the IGBT chip, and causes the failure because the current of the IGBT chip is reduced faster in the turn-off process, the voltage is reduced faster, and larger hole displacement current is caused at the same time, the voltage drop generated by the resistance of the P-type base region is larger than 0.7V, so that a parasitic NPN transistor in the IGBT chip is conducted, the grid is out of control failure, the current of a collector is continuously increased, and the chip is overheated and fails. The difference of the anti-latching capability among IGBT chips is large, and the performance stability of the product is influenced.
In order to improve the stable latch-up resistance of the IGBT chip, a common optimization process is to increase the resistance of the P-type base region by increasing the depth of Contact Etch (Contact Etch) to increase the turn-on voltage, so as to suppress parasitic NPN turn-on. However, the method is difficult to ensure the depth uniformity of the contact holes at each position in the single crystal wafer, and the performance of the device is affected or the device fails due to the too deep contact holes.
Disclosure of Invention
The embodiment of the invention aims to provide a manufacturing method of an Insulated Gate Bipolar Transistor (IGBT), which is used for solving the problem that the depth of a contact hole groove in a single chip is difficult to control to be uniform in the contact hole etching process.
In order to achieve the above object, an embodiment of the present invention provides a method for manufacturing an insulated gate bipolar transistor IGBT, including: forming a basic structure of the IGBT on the front surface of a first material substrate; depositing a second material film on the surface of the base structure; depositing an interlayer dielectric layer film on the surface of the second material film to form a structure to be etched; and etching the contact hole of the structure to be etched by a contact hole etching process and by preselected gas with high selectivity ratio to the third material and the second material and preselected gas with high selectivity ratio to the second material and the first material to form a contact hole groove.
Optionally, the first material is Si, the first material substrate is a Si single wafer, the second material is silicon nitride SIN, the second material film is a SIN film, and the third material is SiO2。
Optionally, the Si single crystal wafer is an N-type single crystal wafer.
Optionally, the basic structure of the IGBT is a trench MOS structure, and the forming the basic structure of the IGBT on the front surface of the first type material single crystal wafer includes: etching a deep groove on the front surface of the first material single wafer, and thermally growing a gate oxide layer; depositing a Poly-Si layer, a P type body region and an N type heavily doped region on the gate oxide layer; and forming the basic structure of the IGBT by IMP implantation and annealing.
Optionally, before depositing the second material film on the surface of the base structure, the method for manufacturing the insulated gate bipolar transistor IGBT further includes: cleaning the surface of the base structure.
Optionally, the thickness parameter of the second material film is 200-300A.
Optionally, the depositing an interlayer dielectric layer film on the surface of the second material film includes: and sequentially depositing undoped silicon glass USG and phosphorosilicate glass BPSG with preset thicknesses on the surface of the second material film through chemical vapor deposition CVD to serve as the interlayer dielectric layer film, and flattening the surface of the interlayer dielectric layer film through a high-temperature reflux process.
Optionally, the thickness parameter of the doped silicate glass USG is 3000A, and the thickness parameter of the phosphosilicate glass BPSG is 9000A.
Optionally, after depositing an interlayer dielectric layer film on the surface of the second material film to form a structure to be etched, the manufacturing method of the insulated gate bipolar transistor IGBT further includes: and moving the photomask graph of the contact hole to the surface of the interlayer dielectric layer film through photoresist coating and developing processes.
Optionally, the forming a contact hole trench by performing contact hole etching on the structure to be etched through a contact hole etching process and a preselected gas having a high selectivity ratio for the third material and the second material and a preselected gas having a high selectivity ratio for the second material and the first material includes: generating plasma through the preselected gas with high selection ratio to the third material and the second material, attacking the surface of the interlayer dielectric layer film, and stopping the attack on the surface of the second material film after a preset first control time; etching the second material film by the preselected gas with high selectivity ratio to the second material and the first material, and stopping the etching on the surface of the basic structure after a preset second control time; and etching the basic structure by using a preselected first material etching gas, and forming the contact hole groove after a preset third control time.
Optionally, the manufacturing method of the insulated gate bipolar transistor IGBT further includes: forming a metal barrier layer on the surface of the contact hole groove by a Physical Vapor Deposition (PVD) process; and filling metal materials in the contact hole groove by Chemical Vapor Deposition (CVD).
Optionally, the metal barrier layer is made of Ti or TiN, and the filled metal material is tungsten.
Optionally, the manufacturing method of the insulated gate bipolar transistor IGBT further includes: and manufacturing the front electrode by Physical Vapor Deposition (PVD) and a photoetching process.
Optionally, the front electrode is made of Al-Cu alloy.
Optionally, the manufacturing method of the insulated gate bipolar transistor IGBT further includes: and thinning the back of the first material substrate by adopting a taiko thinning process and a chemical corrosion mode.
Optionally, the manufacturing method of the insulated gate bipolar transistor IGBT further includes: taking a first preselected acceptor element as an ion implantation source, and performing ion implantation on the back surface of the first material substrate according to a first preselected implantation dose and a first implantation energy; and annealing through a laser annealing process to form the buffer layer.
Optionally, the first acceptor element is phosphorus, the first implantation dose is 5e12, and the first implantation energy is 2 Mev.
Optionally, the manufacturing method of the insulated gate bipolar transistor IGBT further includes: taking a second preselected acceptor element as an ion implantation source, and performing ion implantation on the back surface of the first material substrate according to a second preselected implantation dose and second implantation energy; and annealing through a laser annealing process to form the P-collector layer.
Optionally, the second acceptor element is boron, the second implantation dose is 5e12, and the second implantation energy is 20 ev.
Optionally, the manufacturing method of the insulated gate bipolar transistor IGBT further includes: and manufacturing a back electrode on the back of the first material substrate by a Physical Vapor Deposition (PVD) process.
Optionally, the back electrode is a 4-layer metal electrode, and the material of the back electrode is Al, Ti, Ni, and Ag in sequence.
Through the technical scheme, the second material film is deposited before the process of manufacturing the interlayer dielectric layer film to be used as a stop layer for etching the contact hole, so that the depth of the contact hole at each position of a single chip is uniform; and the contact hole etching is carried out through preselected gas with high selection ratio to the third material and the second material and preselected gas with high selection ratio to the second material and the first material, so that the etching depth uniformity of the contact hole in each area in the single crystal wafer is improved, and the IGBT device is more stable in latch-up resistance.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIG. 1a is a schematic structural diagram of a conventional IGBT chip;
FIG. 1b is an equivalent circuit diagram of FIG. 1 a;
FIGS. 2a-2e are schematic structural diagrams of a conventional manufacturing process of a contact hole etching part;
fig. 3 is a schematic flow chart of a manufacturing method of an insulated gate bipolar transistor IGBT according to an embodiment of the present invention;
FIG. 4a is a schematic structural section of a Trench FS-IGBT;
FIG. 4b is a schematic illustration of single wafer surface silicon carbide deposition;
FIG. 4c is a schematic view of an interlevel dielectric layer deposition structure;
FIG. 4d is a schematic diagram of a structure for photolithographic development of a contact hole;
FIG. 4e is a schematic diagram of etching the SIN film structure during contact hole etching;
FIG. 4f is a schematic structural diagram after etching the SIN film in the contact hole etching;
FIG. 4g is a schematic diagram of the structure after the etching of the contact hole is completed.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
Before describing the embodiments of the present invention in detail, a brief introduction will be made to the design ideas of the prior art and the embodiments of the present invention.
FIG. 1a is a schematic structural diagram of a conventional IGBT chip; fig. 1b is an equivalent circuit diagram of fig. 1 a. Referring to fig. 1a and fig. 1b, the dynamic latch-up failure is a common failure phenomenon of an Insulated Gate Bipolar Transistor (IGBT) chip, and causes the failure because the current drops faster (di/dt) in the turn-off process of the IGBT chip, which causes the voltage (dv/dt) to drop faster and causes a larger hole displacement current IpbodyP-type base resistance RpbodyThe generated voltage drop is larger than 0.7V, so that a parasitic NPN transistor in the IGBT chip is conducted, the control failure of a grid electrode is lost, the current of a collector electrode is continuously increased, and the chip is overheated and fails.
In order to improve the stable latch-up resistance of the IGBT chip, an existing optimization process is to increase the P-type base region resistance R by increasing the depth of Contact Etch (Contact Etch)pbodyThereby increasing the turn-on voltage to inhibit parasitic NPN turn-on.
Fig. 2a-2e are schematic structural diagrams of a conventional manufacturing process of a contact hole etching part, and referring to fig. 2a-2e, a Dry etching (Dry Etch) process is usually adopted in the contact hole etching process, and the etching process is to bombard the surface of a wafer by using plasma generated by special gas, so that the shape of the etched contact hole is in a groove shape with a certain depth-to-width ratio. The existing contact hole etching process mainly comprises the following steps: 1) the etch is stopped at the mesa surface (as shown in fig. 2 d), mainly by controlling the reaction time, and the second step is to etch the mesa again (as shown in fig. 2 e), forming a groove shape of a certain depth and shape, the depth in the mesa also being formed by controlling the reaction time.
Because etching gas for etching needs to have a certain selection ratio to different materials, the selection ratio of an Inter Layer Dielectric Layer (ILD) to a mesa (e.g., Si) is usually not very large, and meanwhile, the gas or temperature in an etching reaction chamber may have differences in different regions, which may cause differences in etching depths of different regions of a wafer, and further cause differences in latch-up resistance of IGBT chips in different regions of the same wafer, that is, it is relatively difficult to ensure the uniformity of contact hole depths at various positions in a single wafer.
Fig. 3 is a schematic flow chart of a manufacturing method of an insulated gate bipolar transistor IGBT according to an embodiment of the present invention; fig. 4 a-4 g are schematic views of the structure of a portion of the fabrication link of fig. 3. While a preferred implementation of the embodiments of the present invention is shown in fig. 4 a-4 g, it should be understood that the embodiments of the present invention may be implemented in various forms and should not be limited by the implementations set forth herein.
Referring to fig. 3, the method for manufacturing the insulated gate bipolar transistor IGBT may include the following steps:
step S110: and forming a basic structure of the IGBT on the front surface of the first material substrate.
Preferably, the first material is Si, and the first material substrate is a Si single crystal wafer.
The substrate of the first material is referred to as Si single crystal wafer hereinafter.
Further preferably, the Si single crystal wafer is an N-type single crystal wafer.
By way of illustration, a float-zone single crystal of N-type <100> crystal orientation may be selected as the substrate material, which has a resistivity of about 30 Ω/cm.
The base structure of the IGBT preferred in the embodiment of the present invention may be a trench MOS structure, and step S110 may include: etching a deep groove on the front surface of the first material single wafer, and thermally growing a gate oxide layer; depositing a Poly-Si layer, a P type body region and an N type heavily doped region on the gate oxide layer; and forming the basic structure of the IGBT by IMP implantation and annealing.
By way of illustration, the basic metal oxide can be formed on the front surface of a Si single crystal wafer based on an FS-Trench IGBT process platformThe Trench MOS structure of the semiconductor comprises a deep groove etched on a Si single crystal wafer and a gate oxide layer thermally grown; depositing a Poly-Si layer and P on the gate oxide layerbodyAnd a heavily doped N-type region (N +); by IMP implantation and annealing, the base structure of the IGBT as shown in fig. 4a can be formed.
Step S120: and depositing a second material film on the surface of the base structure.
Preferably, the second material is silicon nitride SIN, and the second material film is a SIN film.
In the following, the SIN film is often referred to as the second material film.
Further preferably, the thickness parameter of the second material film is 200-300A, wherein 1A is 10-10m。
Preferably, before step S120, the method for manufacturing an insulated gate bipolar transistor IGBT further includes: cleaning the surface of the base structure.
By way of example, the surface of the base structure of the IGBT is cleaned, and then a thick silicon carbide (SIN) film is deposited on the surface, for example, a 200A thick silicon carbide (SIN) film is deposited on the surface, to form the base structure of the IGBT as shown in fig. 4 b.
In the embodiment of the invention, preferably, before the process of manufacturing the interlayer dielectric layer film, a layer of SIN film is deposited to be used as a stop layer of the contact hole etching process, so that the depth of the contact hole at each position of the single chip is ensured to be uniform.
Step S130: and depositing an interlayer dielectric layer film on the surface of the second material film to form a structure to be etched.
Preferably, the step S130 may include: and sequentially depositing undoped silicon glass USG and phosphorosilicate glass BPSG with preset thicknesses on the surface of the second material film through chemical vapor deposition CVD to serve as the interlayer dielectric layer film, and flattening the surface of the interlayer dielectric layer film through a high-temperature reflux process.
By way of example, Undoped Silicate Glass (USG) and doped Boron and Phosphorus Silicate Glass (BPSG) are sequentially deposited on the SIN film surface by a Chemical Vapor Deposition (CVD) method to form an Inter Layer Dielectric (ILD) film, and then a high temperature reflow (reflow) process is performed to planarize the single crystal wafer surface.
Preferably, the thickness parameter of the doped silicate glass USG is 3000A, and the thickness parameter of the phosphosilicate glass BPSG is 9000A.
For example, 3000A Undoped Silicate Glass (USG) and 9000A doped Boron and Phosphorus Silicate Glass (BPSG) are deposited on the surface of the structure shown in fig. 4b by CVD as an ILD film, and then the surface of the ILD film is planarized by, for example, a 900 ℃ high temperature reflow (reflow) process to form the structure shown in fig. 4 c.
After step S130, the method for manufacturing the insulated gate bipolar transistor IGBT may further include: and moving the photomask graph of the contact hole to the surface of the interlayer dielectric layer film through photoresist coating and developing processes.
In connection with the above example, in the structure shown in fig. 4c, before the contact hole (contact) lithography process is performed on the surface of the ILD film, the mask pattern is transferred to the surface of the ILD film through the photoresist coating and developing processes, so as to form the structure shown in fig. 4 d.
Step S140: and etching the contact hole of the structure to be etched by a contact hole etching process and by preselected gas with high selectivity ratio to the third material and the second material and preselected gas with high selectivity ratio to the second material and the first material to form a contact hole groove.
Preferably, the third type of material is SiO 2.
Preferably, the step S140 may include: generating plasma through the preselected gas with high selection ratio to the third material and the second material, attacking the surface of the interlayer dielectric layer film, and stopping the attack on the surface of the second material film after a preset first control time; etching the second material film by the preselected gas with high selectivity ratio to the second material and the first material, and stopping the etching on the surface of the basic structure after a preset second control time; and etching the basic structure by using a preselected first material etching gas, and forming the contact hole groove after a preset third control time.
By way of example, performing a Contact hole etching (Contact Etch) process using a Dry Etch (Dry Etch) process on the structure shown in fig. 4d may include:
1) selecting special gas with high selection ratio of SiO2 and SIN material, generating plasma to bombard ILD (oxide) surface for etching, controlling reaction time, and making the reaction stay on the surface of SIN film to form the structure shown in FIG. 4 e;
2) selecting special gas with high selection ratio of SIN and Si materials, performing SIN etching, controlling reaction time, and making the reaction stay on the surface of Si to form a structure as shown in FIG. 4 f;
3) and finally, selecting special gas with a higher Si etching rate to perform Si etching, and controlling the depth of the contact hole groove by controlling the reaction time to finally form the structure shown in figure 4 g.
Since the etching gas has a large selection ratio to the silicon nitride (SIN) film and the silicon dioxide (SiO 2) or silicon (Si) material, it can also be used as a stop layer of the etching process. Before the ILD film is deposited, a layer of SIN film is deposited to be used as an intermediate stop layer for etching the contact hole, so that the uniformity of the etching depth of the contact hole in each area in the single crystal wafer can be improved.
Preferably, the method for manufacturing the insulated gate bipolar transistor IGBT may further include: forming a metal barrier layer on the surface of the contact hole groove by a Physical Vapor Deposition (PVD) process; and filling a metal material in the contact hole groove by Chemical Vapor Deposition (CVD).
The preferred material of the metal barrier layer in the embodiment of the present invention is Ti or TiN, and the filled metal material is tungsten.
By way of example, on the structure shown in fig. 4f, a Ti or TiN metal barrier layer is formed on the surface of the contact hole by means of a sputtering process in a Physical Vapor Deposition (PVD) process, and then the trench is filled with tungsten (W) metal by means of gas chemical Deposition (CVD).
Preferably, the method for manufacturing the insulated gate bipolar transistor IGBT may further include: and manufacturing the front electrode by Physical Vapor Deposition (PVD) and a photoetching process.
The front electrode in the embodiment of the invention is preferably made of Al-Cu alloy.
In connection with the above example, the front electrode may be fabricated by sputtering and photolithography, and the front metal electrode material may be Al — Cu alloy, wherein the Cu content is preferably less than 5%.
Preferably, the method for manufacturing the insulated gate bipolar transistor IGBT may further include: and thinning the back of the first material substrate by adopting a taiko thinning process and a chemical corrosion mode.
In accordance with the above example, the back surface of the Si single crystal wafer is thinned by a taiko thinning process and a chemical etching method to thin the Si single crystal wafer to, for example, 60um, and then the Si single crystal wafer is cleaned.
Preferably, the method for manufacturing the insulated gate bipolar transistor IGBT may further include: taking a first acceptor element which is preselected as an ion implantation source, and performing ion implantation on the back of the first-class material substrate according to a first implantation dosage and a first implantation energy which are preselected; and annealing through a laser annealing process to form the buffer layer.
In an embodiment of the present invention, the first acceptor element is preferably phosphorus, the first implantation dose is preferably 5e12, and the first implantation energy is preferably 2 Mev.
Taking the above example as a support, a suitable donor element is selected as an ion implantation source, a suitable dose and energy are selected, implantation is performed by an ion implantation method, and annealing is performed by a laser annealing method, so as to form a buffer (N-type buffer) layer. The donor element may be a phosphorus (P) element, the implant energy may be 2Mev, and the implant dose may be 5E 12.
Preferably, the method for manufacturing the insulated gate bipolar transistor IGBT may further include: taking a second preselected acceptor element as an ion implantation source, and performing ion implantation on the back surface of the first material substrate according to a second preselected implantation dose and second implantation energy; and annealing through a laser annealing process to form the P-collector layer.
In the embodiment of the present invention, the second acceptor element is preferably boron, the second implantation dose is preferably 5e12, and the second implantation energy is preferably 20 ev.
According to the above example, a suitable acceptor element is selected as an ion implantation source, a suitable dose and energy are selected for the back surface of the Si single crystal wafer, implantation is performed in an ion implantation manner, and annealing is performed in a laser annealing (LTA) manner, so as to form a P-collector layer of the FS-IGBT. The acceptor element may be a boron (B) element, the implantation energy may be 20Kev, and the implantation dose may be 5E 12.
Preferably, the method for manufacturing the insulated gate bipolar transistor IGBT may further include: and manufacturing a back electrode on the back of the first material substrate by a Physical Vapor Deposition (PVD) process.
The back electrode in the preferred embodiment of the present invention is a 4-layer metal electrode, and the material of the back electrode is Al, Ti, Ni, and Ag in this order.
Taking the above example as a support, a back metal electrode of a Si single wafer may be fabricated through a sputtering (sputtering) process, and the material layer of the back metal electrode may be AL-Ti-Ni-Ag in sequence, so that a complete trench FS-IGBT device may be obtained.
Therefore, the embodiment of the invention aims at the problem that the depth of the contact hole groove in the single chip is difficult to control to be uniform in the contact hole etching process, and the second material film is deposited before the process of manufacturing the interlayer dielectric layer film to be used as a stop layer for etching the contact hole, so that the uniform depth of the contact hole at each position of the single chip is ensured; and the contact hole etching is carried out through preselected gas with high selection ratio to the third material and the second material and preselected gas with high selection ratio to the second material and the first material, so that the etching depth uniformity of the contact hole in each area in the single crystal wafer is improved, and the IGBT device is more stable in latch-up resistance.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims (21)

1. A manufacturing method of an Insulated Gate Bipolar Transistor (IGBT) is characterized by comprising the following steps:
forming a basic structure of the IGBT on the front surface of a first material substrate;
depositing a second material film on the surface of the base structure;
depositing an interlayer dielectric layer film on the surface of the second material film to form a structure to be etched;
and etching the contact hole of the structure to be etched by a contact hole etching process and by preselected gas with high selectivity ratio to the third material and the second material and preselected gas with high selectivity ratio to the second material and the first material to form a contact hole groove.
2. The method of claim 1, wherein the first material is Si, the first substrate is Si single wafer, the second material is silicon nitride (SIN), and the second material is silicon nitride (SIN)The film is an SIN film, and the third material is SiO2。
3. The method of manufacturing an Insulated Gate Bipolar Transistor (IGBT) according to claim 2, wherein the Si single crystal wafer is an N-type single crystal wafer.
4. The method according to claim 1, wherein the base structure of the IGBT is a trench MOS structure, and the forming the base structure of the IGBT on the front surface of the first-type material single crystal wafer includes:
etching a deep groove on the front surface of the first material single wafer, and thermally growing a gate oxide layer;
depositing a Poly-Si layer, a P type body region and an N type heavily doped region on the gate oxide layer;
and forming the basic structure of the IGBT by IMP implantation and annealing.
5. The method of manufacturing an Insulated Gate Bipolar Transistor (IGBT) according to claim 1, wherein before depositing the second material film on the surface of the base structure, the method further comprises:
cleaning the surface of the base structure.
6. The method as claimed in claim 2, wherein the thickness parameter of the second material film is 200-300A.
7. The method for manufacturing the Insulated Gate Bipolar Transistor (IGBT) according to claim 1, wherein the step of depositing the interlayer dielectric layer film on the surface of the second material film comprises the following steps:
and sequentially depositing undoped silicon glass USG and phosphorosilicate glass BPSG with preset thicknesses on the surface of the second material film through chemical vapor deposition CVD to serve as the interlayer dielectric layer film, and flattening the surface of the interlayer dielectric layer film through a high-temperature reflux process.
8. The method according to claim 7, wherein the thickness parameter of the doped silicate glass USG is 3000A and the thickness parameter of the phosphosilicate glass BPSG is 9000A.
9. The method according to claim 1, wherein after depositing an interlayer dielectric film on the surface of the second material film to form a structure to be etched, the method further comprises:
and moving the photomask graph of the contact hole to the surface of the interlayer dielectric layer film through photoresist coating and developing processes.
10. The method as claimed in claim 1, wherein the step of etching the contact hole of the structure to be etched by the contact hole etching process through the gas with the high selectivity ratio to the third material and the second material and the gas with the high selectivity ratio to the second material and the first material to form the contact hole groove comprises the steps of:
generating plasma through the preselected gas with high selection ratio to the third material and the second material, attacking the surface of the interlayer dielectric layer film, and stopping the attack on the surface of the second material film after a preset first control time;
etching the second material film by the preselected gas with high selectivity ratio to the second material and the first material, and stopping the etching on the surface of the basic structure after a preset second control time;
and etching the basic structure by using a preselected first material etching gas, and forming the contact hole groove after a preset third control time.
11. The method of manufacturing an Insulated Gate Bipolar Transistor (IGBT) according to claim 1, further comprising:
forming a metal barrier layer on the surface of the contact hole groove by a Physical Vapor Deposition (PVD) process; and filling metal materials in the contact hole groove by Chemical Vapor Deposition (CVD).
12. The method according to claim 11, wherein the metal barrier layer is made of Ti or TiN, and the filled metal material is tungsten.
13. The method of manufacturing an Insulated Gate Bipolar Transistor (IGBT) according to claim 11, further comprising:
and manufacturing the front electrode by Physical Vapor Deposition (PVD) and a photoetching process.
14. The method according to claim 13, wherein the material of the front electrode is an Al — Cu alloy.
15. The method of manufacturing an Insulated Gate Bipolar Transistor (IGBT) according to claim 1, further comprising:
and thinning the back of the first material substrate by adopting a taiko thinning process and a chemical corrosion mode.
16. The method of manufacturing an Insulated Gate Bipolar Transistor (IGBT) according to claim 15, further comprising:
taking a first preselected acceptor element as an ion implantation source, and performing ion implantation on the back surface of the first material substrate according to a first preselected implantation dose and a first implantation energy;
and annealing through a laser annealing process to form the buffer layer.
17. The method according to claim 16, wherein the first acceptor element is phosphorus, the first implantation dose is 5e12, and the first implantation energy is 2 Mev.
18. The method of manufacturing an Insulated Gate Bipolar Transistor (IGBT) according to claim 16, further comprising:
taking a second preselected acceptor element as an ion implantation source, and performing ion implantation on the back surface of the first material substrate according to a second preselected implantation dose and second implantation energy;
and annealing through a laser annealing process to form the P-collector layer.
19. The method of manufacturing an Insulated Gate Bipolar Transistor (IGBT) according to claim 18, wherein the second acceptor element is boron, the second implantation dose is 5e12, and the second implantation energy is 20 ev.
20. The method of manufacturing an Insulated Gate Bipolar Transistor (IGBT) according to claim 18, further comprising:
and manufacturing a back electrode on the back of the first material substrate by a Physical Vapor Deposition (PVD) process.
21. The method according to claim 20, wherein the back electrode is a 4-layer metal electrode made of Al, Ti, Ni, and Ag in this order.
CN202210411916.0A 2022-04-19 2022-04-19 Manufacturing method of insulated gate bipolar transistor IGBT Pending CN114512537A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105765726A (en) * 2013-12-10 2016-07-13 株式会社爱发科 Insulated gate bipolar transistor and production method therefor
CN109712887A (en) * 2018-12-17 2019-05-03 成都森未科技有限公司 A kind of manufacturing method of semiconductor devices collecting zone
CN213816159U (en) * 2020-12-31 2021-07-27 北京燕东微电子科技有限公司 Power semiconductor device
CN114038743A (en) * 2022-01-07 2022-02-11 绍兴中芯集成电路制造股份有限公司 Manufacturing method of trench gate device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105765726A (en) * 2013-12-10 2016-07-13 株式会社爱发科 Insulated gate bipolar transistor and production method therefor
CN109712887A (en) * 2018-12-17 2019-05-03 成都森未科技有限公司 A kind of manufacturing method of semiconductor devices collecting zone
CN213816159U (en) * 2020-12-31 2021-07-27 北京燕东微电子科技有限公司 Power semiconductor device
CN114038743A (en) * 2022-01-07 2022-02-11 绍兴中芯集成电路制造股份有限公司 Manufacturing method of trench gate device

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