CN114512510A

CN114512510A - Display device

Info

Publication number: CN114512510A
Application number: CN202011278538.0A
Authority: CN
Inventors: 丁景隆; 周政旭; 曾名骏; 陈韵升; 张志雄; 陈良禄
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2020-11-16
Filing date: 2020-11-16
Publication date: 2022-05-17
Also published as: US20220157998A1

Abstract

The present disclosure provides a display device, including a substrate; the channel layer is arranged on the substrate and comprises a first channel layer and a second channel layer; the first metal layer is arranged on the channel layer and comprises a first grid and a second grid; and the second metal layer is arranged on the first metal layer and comprises a first source electrode, a first drain electrode and a second source electrode. The first gate, the first source, the first drain and the first channel layer form a first transistor, and the second gate, the second source, the first drain and the second channel layer form a second transistor. Wherein the first transistor is connected in parallel with the second transistor.

Description

Display device

Technical Field

The present disclosure relates to a display device, and more particularly, to a display device having a gate and a source/drain concentrically arranged.

Background

In a display device, a Thin Film Transistor (TFT) is a technology widely used to drive a pixel (e.g., a light emitting element). However, the existing thin film transistor still has some problems. In a new type of display device, a large current is often required to drive a light emitting element (light emitting unit). However, if a light emitting element is driven by a single transistor, the transistor may experience an excessive current, which may result in a shortened lifetime or reduced reliability.

The transistor's hump effect (bump effect) will cause a decrease in reliability. In the current thin film transistor, the edge regions of both sides of the channel layer have a slope profile. In these edge regions, the thin layer (e.g., gate insulating layer) between the channel layer and the gate may have a non-uniform thickness. For example, the thickness of the gate insulating layer on the edge region is lower than the thickness of the gate insulating layer on the central region. In the Edge region, therefore, Edge (Edge) TFTs different from the center TFT may be formed.

In edge TFTs, a thinner gate insulating layer may trap (trap) electrons (or holes) due to the gate voltage during operation. These electrons (or holes) accumulate to cause a doming effect and shift the threshold voltage (Vth) of the device. The Vth shift affects device characteristics, particularly switching characteristics, such that the device cannot normally operate at a predetermined voltage or current, thereby reducing device reliability.

Therefore, a display device capable of integrating a plurality of thin film transistors to supply a large current and thereby increase the durability of the thin film transistors is required. Alternatively, there is a need for a thin film transistor that can address the blooming effect and increase the reliability of the thin film transistor.

Disclosure of Invention

The embodiment of the disclosure provides a display device. The display device comprises a substrate; the channel layer is arranged on the substrate and comprises a first channel layer and a second channel layer; the first metal layer is arranged on the channel layer and comprises a first grid and a second grid; and a second metal layer disposed on the first metal layer, the second metal layer including a first source, a first drain, and a second source. The first transistor is formed by the first grid electrode, the first source electrode, the first drain electrode and the first channel layer, and the second transistor is formed by the second grid electrode, the second source electrode, the first drain electrode and the second channel layer. Wherein the first transistor is connected in parallel with the second transistor.

Drawings

The disclosure can be better understood from the following description and the accompanying drawings. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. It is also to be emphasized that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may be applied to other embodiments.

FIG. 1 is a schematic diagram of a circuit shown in accordance with an embodiment of the present disclosure.

Fig. 2 is a top view showing the layout of the parallel drive transistors in the circuit according to an embodiment of the present disclosure.

FIG. 3 is a cross-sectional view of the layout of FIG. 2, shown in accordance with an embodiment of the present disclosure.

FIG. 4 is a cross-sectional view of the layout of FIG. 2, shown in accordance with an embodiment of the present disclosure.

Fig. 5 is a top view showing the layout of the parallel drive transistors in the circuit according to an embodiment of the present disclosure.

Fig. 6 is a top view showing the layout of the parallel drive transistors in the circuit according to an embodiment of the present disclosure.

Description of the symbols

1 display device

100 circuit

110 data line

120 scan line

130 switching transistor

140,140-1 to 140-5 drive transistors

150 storage capacitor

160 light emitting element

180 dotted line frame

Vg gate voltage

Voltage Vs

D node

Vdd first voltage

Vss second Voltage

I1-I5 current

It total current

310 base plate

200 layout

M1 first Metal layer

205 doped source/drain layers

210 first source doped layer

212 second Source doping layer

214 third Source doping layer

220 first drain doped layer

222 second drain doped layer

224 third drain doping layer

230 first grid

232 the second grid

234 third gate

236 fourth grid

238 fifth grid

W1 first channel Width

W2 second channel Width

L1 first channel Length

L2 second channel Length

A-B is line segment

C-D line segment

320 first functional layer

330 second functional layer

340 channel layer

350 gate insulating layer

W4-W7 width

500 arrangement

M2 second Metal layer

540 first conductive feature

Second conductive feature 550

560 through hole

510 first source electrode

512 the second source

514 third source

520 first drain electrode

522 second drain electrode

524 the third drain electrode

600: layout

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of the components and arrangements of the present disclosure are set forth below to simplify the description. Of course, these examples are not intended to limit the present disclosure. For example, the description herein may include embodiments in which the first feature is formed over or on the second feature, which may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that there is no direct contact between the first and second features, and may include embodiments in which the first feature is located on or off-normal to the second feature. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, the present disclosure may use spatially relative terms, such as "below …", "below", "above …", "above", and the like, to facilitate describing the relationship of one element or feature to another element or feature in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be turned to a different orientation (rotated 90 degrees or otherwise) and the spatially relative terms used herein should be interpreted accordingly.

Still further, unless specifically stated otherwise, singular words include plural words and vice versa. When a number or range of numbers is described in terms of "about," "approximately," or the like, the term is intended to encompass reasonable numbers including the stated number, such as +/-10% of the stated number or other value as understood by one of ordinary skill in the art.

In the present disclosure, the length and the width may be measured by an optical microscope, and the thickness may be measured by a cross-sectional image in an electron microscope, but not limited thereto. In addition, there may be some error in any two values or directions for comparison. In the present disclosure, features of the embodiments may be arbitrarily mixed and matched without departing from the spirit or conflict of the invention.

The present disclosure provides an electronic device, which may include a display device, an antenna device, a sensing device, or a tiled device, but is not limited thereto. It should be noted that the electronic device can be any permutation and combination of the foregoing, but is not limited thereto. The following will describe the present disclosure with a display device as an electronic device or a tiled device, but the present disclosure is not limited thereto. The electronic device of the present disclosure may be implemented using the circuit 100 shown in fig. 1.

Fig. 1 is a schematic diagram of a circuit 100 in a display device 1 shown according to an embodiment of the disclosure. In some embodiments, the display device 1 may include a substrate 310, a circuit 100, and a light emitting element 160. The circuit 100 may be disposed on the substrate 310. The circuit 100 may be a driving circuit (driving circuit) of the light emitting element 160. The circuit 100 includes a data line (data line)110, a scan line (scan line)120, a switching transistor 130, a driving transistor 140, and a storage capacitor 150. In the embodiment of the present disclosure, the switch transistor 130 and the driving transistor 140 may be a thin film transistor (tft), but is not limited thereto. In some embodiments, a pixel (pixel) may be defined as a region where a signal line and a scan line are interlaced, and a switching transistor 130, a driving transistor 140, a light emitting element 160, and a storage capacitor 150 (but not limited thereto) such as those described above may be disposed in the pixel, but the disclosure is not limited thereto.

The substrate 310 may be a rigid substrate or a flexible substrate. In some embodiments, the material of the rigid substrate may include glass, quartz, ceramic, sapphire, plastic, or the like, but the disclosure is not limited thereto. In some embodiments, the material of the flexible substrate may include Polycarbonate (PC), Polyimide (PI), polypropylene (PP), or polyethylene terephthalate (PET), other suitable materials, or a combination thereof, but the disclosure is not limited thereto. In other embodiments, the substrate 310 may comprise a suitable elemental semiconductor, such as germanium or diamond; suitable compound semiconductors such as silicon carbide, gallium nitride, gallium arsenide, or indium phosphide; or a suitable alloy semiconductor such as silicon germanium, silicon tin, aluminum gallium arsenide, or gallium arsenide phosphide, although the disclosure is not so limited. In some embodiments, the thickness of the substrate 310 (measured along the Z-direction) may be greater than or equal to 0.3 centimeters and less than or equal to 1 centimeter, although the disclosure is not limited thereto.

In the embodiment shown in FIG. 1, circuit 100 includes, for example, 5 parallel driver transistors 140, such as driver transistor 140-1, driver transistor 140-2, driver transistor 140-3, driver transistor 140-4, and driver transistor 140-5, as indicated in FIG. 1. However, it should be noted that the present disclosure is not limited to 5 parallel drive transistors 140. In other embodiments, the circuit 100 produced by the manufacturer according to the requirements of the actual application may include any suitable number of driving transistors 140.

In the embodiment shown in FIG. 1, the circuit 100 may include five electronic units, one of which is 2T1C (a switching transistor, a driving transistor, and a capacitor), and the remaining four of which are 1T1C (a driving transistor, a capacitor, and a common switching transistor with the 2T1C electronic unit). For example, the switching transistor 130, the driving transistor 140-1 and the capacitor 150 in fig. 1 form a first electronic unit, the driving transistor 140-2 and the capacitor 150 form a second electronic unit, the driving transistor 140-3 and the capacitor 150 form a third electronic unit, the driving transistor 140-4 and the capacitor 150 form a fourth electronic unit, the driving transistor 140-5 and the capacitor 150 form a fifth electronic unit, and the second electronic unit, the third electronic unit, the fourth electronic unit and the fifth electronic unit may share the switching transistor 130 in the first electronic unit, but the disclosure is not limited thereto.

In some embodiments, the five electronic units included in the circuit 100 may be 2T1C, that is, each driving transistor may be configured with a switching transistor. In these embodiments, all of the drive transistors are not disabled by the failure of one switching transistor. In some other embodiments, each electronic unit may include any number of transistors. For example, each electronic unit may include a switching transistor and a driving transistor, such as a second switching transistor, but the disclosure is not limited thereto. However, as described above, the present disclosure is not limited to 5 parallel driving transistors 140, and thus is not limited to 5 electronic units. In other embodiments, circuit 100 may include any suitable number of electronic units.

In the circuit 100, the scan line 120 is electrically connected to the gate of the switching transistor 130 to control the on/off of the switching transistor 130. The second electrode of the switching transistor 130 is electrically connected to the gate of the driving transistor 140 (e.g., the driving transistor 140-1) and provides a gate voltage Vg to control the on/off of the driving transistor 140. The first voltage Vdd is connected to the first electrode of the driving transistor 140 and provides a voltage Vs. The storage capacitor 150 is connected to the gate and the first electrode of the driving transistor 140 to stabilize the voltage across the gate and the first electrode.

The nodes D of the second electrode terminal of each of the driving transistors 140 are connected together so that each of the driving transistors 140 is connected in parallel with each other, for example, the driving transistors 140-1 to 140-5 are connected in parallel with each other. The node D is connected to the anode of the light emitting element 160 to supply current to the light emitting element 160. More specifically, as shown in FIG. 1, the current flowing through the driving transistor 140-1 is the current I1, the current flowing through the driving transistor 140-2 is the current I2, the current flowing through the driving transistor 140-3 is the current I3, the current flowing through the driving transistor 140-4 is the current I4, and the current flowing through the driving transistor 140-5 is the current I5. The total current It may be the sum of the current I1, the current I2, the current I3, the current I4, and the current I5. The total current It flows through the light emitting element 160 and causes the light emitting element 160 to emit light. It is noted that when the circuit 100 needs to provide a larger total current It of the light emitting device 160, a plurality of driving transistors 140 can be connected in parallel, so as to reduce the current (e.g., the current I1 to the current I5) passing through each driving transistor 140, thereby increasing the endurance of the driving transistors 140 and prolonging the lifetime.

The light emitting element 160 may be a light emitting diode including an Organic Light Emitting Diode (OLED), a submillimeter light emitting diode (mini LED), a micro light emitting diode (micro LED) or a quantum dot light emitting diode (QD, such as QLED or QDLED), a fluorescent light (fluorescent), a phosphorescent light (phosphor) or other suitable materials, and the materials may be arranged and combined in any manner, but the disclosure is not limited thereto. The cathode of the light emitting element 160 is connected to a second voltage Vss (e.g., ground).

In fig. 1, a dashed box 180 is used to indicate a plurality of drive transistors 140 in parallel. In the embodiment shown in FIG. 1, 5 parallel driver transistors 140 (e.g., driver transistor 140-1 through driver transistor 140-5) are included in dashed box 180. The equivalent circuit of these drive transistors 140, in dashed box 180, may be shown as layout 200 and is depicted in fig. 2.

Fig. 2 is a top view illustrating a layout 200 of the driving transistors 140-1 to 140-5 connected in parallel of the circuit 100 of fig. 1, according to an embodiment of the disclosure. Layout 200 includes first metal layer M1 and includes a source/drain doped layer 205 (also referred to as doped layer 205), such as a source doped layer or a drain doped layer. In some embodiments, the first metal layer M1 may serve as a gate of the driving transistor 140. In detail, the first metal layer M1 may include a first gate 230, a second gate 232, a third gate 234, a fourth gate 236, and a fifth gate 238. In some embodiments, source/drain doped layer 205 may include first source doped layer 210, first drain doped layer 220, second source doped layer 212, second drain doped layer 222, third source doped layer 214, and third drain doped layer 224.

The material of the first metal layer M1 may include aluminum (Al), copper (Cu), gold (Au), silver (Ag), tungsten (W), cobalt (Co), ruthenium (Ru), other suitable conductive materials, or a combination thereof, but the disclosure is not limited thereto. The first metal layer M1 may be formed on a gate insulation layer (e.g., the gate insulation layer 350 discussed below with reference to fig. 3) by a suitable deposition process, a photolithography process, and an etching process. In some embodiments, the photolithography process includes photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, developing the photoresist, rinsing (rinsing), and drying (e.g., hard baking). In other embodiments, the photolithography process may be performed or replaced by other suitable methods, such as mask-less photolithography (maskless lithography), electron-beam writing (electron-beam writing), and ion-beam writing (ion-beam writing).

In some embodiments, the etching process may include dry etching, wet etching, Reactive Ion Etching (RIE), and/or other suitable processes, but the disclosure is not limited thereto. In some embodiments, the deposition process of the first metal layer M1 may include PVD, CVD, sputtering, evaporation, pulsed laser deposition, LPCVD, LTCVD, RTCVD, PECVD, HDPCVD, MOCVD, RPCVD, ALD, other suitable processes, and/or combinations thereof, but the disclosure is not limited thereto. In some embodiments, the thickness (measured along the Z direction) of the first metal layer M1 may be greater than or equal to 0.05 microns and less than or equal to 0.5 microns, although the disclosure is not so limited.

In the layout 200, the first metal layer M1 and the source/drain doped layer 205 are substantially surrounded by each other in a concentric rectangular manner. For example, in the embodiment shown in fig. 2, the center of the concentric rectangles is the first source doped layer 210, the first gate 230 surrounds the first source doped layer 210, the first drain doped layer 220 surrounds the first gate 230, the second gate 232 surrounds the first drain doped layer 220, the second source doped layer 212 surrounds the second gate 232, and the third gate 234 surrounds the second source doped layer 212. Next, the second drain doped layer 222 surrounds the third gate 234, the fourth gate 236 surrounds the second drain doped layer 222, the third source doped layer 214 surrounds the fourth gate 236, the fifth gate 238 surrounds the third source doped layer 214, and the third drain doped layer 224 surrounds the fifth gate 238. It is noted that the term "surround" as used in this disclosure may include a complete surround, and may also include a partial surround. For example, in the case that the first gate 230 surrounds the first source doped layer 210, the first gate 230 may surround the first source doped layer 210 by 360 degrees, or the first gate 230 may surround by more than 270 degrees, which is not limited in the disclosure.

Referring to fig. 1 and 2, in the layout 200, transistors may share a source doped layer or a drain doped layer. For example, a first transistor (e.g., driving transistor 140-1) shares the first drain doped layer 220 with a second transistor (e.g., driving transistor 140-2), the second transistor shares the second source doped layer 212 with a third transistor (e.g., driving transistor 140-3), the third transistor shares the second drain doped layer 222 with a fourth transistor (e.g., driving transistor 140-4), and the fourth transistor shares the third source doped layer 214 with a fifth transistor (e.g., driving transistor 140-5).

Although not shown in fig. 2, a channel layer is included under the first metal layer M1 and sandwiched between the source and the drain. In more detail, a channel layer may be disposed on the substrate 310, and the first metal layer M1 is disposed on the channel layer. In this embodiment, the channel layer may include a first channel layer, a second channel layer, a third channel layer, a fourth channel layer and a fifth channel layer, and is disposed corresponding to the first gate 230, the second gate 232, the third gate 234, the fourth gate 236 and the fifth gate 238, respectively. For example, the first gate 230 is disposed on a first channel layer, wherein the first channel layer has substantially the same size as the first gate 230. The second gate 232 is disposed on the second channel layer, wherein the second channel layer has substantially the same size as the second gate 232. The third gate 234 is disposed on the third channel layer, wherein the third channel layer has substantially the same size as the third gate 234. The fourth gate 236 is disposed on the fourth channel layer, wherein the fourth channel layer has substantially the same size as the fourth gate 236. The fifth gate 238 is disposed on the fifth channel layer, wherein the dimensions of the fifth channel layer are substantially the same as the dimensions of the fifth gate 238. It is to be noted that the "dimension" referred to in the present disclosure may include a maximum width in the X direction, an area in a plan view direction, or a maximum length in the Y direction, but the present disclosure is not limited thereto as long as the present disclosure can be clearly expressed and meets the purpose of the present disclosure.

According to some embodiments, the second channel layer surrounds the first channel layer, and the third channel layer surrounds the second channel layer. In some embodiments, the fourth channel layer surrounds the third channel layer, and the fifth channel layer surrounds the fourth channel layer.

In layout 200, different transistors may have different channel widths (channel widths) and/or different channel lengths (channel lengths). Alternatively, different transistors may have different channel width to channel length ratios. In the layout 200, the first transistor (e.g., the driving transistor 140-1) has a first channel width W1 and a first channel length L1, and the second transistor (e.g., the driving transistor 140-1) has a second channel width W2 and a second channel length L2, as shown in FIG. 2. In some embodiments, the first channel width W1 is different from the second channel width W2. In some embodiments, the first channel length L1 is different than the second channel length L2. Alternatively, in some embodiments, the ratio of the first channel width W1 to the first channel length L1 (W1/L1) is different than the ratio of the second channel width W2 to the second channel length L2 (W2/L2). In other embodiments, the channel widths of other transistors in the layout 200 may be different from the first channel width W1 and/or the second channel width W2, and the channel lengths may be different from the first channel length L1 and/or the second channel length L2. Alternatively, other transistors may have different channel width to length ratios.

Transistors with different channel widths can provide different magnitudes of current because the larger the channel width, the larger the current that the transistor can flow. In the embodiment of the present disclosure, since the current is provided by a plurality of transistors connected in parallel, the transistor with a larger channel width can provide a larger current to compensate for the transistor with a smaller current. For example, when the current of some transistors is lower than expected due to process problems, a transistor with a larger channel width can be used to provide a larger current to compensate for the missing current.

It should be noted that although layout 200 in fig. 2 shows 5 transistors in parallel, the present disclosure is not so limited. As noted above, the present disclosure may include any suitable number of transistors, and thus the layout 200 may be modified accordingly. One skilled in the art would readily increase or decrease the number of source doped layers, drain doped layers, gates, etc. in layout 200 based on the number of transistors, and such modifications are encompassed by the present disclosure.

FIG. 3 is a cross-sectional view of the layout 200 of FIG. 2, taken along the line A-B, shown in accordance with an embodiment of the present disclosure. Fig. 3 is a cross-sectional view of a drive transistor (e.g., drive transistor 140-4) in the X-Z plane. FIG. 4 is a cross-sectional view of the layout 200 of FIG. 2, shown on line C-D, in accordance with an embodiment of the present disclosure. Fig. 4 is a cross-sectional view of a drive transistor (e.g., drive transistor 140-4) in the Y-Z plane.

As shown in fig. 3, the display device 1 may include, but is not limited to: a substrate 310, a first functional layer 320 such as a barrier layer (barrier layer), a second functional layer 330 such as a buffer layer (buffer layer), a fourth channel layer 340, a third source doped layer 214, a second drain doped layer 222, a gate insulating layer 350, and a fourth gate 236. It should be noted that, for clarity of illustration, the gate insulating layer 350 is not shown in fig. 2, but rather the doped layer 205 is shown below the gate insulating layer 350.

Each of first functional layer 320 and second functional layer 330 may comprise a single thin layer or a plurality of thin layers. The first functional layer 320 and the second functional layer 330 may include an insulating material. In some embodiments, the first functional layer 320 and the second functional layer 330 may include organic materials, inorganic materials, or a combination thereof, but the disclosure is not limited thereto. For example, the organic material may include polyethylene terephthalate (PET), Polyethylene (PE), Polyether Sulfone (PEs), Polycarbonate (PC), polymethyl methacrylate (PMMA), isoprene (isoprene), phenol-formaldehyde resin (phenol-formaldehyde resin), benzocyclobutene (BCB), Perfluorocyclobutane (PECB), or a combination thereof, but the disclosure is not limited thereto. The inorganic material may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, titanium oxide, other suitable materials, or combinations thereof, although the disclosure is not limited thereto.

In some embodiments, the first functional layer 320 and the second functional layer 330 may be formed on the substrate 310 by a deposition process. The deposition process may include a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, a coating process, other suitable processes, or combinations thereof. The pvd process may include a sputtering process, an evaporation process, a pulsed laser deposition process, etc., but the disclosure is not limited thereto. The CVD process may include a Low-Pressure CVD (LPCVD) process, a Low-Temperature CVD (LTCVD) process, a Rapid Thermal CVD (RTCVD) process, a Plasma Enhanced CVD (PECVD) process, a high-density plasma CVD (HDPCVD) process, a Metal Organic CVD (MOCVD) process, a Remote Plasma CVD (RPCVD) process, an Atomic Layer Deposition (ALD) process, an electroplating (plating), other suitable processes, and/or combinations thereof, but the disclosure is not limited thereto. In some embodiments, the first functional layer 320 and the second functional layer 330 may be formed in different process chambers. In some embodiments, the thickness (measured along the Z direction) of the first functional layer 320 may be greater than or equal to 3000 angstroms (angstrom) and less than or equal to 7000 angstroms, although the disclosure is not limited thereto. In some embodiments, the thickness (measured along the Z direction) of the second functional layer 330 may be greater than or equal to 500 angstroms and less than or equal to 3000 angstroms, although the disclosure is not limited thereto.

A first material layer may be formed on the second functional layer 330, and the channel layer 340 and the doped layer 205 may be formed by using the first material layer in a subsequent process. In other words, the first material layer includes, for example, the channel layer 340 and the doped layer 205. The material of the first material layer may be polycrystalline silicon (Poly-Si), amorphous silicon (amorphous Si), Indium Gallium Zinc Oxide (IGZO), or the like, but the disclosure is not limited thereto. In some embodiments, the first material layer may be formed on the second functional layer 330 by a deposition process. The deposition process may include PVD, CVD, sputtering, evaporation, pulsed laser deposition, LPCVD, LTCVD, RTCVD, PECVD, HDPCVD, MOCVD, RPCVD, ALD, other suitable processes, and/or combinations thereof, although the disclosure is not limited thereto. In some embodiments, the thickness of the first material layer (measured along the Z-direction) may be greater than or equal to 100 angstroms and less than or equal to 600 angstroms, although the disclosure is not limited thereto.

The material of the gate insulating layer 350 may include an organic material, such as Polyimide (PI), polyethylene terephthalate (PET), Polyethylene (PE), Polyether Sulfone (PEs), Polycarbonate (PC), polymethyl methacrylate (PMMA), isoprene (isoprene), phenol resin, benzocyclobutene (BCB), Perfluorocyclobutane (PECB), or a combination thereof, but the disclosure is not limited thereto. In some embodiments, the gate insulation layer 350 may be formed on the first material layer by a deposition process. The deposition process may include PVD, CVD, sputtering, evaporation, pulsed laser deposition, LPCVD, LTCVD, RTCVD, PECVD, HDPCVD, MOCVD, RPCVD, ALD, other suitable processes, and/or combinations thereof, although the disclosure is not limited thereto. In some embodiments, the thickness (measured along the Z-direction) of the gate insulation layer 350 may be greater than or equal to 500 angstroms and less than or equal to 3000 angstroms, although the disclosure is not limited thereto.

According to some embodiments, after forming the first metal layer M1, the first metal layer M1 may be used as an implantation mask to dope the first material layer. In some embodiments, dopant (dopant) may be doped into the first material layer in the regions not shielded by the first metal layer M1 by ion implantation (implantation) process to form heavily doped source/drain regions, such as heavily doped P-type polysilicon (P)⁺Poly-Si). These heavily doped source/drain regions form doped layer 205. In addition, the channel layer 340 is formed in the regions of the first material layer not doped with the dopant. The channel layer 440 is used as a channel of the driving transistor 140.

In an embodiment where the driving transistor 140 is a p-type transistor, the dopant may be a p-type dopant such as boron, but the disclosure is not limited thereto. In embodiments where the driving transistor 140 is an n-type transistor, the dopant may be an n-type dopant such as phosphorus or arsenic, but the disclosure is not limited thereto.

By using the gate (e.g., the first metal layer M1) as an implantation mask, it is ensured that the channel layer under the gate has a width substantially equal to the gate width. More specifically, it is ensured that the gate width is substantially equal to the width of the channel layer in the normal direction of the substrate (e.g., the Z direction). Referring to fig. 3, the width W4 of the first metal layer M1 (e.g., the fourth gate 236) is substantially equal to the width W5 of the channel layer 340 in the X direction in the direction (X direction) perpendicular to the normal direction (Z direction) of the substrate. Referring to FIG. 4, the width W6 of the first metal layer M1 (e.g., the fourth gate 236) in the Y direction is substantially equal to the width W7 of the channel layer 340 in the Y direction.

By using the layout 200 and the corresponding process shown in FIG. 2, the channel layer 340 and the gate insulating layer 350 may be formed with uniform thickness, and the gate and channel layers may be formed with substantially the same width in a direction (e.g., X direction) perpendicular to the normal direction (e.g., Z direction) of the substrate. In this way, the slope profile of the edge regions on both sides of the channel layer is eliminated, i.e., no slope is generated in the gate insulation layer 350 near the edge of the channel layer 340. As shown in fig. 3 and 4, since the width of the channel layer 340 is substantially the same as the width of the gate (e.g., the fourth gate 236), and the channel layer 340 and the gate insulating layer 350 have substantially uniform thickness, the edge regions on both sides of the channel layer have no slope profile. Therefore, the probability of generating edge transistors or the probability of capturing electrons or holes by the gate insulating layer is reduced. Therefore, the doming effect is improved or the reliability of the transistor is increased.

After the doped layer 205 is formed by implantation, a subsequent process may be performed to form a second metal layer M2 as a source/drain, wherein the second metal layer M2 is shown in fig. 5. In some embodiments, referring to fig. 3, an inter-layer dielectric (ILD), not shown, may be formed on the gate insulating layer 350 and the first metal layer M1 (e.g., the fourth gate 236). The interlayer dielectric layer may include a dielectric material, such as Tetraethylorthosilicate (TEOS), undoped silicate glass (silicate glass), or a doped silicon oxide, such as borophosphosilicate glass (BPSG), Fused Silica Glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG), other suitable dielectric materials, or combinations thereof, although the disclosure is not limited thereto. The interfacial dielectric layer may be formed by a deposition process such as PVD, CVD, sputtering, evaporation, pulsed laser deposition, LPCVD, LTCVD, RTCVD, PECVD, HDPCVD, MOCVD, RPCVD, ALD, other suitable processes, and/or combinations thereof, although the disclosure is not limited thereto.

Next, a via (via) may be formed in the ild layer to the doped layer 205 by an etching process. The etching process may include dry etching, wet etching, Reactive Ion Etching (RIE), and/or other suitable processes, although the disclosure is not limited thereto.

After the via is formed, a conductive material may be formed in the via by a deposition process. The conductive material may include aluminum (Al), copper (Cu), gold (Au), silver (Ag), tungsten (W), cobalt (Co), ruthenium (Ru), other suitable conductive materials, or combinations thereof, but the disclosure is not limited thereto. The deposition process may include PVD, CVD, sputtering, evaporation, pulsed laser deposition, LPCVD, LTCVD, RTCVD, PECVD, HDPCVD, MOCVD, RPCVD, ALD, other suitable processes, and/or combinations thereof, although the disclosure is not limited thereto.

Next, a second metal layer M2 may be formed on the via by using an appropriate deposition process, etching process and/or photolithography process. In some embodiments, the second metal layer M2 is higher in the Z direction than the first metal layer M1. That is, the second metal layer M2 is disposed on the first metal layer M1. The second metal layer M2 may include a conductive material, such as aluminum (Al), copper (Cu), gold (Au), silver (Ag), tungsten (W), cobalt (Co), ruthenium (Ru), other suitable conductive materials, or a combination thereof, but the disclosure is not limited thereto.

In some embodiments, the photolithography process includes photoresist coating, soft baking, mask alignment, exposure, post exposure baking, developing the photoresist, rinsing, and drying. In other embodiments, the photolithography process may be performed or replaced by other suitable methods, such as maskless lithography, e-beam writing, and ion beam writing. The etching process may include dry etching, wet etching, reactive ion etching, and/or other suitable processes, but the disclosure is not limited thereto. The deposition process may include PVD, CVD, sputtering, evaporation, pulsed laser deposition, LPCVD, LTCVD, RTCVD, PECVD, HDPCVD, MOCVD, RPCVD, ALD, other suitable processes, and/or combinations thereof, although the disclosure is not limited thereto.

Fig. 5 is a top view illustrating a layout 500 of the parallel driving transistors 140 of the circuit 100 according to an embodiment of the disclosure. After the second metal layer M2 is formed, the relationship between the first metal layer M1 and the second metal layer M2 is shown in FIG. 5. Similar to the source/drain doped layer 205, in fig. 5, the first metal layer M1 and the second metal layer M2 are substantially surrounded by each other in a concentric rectangular manner. Layout 500 is similar to the elements included in layout 200 of FIG. 2, except that layout 500 shows second metal layer M2 disposed on first metal layer M1, first conductive feature 540 for connecting to the source, and second conductive feature 550 for connecting to the drain.

Referring to fig. 2 and 5, the second metal layer M2 includes a first source electrode 510 (connected to the first source doped layer 210), a first drain electrode 520 (connected to the first drain doped layer 220), a second source electrode 512 (connected to the second source doped layer 212), a second drain electrode 522 (connected to the second drain doped layer 222), a third source electrode 514 (connected to the third source doped layer 214), and a third drain electrode 524 (connected to the third source doped layer 224). As described above, the second metal layer M2 can be electrically connected to the underlying doped layer through a via (not shown).

The first source electrode 510, the first drain electrode 520, the first gate electrode 230 between the first source electrode 510 and the first drain electrode 520, and the first channel layer corresponding to the first gate electrode 230 may form a first transistor (e.g., the driving transistor 140-1). Similarly, the second source 512, the first drain 520, the second gate 232, and the second channel layer may form a second transistor (e.g., the driving transistor 140-2). Second source 512, second drain 522, third gate 234, and a third channel layer may form a third transistor (e.g., driving transistor 140-3). The second drain 522, the third source 514, the fourth gate 236, and the fourth channel layer may form a fourth transistor (e.g., the driving transistor 140-4). The third source 514, the third drain 524, the fifth gate 238, and the fifth channel layer may form a fifth transistor (e.g., the driving transistor 140-5).

In some embodiments, the transistor may further comprise a doped layer. For example, a first transistor may include the first source doped layer 210 and the first drain doped layer 220, a second transistor may include the first drain doped layer 220 and the second source doped layer 212, a third transistor may include the second source doped layer 212 and the second drain doped layer 222, a fourth transistor may include the second drain doped layer 222 and the third source doped layer 214, and a fifth transistor may include the third source doped layer 214 and the third drain doped layer 224.

In some embodiments, referring to fig. 2 and 5, the first source electrode 510 is disposed corresponding to the first source doped layer 210. The first drain electrode 520 is disposed corresponding to the first drain doped layer 220. The second source 512 is disposed corresponding to the second source doped layer 212. The second drain 522 is disposed corresponding to the second drain doped layer 222. The third source 514 is disposed corresponding to the third source doped layer 214. Third drain 524 is disposed corresponding to third drain doped layer 224. According to some embodiments, the first gate 230 surrounds the first source 510, and the first drain 520 surrounds the first gate 230. In some embodiments, the second gate 232 surrounds the first drain 520,

the second source 512 surrounds the second gate 232, the third gate 234 surrounds the second source 512, and the second drain 522 surrounds the third gate 234. In some embodiments, the fourth gate 236 surrounds the second drain 522,

the third source 514 surrounds the fourth gate 236, the fifth gate 238 surrounds the third source 514, and the third drain 524 surrounds the fifth gate 238.

According to some embodiments, five transistors (i.e., the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor) such as those described above may be connected in parallel by using conductive features, for example, referring to fig. 1 and 5, the layout 500 further includes a first conductive feature 540 for connecting the source and a second conductive feature 550 for connecting the drain. In the embodiment shown in fig. 5, the first conductive feature 540 is electrically connected to the first source 510, the second source 512, and the third source 514, for example, by a via 560. The second conductive feature 550 is electrically connected to the first drain 520, the second drain 522, and the third drain 524, for example, by a via 560. In some embodiments, the first conductive feature 540 is used to provide a source voltage for the transistor. In some embodiments, the second conductive feature 550 electrically connects the drain of the transistor to the light emitting element 160 to provide current to the light emitting element 160. For example, the first conductive feature 540 and the second conductive feature 550 may be metal layers or other conductive structures.

Similar to layout 200, in layout 500, transistors may share a source or a drain with each other. For example, the first transistor and the second transistor share a first drain 520, the second transistor and the third transistor share a second source 512, the third transistor and the fourth transistor share a second drain 522, and the fourth transistor and the fifth transistor share a third source 514.

Fig. 6 is a top view of the circuit 100, showing a layout 600 of the driving transistors 140 connected in parallel according to an embodiment of the disclosure, referring to fig. 1 and fig. 6. Layout 600 has the same elements as layout 500, such as first metal layer M1, second metal layer M2, first conductive feature 540, second conductive feature 550, and so on. Layout 600 differs from layout 500 in that first metal layer M1 and second metal layer M2 of layout 500 are disposed in a substantially concentric rectangular manner, and first metal layer M1 and second metal layer M2 of layout 600 are disposed in a substantially concentric circular manner.

The layout 600 of the driving transistor 140 also has the cross-sectional views shown in fig. 3 and 4. In fig. 6, the driving transistor 140 can be formed by a process similar to that of fig. 2 (as described above with reference to fig. 3 and 4), and thus, the description thereof is omitted here. Layout 600 may have similar advantages to layout 500 (and layout 200) due to the use of similar manufacturing processes.

Similar to layout 200, via layout 600 and the corresponding process, a channel layer and a gate insulation layer having substantially uniform thickness and a gate and channel layer having substantially the same width in a direction (e.g., X direction) perpendicular to a normal direction (e.g., Z direction) of the substrate may be formed. Thus, the gradient profile of the edge regions on both sides of the channel layer can be reduced. As shown in fig. 3 and 4, since the width of the channel layer is the same as the width of the gate, and the channel layer and the gate insulating layer have substantially uniform thickness, the edge regions at both sides of the channel layer do not have a slope profile. Therefore, the probability of generating the edge transistor or the probability of capturing the electrons or the holes by the gate insulating layer can be reduced. Therefore, the doming effect is improved or the reliability of the transistor is increased.

After the doped layer is formed by an implantation process using the gate electrode as an implantation mask, a subsequent process may be performed to form the second metal layer M2 as a source/drain electrode. In some embodiments, the second metal layer M2 may be formed by the processes described above (e.g., forming an interlayer dielectric layer, forming a via, forming a conductive material, and forming the second metal layer M2), and thus, the description thereof is omitted here.

In some other embodiments, the layout of the parallel driving transistors 140 of the circuit 100 may have shapes other than concentric rectangles (e.g., fig. 2 and 5) and concentric circles (e.g., fig. 6). For example, in other layouts, the first metal layer M1 and the second metal layer M2 may be arranged as substantially concentric ellipses, substantially concentric triangles, substantially concentric pentagons, or substantially concentric polygons, but the disclosure is not limited thereto.

In these embodiments, there are also cross-sectional views as shown in fig. 3 and 4. Therefore, in these embodiments, the channel layer has a substantially same width as the gate, and the channel layer and the gate insulating layer have substantially uniform thickness, so that the edge regions on both sides of the channel layer have no slope profile. Thus, the slope profile of the edge regions on both sides of the low channel layer can be obtained. Therefore, the probability of the generation of the edge transistor or the probability of the electrons or holes being captured by the gate insulating layer is reduced. Thus, the embodiments can improve the doming effect or increase the reliability of the transistor.

In these embodiments, the driving transistor can be formed by the same process as that shown in fig. 2 (as described above with reference to fig. 3 and 4), and thus, the description thereof is omitted here. Similarly, in these embodiments, after the doped layer is formed, a subsequent process may be performed to form a second metal layer as a source/drain electrode.

By implementing embodiments of the present disclosure having different layout shapes (e.g., concentric rectangles, concentric circles, concentric polygons, etc.), the pattern layout on the substrate may be more flexible. For example, an appropriate layout shape may be set according to the shape of an area on the substrate that has not been patterned. Thus, the limited substrate area can be more effectively utilized.

It should be noted that the transistors in the drawings of the present disclosure are all gate-top thin film transistors as examples, but in other embodiments, the transistors may be bottom-gate thin film transistors. Alternatively, in still other embodiments, the transistors may be other types of transistors besides thin film transistors.

By means of the embodiments provided by the present disclosure, a plurality of transistors (e.g., driving transistors) in a circuit of an electronic device (e.g., a display device) can be effectively integrated in a parallel manner. Thus, the total current can be increased, and the current borne by each transistor can be reduced. Therefore, the durability and the lifetime of the transistor can be improved. Also by the embodiments provided by the disclosure, the slope profile of the edge region at both sides of the channel layer can be reduced by forming the channel layer and the gate insulating layer with uniform thickness and forming the channel layer and the gate with the same width. Therefore, the probability of generating the edge transistor or the probability of capturing the electrons or the holes by the gate insulating layer can be reduced. Therefore, the doming effect is improved or the reliability of the transistor is increased.

In addition, by means of the embodiment provided by the disclosure, the transistors in parallel connection have different channel ratios, and the transistors have different current sizes. Thus, a transistor with a larger current can be used to compensate for a transistor that cannot provide enough current. Therefore, the failure rate of the circuit is reduced. Also, by using the embodiments provided by the disclosure, the pattern layout of the substrate can be made more flexible by combining the embodiments with different layout shapes. Thus, the limited substrate area can be more effectively utilized.

The foregoing text summarizes features of various embodiments or examples so as to enable those skilled in the art to better appreciate the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A display device, comprising:

a substrate;

the channel layer is arranged on the substrate and comprises a first channel layer and a second channel layer;

the first metal layer is arranged on the channel layer and comprises a first grid and a second grid; and

the second metal layer is arranged on the first metal layer and comprises a first source electrode, a first drain electrode and a second source electrode;

the first gate, the first source, the first drain and the first channel layer form a first transistor;

the second gate, the second source, the first drain and the second channel layer form a second transistor, and the first transistor and the second transistor are connected in parallel.

2. The display device according to claim 1, wherein the first gate surrounds the first source and the first drain surrounds the first gate in a top view direction.

3. The display device of claim 1, wherein a first channel width to channel length ratio of a channel width to a channel length of the first channel layer of the first transistor is different from a second channel width to channel length ratio of the second channel layer of the second transistor.

4. The display device according to claim 1, wherein the substrate has a normal direction, and the width of the first channel layer is the same as the width of the first gate electrode in a direction perpendicular to the normal direction.

5. The display device according to claim 4, wherein a width of the second channel layer is the same as a width of the second gate electrode in a direction perpendicular to the normal direction.

6. The display device of claim 1, wherein the channel layer further comprises a third channel layer, the first metal layer further comprises a third gate, the second metal layer further comprises a second drain, and the third channel layer, the third gate, the second source, and the second drain form a third transistor, and the third transistor is connected in parallel with the first transistor and the second transistor.

7. The display device according to claim 6, wherein the second gate surrounds the first drain, the second source surrounds the second gate, the third gate surrounds the second source, and the second drain surrounds the third gate.

8. The display device of claim 6, wherein the second channel layer surrounds the first channel layer and the third channel layer surrounds the second channel layer.

9. The display device of claim 1, further comprising a first conductive feature electrically connected to the first source and the second source.

10. The display device of claim 6, further comprising a second conductive feature electrically connected to the first drain and the second drain.